msm: acpuclock-8064: Update L2 voltage table
Characterization data shows that L2 runs up to 667MHz with vdd_cx at 1.05v.
Therefore, update the L2 voltage table to match the new data.
In addition, update acpuclock table to use the updated max L2 frequency
with vdd_cx at 1.05v.
Change-Id: I05ce13b9050a4b084d10a8f15dfa3bfe40d5fbe5
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
(cherry picked from commit 222732641a6b3a7eb81244c994c7d88435bedb45)
Signed-off-by: Dhivya Subramanian <dthiru@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index c171b86..359a156 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -122,7 +122,7 @@
[3] = { { 540000, HFPLL, 2, 0x28 }, 1050000, 1050000, 2 },
[4] = { { 594000, HFPLL, 1, 0x16 }, 1050000, 1050000, 2 },
[5] = { { 648000, HFPLL, 1, 0x18 }, 1050000, 1050000, 4 },
- [6] = { { 702000, HFPLL, 1, 0x1A }, 1050000, 1050000, 4 },
+ [6] = { { 702000, HFPLL, 1, 0x1A }, 1150000, 1150000, 4 },
[7] = { { 756000, HFPLL, 1, 0x1C }, 1150000, 1150000, 4 },
[8] = { { 810000, HFPLL, 1, 0x1E }, 1150000, 1150000, 4 },
[9] = { { 864000, HFPLL, 1, 0x20 }, 1150000, 1150000, 4 },
@@ -137,18 +137,18 @@
static struct acpu_level tbl_slow[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 975000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 975000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 1000000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 1000000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 1025000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 1025000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 1075000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 1075000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1100000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1100000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1125000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1075000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1100000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1125000 },
{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
{ 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
@@ -163,18 +163,18 @@
static struct acpu_level tbl_nom[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 925000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 925000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 950000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 950000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 975000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 975000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 1025000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 1025000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1050000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1050000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1075000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1075000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 950000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 975000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 975000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 1025000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1025000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1050000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1050000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1075000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1075000 },
{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1125000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1125000 },
{ 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1150000 },
@@ -189,18 +189,18 @@
static struct acpu_level tbl_fast[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 925000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 975000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 975000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1000000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1000000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1025000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1025000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 925000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 975000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 975000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1000000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1000000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1025000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1025000 },
{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1075000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1075000 },
{ 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1100000 },
@@ -215,18 +215,18 @@
static struct acpu_level tbl_faster[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 925000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 962500 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 962500 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 975000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 975000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1000000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1000000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 925000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 962500 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 962500 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 975000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 975000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1000000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1000000 },
{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1050000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1050000 },
{ 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1075000 },
@@ -353,12 +353,12 @@
static struct acpu_level tbl_PVS0_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 950000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 950000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 962500 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 1000000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1025000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1037500 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 962500 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1000000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1025000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1037500 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1075000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1087500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1125000 },
@@ -371,12 +371,12 @@
static struct acpu_level tbl_PVS1_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 950000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 950000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 962500 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 975000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1000000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1012500 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 962500 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 975000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1000000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1012500 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1037500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1050000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1087500 },
@@ -389,12 +389,12 @@
static struct acpu_level tbl_PVS2_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 925000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 925000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 937500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 950000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 937500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 950000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 975000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1000000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1012500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1037500 },
@@ -407,12 +407,12 @@
static struct acpu_level tbl_PVS3_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 900000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 925000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 950000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 900000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 925000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 950000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 975000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 987500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1000000 },
@@ -425,12 +425,12 @@
static struct acpu_level tbl_PVS4_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 950000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 962500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 975000 },
@@ -443,12 +443,12 @@
static struct acpu_level tbl_PVS5_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 937500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 950000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 962500 },
@@ -461,12 +461,12 @@
static struct acpu_level tbl_PVS6_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 937500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 950000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 962500 },
@@ -479,12 +479,12 @@
static struct acpu_level tbl_PVS0_2000MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 950000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 950000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 950000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 962500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 975000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1000000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 950000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 962500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 975000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1000000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1025000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1037500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1062500 },
@@ -498,12 +498,12 @@
static struct acpu_level tbl_PVS1_2000MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 925000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 925000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 937500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 950000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 937500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 950000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 975000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1000000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1012500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1037500 },
@@ -517,12 +517,12 @@
static struct acpu_level tbl_PVS2_2000MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 912500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 925000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 950000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 912500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 925000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 950000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 975000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 987500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1012500 },
@@ -536,12 +536,12 @@
static struct acpu_level tbl_PVS3_2000MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 900000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 912500 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 937500 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 900000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 912500 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 937500 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 962500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 975000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1000000 },
@@ -555,12 +555,12 @@
static struct acpu_level tbl_PVS4_2000MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 950000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 962500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 975000 },
@@ -574,12 +574,12 @@
static struct acpu_level tbl_PVS5_2000MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 937500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 950000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 962500 },
@@ -593,12 +593,12 @@
static struct acpu_level tbl_PVS6_2000MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 937500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 950000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 962500 },