)]}'
{
  "commit": "30962d9d0c74f6b00a7dece200fa08392b62817d",
  "tree": "72c1e60fd4f42c244fb8fe9c68f8e3d95a880edb",
  "parents": [
    "4d30e82c26b7212021b9a5ab57760d9b8a3075fe"
  ],
  "author": {
    "name": "Paul Walmsley",
    "email": "paul@pwsan.com",
    "time": "Mon Feb 22 22:09:38 2010 -0700"
  },
  "committer": {
    "name": "Paul Walmsley",
    "email": "paul@pwsan.com",
    "time": "Wed Feb 24 17:45:16 2010 -0700"
  },
  "message": "OMAP2+ clock: revise omap2_clk_{disable,enable}()\n\nSimplify the code in the omap2_clk_disable() and omap2_clk_enable()\nfunctions, reducing levels of indentation.  This makes the code easier\nto read.  Add some additional debugging pr_debug()s here also to help\nothers understand what is going on.\n\nRevise the omap2_clk_disable() logic so that it now attempts to\ndisable the clock\u0027s clockdomain before recursing up the clock tree.\nSimultaneously, ensure that omap2_clk_enable() is called on parent\nclocks first, before enabling the clockdomain.  This ensures that a\nparent clock\u0027s clockdomain is enabled before the child clock\u0027s\nclockdomain.  These sequences should be the inverse of each other.\n\nRevise the omap2_clk_enable() logic so that it now cleans up after\nitself upon encountering an error.  Previously, an error enabling a\nparent clock could have resulted in inconsistent usecounts on the\nenclosing clockdomain.\n\nRemove the trivial _omap2_clk_disable() and _omap2_clk_enable() static\nfunctions, and replace it with the clkops calls that they were\nexecuting.\n\nFor all this to work, the clockdomain omap2_clkdm_clk_enable() and\nomap2_clkdm_clk_disable() code must not return an error on clockdomains\nwithout CLKSTCTRL registers; so modify those functions to simply return 0\nin that case.\n\nWhile here, add some basic kerneldoc documentation on both functions,\nand get rid of some old non-CodingStyle-compliant comments that have\nexisted since the dawn of time (at least, the OMAP clock framework\u0027s\ntime).\n\nSigned-off-by: Paul Walmsley \u003cpaul@pwsan.com\u003e\nCc: Richard Woodruff \u003cr-woodruff2@ti.com\u003e\nCc: Rajendra Nayak \u003crnayak@ti.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d1f115d0edadb871b5132fd6a3bd4ba56e705e0e",
      "old_mode": 33188,
      "old_path": "arch/arm/mach-omap2/clock.c",
      "new_id": "a6d0b34b799091cd1f0299225d60f8c181db204a",
      "new_mode": 33188,
      "new_path": "arch/arm/mach-omap2/clock.c"
    },
    {
      "type": "modify",
      "old_id": "b26d30a14303646f8f9eee15a8298b4072bd669e",
      "old_mode": 33188,
      "old_path": "arch/arm/mach-omap2/clockdomain.c",
      "new_id": "b87ad66f083ee12ae2a47066a6746faf7ee3a747",
      "new_mode": 33188,
      "new_path": "arch/arm/mach-omap2/clockdomain.c"
    }
  ]
}