)]}'
{
  "commit": "30aacebed0f0619f23ce84df7c59ad033ca08d77",
  "tree": "fb32292e6804fdab515227a0b7d9722e9595d532",
  "parents": [
    "1269277a5e7c6d7ae1852e648a8bcdb78035e9fa"
  ],
  "author": {
    "name": "Eugene Surovegin",
    "email": "ebs@ebshome.net",
    "time": "Tue Apr 25 01:22:44 2006 -0700"
  },
  "committer": {
    "name": "Paul Mackerras",
    "email": "paulus@samba.org",
    "time": "Fri Apr 28 21:04:56 2006 +1000"
  },
  "message": "[PATCH] ppc32: add 440GX erratum 440_43 workaround\n\nThis patch adds workaround for PPC 440GX erratum 440_43. According to\nthis erratum spurious MachineChecks (caused by L1 cache parity) can\nhappen during DataTLB miss processing. We disable L1 cache parity\nchecking for 440GX rev.C and rev.F\n\nSigned-off-by: Eugene Surovegin \u003cebs@ebshome.net\u003e\nSigned-off-by: Paul Mackerras \u003cpaulus@samba.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f841972f1fa9204238a49dd841c70839601d46c6",
      "old_mode": 33188,
      "old_path": "arch/ppc/platforms/4xx/ocotea.c",
      "new_id": "554776d4b8ac79f573183e93b31e22c7c331ee18",
      "new_mode": 33188,
      "new_path": "arch/ppc/platforms/4xx/ocotea.c"
    },
    {
      "type": "modify",
      "old_id": "a7dd55f1c63e126f604227f249aefe648039d2db",
      "old_mode": 33188,
      "old_path": "arch/ppc/syslib/ibm440gx_common.c",
      "new_id": "f6cc16888527fd159e017a76f524253ab8c441ff",
      "new_mode": 33188,
      "new_path": "arch/ppc/syslib/ibm440gx_common.c"
    },
    {
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      "old_mode": 33188,
      "old_path": "arch/ppc/syslib/ibm440gx_common.h",
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      "new_mode": 33188,
      "new_path": "arch/ppc/syslib/ibm440gx_common.h"
    },
    {
      "type": "modify",
      "old_id": "00ad9c754c789b580a05f07110f7f4fccae9202c",
      "old_mode": 33188,
      "old_path": "include/asm-ppc/reg_booke.h",
      "new_id": "4944c0fb8beaf403fb7788cffaf94fb9924276db",
      "new_mode": 33188,
      "new_path": "include/asm-ppc/reg_booke.h"
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  ]
}