)]}'
{
  "commit": "345077cd98ff5532b2d1158013c3fec7b1ae85ec",
  "tree": "b26a683fca5fcb39f5646219fceecb5a168eec77",
  "parents": [
    "40fb17152c50a69dc304dd632131c2f41281ce44"
  ],
  "author": {
    "name": "Suresh Siddha",
    "email": "suresh.b.siddha@intel.com",
    "time": "Thu Dec 18 18:09:21 2008 -0800"
  },
  "committer": {
    "name": "Ingo Molnar",
    "email": "mingo@elte.hu",
    "time": "Fri Dec 19 09:13:50 2008 +0100"
  },
  "message": "x86: fix intel x86_64 llc_shared_map/cpu_llc_id anomolies\n\nImpact: fix wrong cache sharing detection on platforms supporting \u003e 8 bit apicid\u0027s\n\nIn the presence of extended topology eumeration leaf 0xb provided\nby cpuid, 32bit extended initial_apicid in cpuinfo_x86 struct will be\nupdated by detect_extended_topology(). At this instance, we should also\nreinit the apicid (which could also potentially be extended to 32bit).\n\nWith out this there will potentially be duplicate apicid\u0027s populated in the\nper cpu\u0027s cpuinfo_x86 struct, resulting in wrong cache sharing topology etc\ndetected by init_intel_cacheinfo().\n\nReported-by: Dimitri Sivanich \u003csivanich@sgi.com\u003e\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nAcked-by: Dimitri Sivanich \u003csivanich@sgi.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: \u003cstable@kernel.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ef8f831af823a89530297919585e50c9a691e804",
      "old_mode": 33188,
      "old_path": "arch/x86/kernel/cpu/addon_cpuid_features.c",
      "new_id": "2cf23634b6d94d60e239d3f63cd9d4d21526b3fd",
      "new_mode": 33188,
      "new_path": "arch/x86/kernel/cpu/addon_cpuid_features.c"
    },
    {
      "type": "modify",
      "old_id": "caec59437a228f7dd47022100d57f6caaf6e5ab8",
      "old_mode": 33188,
      "old_path": "arch/x86/kernel/cpu/intel.c",
      "new_id": "b21c37c060a243a78c62bf71f6932ada79d64cb4",
      "new_mode": 33188,
      "new_path": "arch/x86/kernel/cpu/intel.c"
    }
  ]
}