commit 358c386e9af5eefe922a729cfe965d175aa5d3c3
author Tianyi Gou <tgou@codeaurora.org> Tue Oct 18 17:03:41 2011 -0700
committer Linux Build Service Account <lnxbuild@localhost> Mon Oct 24 22:59:21 2011 -0600
tree 860f338851697cab9bb504648f296b26264a56d6
parent 4ec8b162a06dbfe4e35bc9379be30bacbe8f8344

msm: clock-8960: Clean up code to program PLL for 8064

Fix mislabeled register for lock count. Program bias count for FSM PLLs.
Disable PLLs AUX output if no clocks use them.

Change-Id: If3dc9c378baa93c6c6097bd4a53486deee20b74c
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>

arch/arm/mach-msm/clock-8960.c

diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index ee122ec..4c0fd07 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -5441,6 +5441,11 @@
 	writel_relaxed(regval, mode_reg);
 
 	/* Program bias count */
+	regval &= ~BM(19, 14);
+	regval |= BVAL(19, 14, 0x1);
+	writel_relaxed(regval, mode_reg);
+
+	/* Program lock count */
 	regval &= ~BM(13, 8);
 	regval |= BVAL(13, 8, 0x8);
 	writel_relaxed(regval, mode_reg);
@@ -5641,11 +5646,6 @@
 			/* Set VCO frequency */
 			rmwreg(0x10000, BB_PLL14_CONFIG_REG, 0x30000);
 
-			/* Enable AUX output */
-			regval = readl_relaxed(BB_PLL14_TEST_CTL_REG);
-			regval |= BIT(12);
-			writel_relaxed(regval, BB_PLL14_TEST_CTL_REG);
-
 			set_fsm_mode(BB_PLL14_MODE_REG);
 		}
 		/* Program PLL2 to 800MHz with ref clk = 27MHz */
@@ -5667,11 +5667,6 @@
 		/* Set VCO frequency */
 		rmwreg(0x20000, MM_PLL1_CONFIG_REG, 0x30000);
 
-		/* Enable AUX output */
-		regval = readl_relaxed(MM_PLL1_TEST_CTL_REG);
-		regval |= BIT(12);
-		writel_relaxed(regval, MM_PLL1_TEST_CTL_REG);
-
 		/* Program PLL15 to 975MHz with ref clk = 27MHz */
 		writel_relaxed(0x24, MM_PLL3_L_VAL_REG);
 		writel_relaxed(0x1,  MM_PLL3_M_VAL_REG);