commit 387ac2ea3542646d8ddcf112e5cc185c60bf52ec
author Stephen Boyd <sboyd@codeaurora.org> Wed Sep 28 10:29:43 2011 -0700
committer Bryan Huntsman <bryanh@codeaurora.org> Mon Oct 03 16:21:36 2011 -0700
tree 757f8462680d3d88ae38dbfcc341830544bb195e
parent 343cbb0c549c5445e04064e67a574fd645a6325a

msm: krait-l2-accessor: Use acpuclock-8960 implementation

The implementation of these function in acpuclock-8960.c is more
tried and tested. It also includes the appropriate barriers and
rumi3 checks so copy that implementation here.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

arch/arm/mach-msm/msm-krait-l2-accessors.c

diff --git a/arch/arm/mach-msm/msm-krait-l2-accessors.c b/arch/arm/mach-msm/msm-krait-l2-accessors.c
index 7ba19ab..61b5228 100644
--- a/arch/arm/mach-msm/msm-krait-l2-accessors.c
+++ b/arch/arm/mach-msm/msm-krait-l2-accessors.c
@@ -12,6 +12,7 @@
  */
 
 #include <linux/spinlock.h>
+#include <asm/mach-types.h>
 
 DEFINE_RAW_SPINLOCK(l2_access_lock);
 
@@ -19,13 +20,19 @@
 {
 	unsigned long flags;
 	u32 ret_val;
+	/* CP15 registers are not emulated on RUMI3. */
+	if (machine_is_msm8960_rumi3())
+		return 0;
 
 	raw_spin_lock_irqsave(&l2_access_lock, flags);
 
-	asm volatile ("mcr p15, 3, %0, c15, c0, 6" : : "r" (reg_addr));
-
-	asm volatile ("mcr p15, 3, %0, c15, c0, 7" : : "r" (val));
-
+	mb();
+	asm volatile ("mcr     p15, 3, %[l2cpselr], c15, c0, 6\n\t"
+		      "mcr     p15, 3, %[l2cpdr],   c15, c0, 7\n\t"
+			:
+			: [l2cpselr]"r" (reg_addr), [l2cpdr]"r" (val)
+	);
+	isb();
 	/* Ensure the value took */
 	asm volatile ("mrc p15, 3, %0, c15, c0, 7" : "=r" (ret_val));
 
@@ -37,13 +44,18 @@
 void set_l2_indirect_reg(u32 reg_addr, u32 val)
 {
 	unsigned long flags;
+	/* CP15 registers are not emulated on RUMI3. */
+	if (machine_is_msm8960_rumi3())
+		return;
 
 	raw_spin_lock_irqsave(&l2_access_lock, flags);
-
-	asm volatile ("mcr p15, 3, %0, c15, c0, 6" : : "r" (reg_addr));
-
-	asm volatile ("mcr p15, 3, %0, c15, c0, 7" : : "r" (val));
-
+	mb();
+	asm volatile ("mcr     p15, 3, %[l2cpselr], c15, c0, 6\n\t"
+		      "mcr     p15, 3, %[l2cpdr],   c15, c0, 7\n\t"
+			:
+			: [l2cpselr]"r" (reg_addr), [l2cpdr]"r" (val)
+	);
+	isb();
 	raw_spin_unlock_irqrestore(&l2_access_lock, flags);
 }
 
@@ -51,13 +63,16 @@
 {
 	u32 val;
 	unsigned long flags;
+	/* CP15 registers are not emulated on RUMI3. */
+	if (machine_is_msm8960_rumi3())
+		return 0;
 
 	raw_spin_lock_irqsave(&l2_access_lock, flags);
-
-	asm volatile ("mcr p15, 3, %0, c15, c0, 6" : : "r" (reg_addr));
-
-	asm volatile ("mrc p15, 3, %0, c15, c0, 7" : "=r" (val));
-
+	asm volatile ("mcr     p15, 3, %[l2cpselr], c15, c0, 6\n\t"
+		      "mrc     p15, 3, %[l2cpdr],   c15, c0, 7\n\t"
+			: [l2cpdr]"=r" (val)
+			: [l2cpselr]"r" (reg_addr)
+	);
 	raw_spin_unlock_irqrestore(&l2_access_lock, flags);
 
 	return val;