ARM: cache-l2x0: Save L2CC registers using pl310 save/resume
This reverts commit a022290fe5165ffe4973355cb76556ce8c629d70.
Save the contents of the L2CC registers in l2x0_init itself as
they are not modified later.
CRs-Fixed: 356696
Change-Id: I05ec3bcce8d1e2f941a9ecbaae8c6598f52831c5
Signed-off-by: Taniya Das <tdas@codeaurora.org>
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index db2a9b4..e81f881 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -2,7 +2,7 @@
* arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
*
* Copyright (C) 2007 ARM Limited
- * Copyright (c) 2009, 2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009, 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -30,8 +30,6 @@
#define CACHE_LINE_SIZE 32
static void __iomem *l2x0_base;
-static uint32_t aux_ctrl_save;
-static uint32_t data_latency_ctrl;
static DEFINE_RAW_SPINLOCK(l2x0_lock);
static uint32_t l2x0_way_mask; /* Bitmask of active ways */
@@ -39,6 +37,7 @@
static u32 l2x0_cache_id;
static unsigned int l2x0_sets;
static unsigned int l2x0_ways;
+static void pl310_save(void);
static inline bool is_pl310_rev(int rev)
{
@@ -447,51 +446,9 @@
printk(KERN_INFO "%s cache controller enabled\n", type);
printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
ways, cache_id, aux, l2x0_size);
-}
-void l2x0_suspend(void)
-{
- /* Save aux control register value */
- aux_ctrl_save = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
- data_latency_ctrl = readl_relaxed(l2x0_base + L2X0_DATA_LATENCY_CTRL);
- /* Flush all cache */
- l2x0_flush_all();
- /* Disable the cache */
- writel_relaxed(0, l2x0_base + L2X0_CTRL);
-
- /* Memory barrier */
- dmb();
-}
-
-void l2x0_resume(int collapsed)
-{
- if (collapsed) {
- /* Disable the cache */
- writel_relaxed(0, l2x0_base + L2X0_CTRL);
-
- /* Restore aux control register value */
- writel_relaxed(aux_ctrl_save, l2x0_base + L2X0_AUX_CTRL);
- writel_relaxed(data_latency_ctrl, l2x0_base +
- L2X0_DATA_LATENCY_CTRL);
-
- /* Invalidate the cache */
- l2x0_inv_all();
- /*
- * TBD: make sure that l2xo_inv_all finished
- * before actually enabling the cache. Logically this
- * is not required as cache sync is atomic operation.
- * but on 8x25, observed the random crashes and they go
- * away if we add dmb or disable the L2.
- * keeping this as temporary workaround until root
- * cause is find out.
- */
- dmb();
- }
-
- /* Enable the cache */
- writel_relaxed(1, l2x0_base + L2X0_CTRL);
-
- mb();
+ /* Save the L2X0 contents, as they are not modified else where */
+ pl310_save();
}
#ifdef CONFIG_OF
@@ -562,6 +519,7 @@
l2x0_base + L2X0_ADDR_FILTER_START);
}
}
+#endif
static void pl310_save(void)
{
@@ -637,6 +595,7 @@
l2x0_resume();
}
+#ifdef CONFIG_OF
static const struct l2x0_of_data pl310_data = {
pl310_of_setup,
pl310_save,
@@ -692,3 +651,15 @@
return 0;
}
#endif
+
+void l2cc_suspend(void)
+{
+ l2x0_disable();
+ dmb();
+}
+
+void l2cc_resume(void)
+{
+ pl310_resume();
+ dmb();
+}