)]}'
{
  "commit": "399de50bbbb2501a6db43daaa8a2dafbc9bcfe0c",
  "tree": "1c4e6034b0d5485c4ed3d010acc2d60d52ec2ed8",
  "parents": [
    "a232f76732e11c91c2215d3a43cf9ebc7f939939"
  ],
  "author": {
    "name": "Michael Chan",
    "email": "mchan@broadcom.com",
    "time": "Mon Oct 03 14:02:39 2005 -0700"
  },
  "committer": {
    "name": "David S. Miller",
    "email": "davem@davemloft.net",
    "time": "Mon Oct 03 14:02:39 2005 -0700"
  },
  "message": "[TG3]: Refine AMD K8 write-reorder chipset test.\n\nTest for VIA K8T800 north bridge instead of AMD K8 HyperTransport\nbridge based on new information from Andi Kleen. The AMD\nHyperTransport interface is not responsible for PCI transactions\nand so the re-ordering is more likely done by the VIA north bridge.\nThis code is subject to change if we get more information from AMD\nor VIA.\n\nPCI Express devices are excluded from doing the read flush since all\nchipsets in the write_reorder list are PCI chipsets.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "25f85fb9df46d33b16fafa3f0be04b2dd757aef6",
      "old_mode": 33188,
      "old_path": "drivers/net/tg3.c",
      "new_id": "fee0e6e5ff1e5e00106de7cf9ddc12d884184e1a",
      "new_mode": 33188,
      "new_path": "drivers/net/tg3.c"
    }
  ]
}