commit 3f2bc4d6eb5a4fada842462ba22bb6bbb41d00c7
author Bryan Huntsman <bryanh@codeaurora.org> Tue Aug 16 17:27:22 2011 -0700
committer Bryan Huntsman <bryanh@codeaurora.org> Mon Oct 03 09:57:10 2011 -0700
tree 088e0646c8abcbde263d13ee865ba69032ac86dd
parent f06154cc47399dfdb3950d3e6b71d67ee186f69d

Initial Contribution

msm-2.6.38: tag AU_LINUX_ANDROID_GINGERBREAD.02.03.04.00.142

Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>

arch/arm/kernel/perf_event.c

diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 2b5b142..c998282 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -19,6 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/uaccess.h>
+#include <linux/irq.h>
 
 #include <asm/cputype.h>
 #include <asm/irq.h>
@@ -71,6 +72,10 @@
 	enum arm_perf_pmu_ids id;
 	const char	*name;
 	irqreturn_t	(*handle_irq)(int irq_num, void *dev);
+#ifdef CONFIG_SMP
+	void            (*secondary_enable)(unsigned int irq);
+	void            (*secondary_disable)(unsigned int irq);
+#endif
 	void		(*enable)(struct hw_perf_event *evt, int idx);
 	void		(*disable)(struct hw_perf_event *evt, int idx);
 	int		(*get_event_idx)(struct cpu_hw_events *cpuc,
@@ -426,6 +431,10 @@
 			pr_warning("unable to request IRQ%d for ARM perf "
 				"counters\n", irq);
 			break;
+#ifdef CONFIG_SMP
+		} else if (armpmu->secondary_enable) {
+			armpmu->secondary_enable(irq);
+#endif
 		}
 	}
 
@@ -449,8 +458,13 @@
 
 	for (i = pmu_device->num_resources - 1; i >= 0; --i) {
 		irq = platform_get_irq(pmu_device, i);
-		if (irq >= 0)
+		if (irq >= 0) {
 			free_irq(irq, NULL);
+#ifdef CONFIG_SMP
+			if (armpmu->secondary_disable)
+				armpmu->secondary_disable(irq);
+#endif
+		}
 	}
 	armpmu->stop();
 
@@ -624,6 +638,10 @@
 #include "perf_event_xscale.c"
 #include "perf_event_v6.c"
 #include "perf_event_v7.c"
+#include "perf_event_msm.c"
+#include "perf_event_msm_l2.c"
+#include "perf_event_msm_krait.c"
+#include "perf_event_msm_krait_l2.c"
 
 /*
  * Ensure the PMU has sane values out of reset.
@@ -674,6 +692,22 @@
 			armpmu = xscale2pmu_init();
 			break;
 		}
+	/* Qualcomm CPUs */
+	} else if (0x51 == implementor) {
+		switch (part_number) {
+		case 0x00F0:    /* 8x50 & 7x30*/
+			armpmu = armv7_scorpion_pmu_init();
+			break;
+		case 0x02D0:    /* 8x60 */
+			armpmu = armv7_scorpionmp_pmu_init();
+			scorpionmp_l2_pmu_init();
+			break;
+		case 0x0490:    /* 8960 sim */
+		case 0x04D0:    /* 8960 */
+			armpmu = armv7_krait_pmu_init();
+			krait_l2_pmu_init();
+			break;
+		}
 	}
 
 	if (armpmu) {