Initial Contribution
msm-2.6.38: tag AU_LINUX_ANDROID_GINGERBREAD.02.03.04.00.142
Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
new file mode 100644
index 0000000..88160be
--- /dev/null
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -0,0 +1,699 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/msm_kgsl.h>
+#include <linux/regulator/machine.h>
+#include <mach/irqs.h>
+#include <mach/msm_iomap.h>
+#include <mach/board.h>
+#include <mach/dma.h>
+#include <mach/dal_axi.h>
+#include <asm/mach/flash.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/mmc.h>
+#include <mach/rpc_hsusb.h>
+#include <mach/socinfo.h>
+
+#include "devices.h"
+#include "devices-msm7x2xa.h"
+#include "footswitch.h"
+
+/* Address of GSBI blocks */
+#define MSM_GSBI0_PHYS 0xA1200000
+#define MSM_GSBI1_PHYS 0xA1300000
+
+/* GSBI QUPe devices */
+#define MSM_GSBI0_QUP_PHYS (MSM_GSBI0_PHYS + 0x80000)
+#define MSM_GSBI1_QUP_PHYS (MSM_GSBI1_PHYS + 0x80000)
+
+static struct resource gsbi0_qup_i2c_resources[] = {
+ {
+ .name = "qup_phys_addr",
+ .start = MSM_GSBI0_QUP_PHYS,
+ .end = MSM_GSBI0_QUP_PHYS + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "gsbi_qup_i2c_addr",
+ .start = MSM_GSBI0_PHYS,
+ .end = MSM_GSBI0_PHYS + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "qup_err_intr",
+ .start = INT_PWB_I2C,
+ .end = INT_PWB_I2C,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/* Use GSBI0 QUP for /dev/i2c-0 */
+struct platform_device msm_gsbi0_qup_i2c_device = {
+ .name = "qup_i2c",
+ .id = MSM_GSBI0_QUP_I2C_BUS_ID,
+ .num_resources = ARRAY_SIZE(gsbi0_qup_i2c_resources),
+ .resource = gsbi0_qup_i2c_resources,
+};
+
+static struct resource gsbi1_qup_i2c_resources[] = {
+ {
+ .name = "qup_phys_addr",
+ .start = MSM_GSBI1_QUP_PHYS,
+ .end = MSM_GSBI1_QUP_PHYS + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "gsbi_qup_i2c_addr",
+ .start = MSM_GSBI1_PHYS,
+ .end = MSM_GSBI1_PHYS + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "qup_err_intr",
+ .start = INT_ARM11_DMA,
+ .end = INT_ARM11_DMA,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/* Use GSBI1 QUP for /dev/i2c-1 */
+struct platform_device msm_gsbi1_qup_i2c_device = {
+ .name = "qup_i2c",
+ .id = MSM_GSBI1_QUP_I2C_BUS_ID,
+ .num_resources = ARRAY_SIZE(gsbi1_qup_i2c_resources),
+ .resource = gsbi1_qup_i2c_resources,
+};
+
+#define MSM_HSUSB_PHYS 0xA0800000
+static struct resource resources_hsusb_otg[] = {
+ {
+ .start = MSM_HSUSB_PHYS,
+ .end = MSM_HSUSB_PHYS + SZ_1K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_USB_HS,
+ .end = INT_USB_HS,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 dma_mask = 0xffffffffULL;
+struct platform_device msm_device_otg = {
+ .name = "msm_otg",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(resources_hsusb_otg),
+ .resource = resources_hsusb_otg,
+ .dev = {
+ .dma_mask = &dma_mask,
+ .coherent_dma_mask = 0xffffffffULL,
+ },
+};
+
+static struct resource resources_gadget_peripheral[] = {
+ {
+ .start = MSM_HSUSB_PHYS,
+ .end = MSM_HSUSB_PHYS + SZ_1K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_USB_HS,
+ .end = INT_USB_HS,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device msm_device_gadget_peripheral = {
+ .name = "msm_hsusb",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(resources_gadget_peripheral),
+ .resource = resources_gadget_peripheral,
+ .dev = {
+ .dma_mask = &dma_mask,
+ .coherent_dma_mask = 0xffffffffULL,
+ },
+};
+
+static struct resource resources_hsusb_host[] = {
+ {
+ .start = MSM_HSUSB_PHYS,
+ .end = MSM_HSUSB_PHYS + SZ_1K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_USB_HS,
+ .end = INT_USB_HS,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device msm_device_hsusb_host = {
+ .name = "msm_hsusb_host",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(resources_hsusb_host),
+ .resource = resources_hsusb_host,
+ .dev = {
+ .dma_mask = &dma_mask,
+ .coherent_dma_mask = 0xffffffffULL,
+ },
+};
+
+static struct platform_device *msm_host_devices[] = {
+ &msm_device_hsusb_host,
+};
+
+int msm_add_host(unsigned int host, struct msm_usb_host_platform_data *plat)
+{
+ struct platform_device *pdev;
+
+ pdev = msm_host_devices[host];
+ if (!pdev)
+ return -ENODEV;
+ pdev->dev.platform_data = plat;
+ return platform_device_register(pdev);
+}
+
+static struct resource msm_dmov_resource[] = {
+ {
+ .start = INT_ADM_AARM,
+ .end = (resource_size_t)MSM_DMOV_BASE,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device msm_device_dmov = {
+ .name = "msm_dmov",
+ .id = -1,
+ .resource = msm_dmov_resource,
+ .num_resources = ARRAY_SIZE(msm_dmov_resource),
+};
+
+struct platform_device msm_device_smd = {
+ .name = "msm_smd",
+ .id = -1,
+};
+
+static struct resource resources_uart1[] = {
+ {
+ .start = INT_UART1,
+ .end = INT_UART1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = MSM_UART1_PHYS,
+ .end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device msm_device_uart1 = {
+ .name = "msm_serial",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(resources_uart1),
+ .resource = resources_uart1,
+};
+
+#define MSM_UART1DM_PHYS 0xA0200000
+static struct resource msm_uart1_dm_resources[] = {
+ {
+ .start = MSM_UART1DM_PHYS,
+ .end = MSM_UART1DM_PHYS + PAGE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_UART1DM_IRQ,
+ .end = INT_UART1DM_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = INT_UART1DM_RX,
+ .end = INT_UART1DM_RX,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = DMOV_HSUART1_TX_CHAN,
+ .end = DMOV_HSUART1_RX_CHAN,
+ .name = "uartdm_channels",
+ .flags = IORESOURCE_DMA,
+ },
+ {
+ .start = DMOV_HSUART1_TX_CRCI,
+ .end = DMOV_HSUART1_RX_CRCI,
+ .name = "uartdm_crci",
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static u64 msm_uart_dm1_dma_mask = DMA_BIT_MASK(32);
+struct platform_device msm_device_uart_dm1 = {
+ .name = "msm_serial_hs",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(msm_uart1_dm_resources),
+ .resource = msm_uart1_dm_resources,
+ .dev = {
+ .dma_mask = &msm_uart_dm1_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+#define MSM_UART2DM_PHYS 0xA0300000
+static struct resource msm_uart2dm_resources[] = {
+ {
+ .start = MSM_UART2DM_PHYS,
+ .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1,
+ .name = "uartdm_resource",
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_UART2DM_IRQ,
+ .end = INT_UART2DM_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device msm_device_uart_dm2 = {
+ .name = "msm_serial_hsl",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(msm_uart2dm_resources),
+ .resource = msm_uart2dm_resources,
+};
+
+#define MSM_NAND_PHYS 0xA0A00000
+#define MSM_NANDC01_PHYS 0xA0A40000
+#define MSM_NANDC10_PHYS 0xA0A80000
+#define MSM_NANDC11_PHYS 0xA0AC0000
+#define EBI2_REG_BASE 0xA0D00000
+static struct resource resources_nand[] = {
+ [0] = {
+ .name = "msm_nand_dmac",
+ .start = DMOV_NAND_CHAN,
+ .end = DMOV_NAND_CHAN,
+ .flags = IORESOURCE_DMA,
+ },
+ [1] = {
+ .name = "msm_nand_phys",
+ .start = MSM_NAND_PHYS,
+ .end = MSM_NAND_PHYS + 0x7FF,
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ .name = "msm_nandc01_phys",
+ .start = MSM_NANDC01_PHYS,
+ .end = MSM_NANDC01_PHYS + 0x7FF,
+ .flags = IORESOURCE_MEM,
+ },
+ [3] = {
+ .name = "msm_nandc10_phys",
+ .start = MSM_NANDC10_PHYS,
+ .end = MSM_NANDC10_PHYS + 0x7FF,
+ .flags = IORESOURCE_MEM,
+ },
+ [4] = {
+ .name = "msm_nandc11_phys",
+ .start = MSM_NANDC11_PHYS,
+ .end = MSM_NANDC11_PHYS + 0x7FF,
+ .flags = IORESOURCE_MEM,
+ },
+ [5] = {
+ .name = "ebi2_reg_base",
+ .start = EBI2_REG_BASE,
+ .end = EBI2_REG_BASE + 0x60,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct flash_platform_data msm_nand_data;
+
+struct platform_device msm_device_nand = {
+ .name = "msm_nand",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(resources_nand),
+ .resource = resources_nand,
+ .dev = {
+ .platform_data = &msm_nand_data,
+ },
+};
+
+#define MSM_SDC1_BASE 0xA0400000
+#define MSM_SDC2_BASE 0xA0500000
+#define MSM_SDC3_BASE 0xA0600000
+#define MSM_SDC4_BASE 0xA0700000
+static struct resource resources_sdc1[] = {
+ {
+ .start = MSM_SDC1_BASE,
+ .end = MSM_SDC1_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_SDC1_0,
+ .end = INT_SDC1_1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 8,
+ .end = 8,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static struct resource resources_sdc2[] = {
+ {
+ .start = MSM_SDC2_BASE,
+ .end = MSM_SDC2_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_SDC2_0,
+ .end = INT_SDC2_1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 8,
+ .end = 8,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static struct resource resources_sdc3[] = {
+ {
+ .start = MSM_SDC3_BASE,
+ .end = MSM_SDC3_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_SDC3_0,
+ .end = INT_SDC3_1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 8,
+ .end = 8,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static struct resource resources_sdc4[] = {
+ {
+ .start = MSM_SDC4_BASE,
+ .end = MSM_SDC4_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_SDC4_0,
+ .end = INT_SDC4_1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 8,
+ .end = 8,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+struct platform_device msm_device_sdc1 = {
+ .name = "msm_sdcc",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(resources_sdc1),
+ .resource = resources_sdc1,
+ .dev = {
+ .coherent_dma_mask = 0xffffffff,
+ },
+};
+
+struct platform_device msm_device_sdc2 = {
+ .name = "msm_sdcc",
+ .id = 2,
+ .num_resources = ARRAY_SIZE(resources_sdc2),
+ .resource = resources_sdc2,
+ .dev = {
+ .coherent_dma_mask = 0xffffffff,
+ },
+};
+
+struct platform_device msm_device_sdc3 = {
+ .name = "msm_sdcc",
+ .id = 3,
+ .num_resources = ARRAY_SIZE(resources_sdc3),
+ .resource = resources_sdc3,
+ .dev = {
+ .coherent_dma_mask = 0xffffffff,
+ },
+};
+
+struct platform_device msm_device_sdc4 = {
+ .name = "msm_sdcc",
+ .id = 4,
+ .num_resources = ARRAY_SIZE(resources_sdc4),
+ .resource = resources_sdc4,
+ .dev = {
+ .coherent_dma_mask = 0xffffffff,
+ },
+};
+
+static struct platform_device *msm_sdcc_devices[] __initdata = {
+ &msm_device_sdc1,
+ &msm_device_sdc2,
+ &msm_device_sdc3,
+ &msm_device_sdc4,
+};
+
+int __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat)
+{
+ struct platform_device *pdev;
+
+ if (controller < 1 || controller > 4)
+ return -EINVAL;
+
+ pdev = msm_sdcc_devices[controller-1];
+ pdev->dev.platform_data = plat;
+ return platform_device_register(pdev);
+}
+
+#define MDP_BASE 0xAA200000
+#define MIPI_DSI_HW_BASE 0xA1100000
+
+static struct resource msm_mipi_dsi_resources[] = {
+ {
+ .name = "mipi_dsi",
+ .start = MIPI_DSI_HW_BASE,
+ .end = MIPI_DSI_HW_BASE + 0x000F0000 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_DSI_IRQ,
+ .end = INT_DSI_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device msm_mipi_dsi_device = {
+ .name = "mipi_dsi",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(msm_mipi_dsi_resources),
+ .resource = msm_mipi_dsi_resources,
+};
+
+static struct resource msm_mdp_resources[] = {
+ {
+ .name = "mdp",
+ .start = MDP_BASE,
+ .end = MDP_BASE + 0x000F1008 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = INT_MDP,
+ .end = INT_MDP,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device msm_mdp_device = {
+ .name = "mdp",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(msm_mdp_resources),
+ .resource = msm_mdp_resources,
+};
+
+static struct platform_device msm_lcdc_device = {
+ .name = "lcdc",
+ .id = 0,
+};
+
+static struct resource kgsl_3d0_resources[] = {
+ {
+ .name = KGSL_3D0_REG_MEMORY,
+ .start = 0xA0000000,
+ .end = 0xA001ffff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = KGSL_3D0_IRQ,
+ .start = INT_GRAPHICS,
+ .end = INT_GRAPHICS,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct kgsl_device_platform_data kgsl_3d0_pdata = {
+ .pwr_data = {
+ .pwrlevel = {
+ {
+ .gpu_freq = 245760000,
+ .bus_freq = 200000000,
+ },
+ {
+ .gpu_freq = 133330000,
+ .bus_freq = 0,
+ },
+ },
+ .init_level = 0,
+ .num_levels = 2,
+ .set_grp_async = set_grp_xbar_async,
+ .idle_timeout = HZ/5,
+ .nap_allowed = false,
+ },
+ .clk = {
+ .name = {
+ .clk = "grp_clk",
+ .pclk = "grp_pclk",
+ },
+ },
+ .imem_clk_name = {
+ .clk = "imem_clk",
+ .pclk = NULL,
+ },
+
+};
+
+struct platform_device msm_kgsl_3d0 = {
+ .name = "kgsl-3d0",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(kgsl_3d0_resources),
+ .resource = kgsl_3d0_resources,
+ .dev = {
+ .platform_data = &kgsl_3d0_pdata,
+ },
+};
+
+void __init msm7x25a_kgsl_3d0_init(void)
+{
+ if (cpu_is_msm7x25a() || cpu_is_msm7x25aa()) {
+ kgsl_3d0_pdata.pwr_data.pwrlevel[0].gpu_freq = 133330000;
+ kgsl_3d0_pdata.pwr_data.pwrlevel[0].bus_freq = 200000000;
+ kgsl_3d0_pdata.pwr_data.pwrlevel[1].gpu_freq = 96000000;
+ kgsl_3d0_pdata.pwr_data.pwrlevel[1].bus_freq = 0;
+ }
+}
+
+static void __init msm_register_device(struct platform_device *pdev, void *data)
+{
+ int ret;
+
+ pdev->dev.platform_data = data;
+
+ ret = platform_device_register(pdev);
+
+ if (ret)
+ dev_err(&pdev->dev,
+ "%s: platform_device_register() failed = %d\n",
+ __func__, ret);
+}
+
+void __init msm_fb_register_device(char *name, void *data)
+{
+ if (!strncmp(name, "mdp", 3))
+ msm_register_device(&msm_mdp_device, data);
+ else if (!strncmp(name, "mipi_dsi", 8))
+ msm_register_device(&msm_mipi_dsi_device, data);
+ else if (!strncmp(name, "lcdc", 4))
+ msm_register_device(&msm_lcdc_device, data);
+ else
+ printk(KERN_ERR "%s: unknown device! %s\n", __func__, name);
+}
+
+#define PERPH_WEB_BLOCK_ADDR (0xA9D00040)
+#define PDM0_CTL_OFFSET (0x04)
+#define SIZE_8B (0x08)
+
+static struct resource resources_led[] = {
+ {
+ .start = PERPH_WEB_BLOCK_ADDR,
+ .end = PERPH_WEB_BLOCK_ADDR + (SIZE_8B) - 1,
+ .name = "led-gpio-pdm",
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct led_info msm_kpbl_pdm_led_pdata = {
+ .name = "keyboard-backlight",
+};
+
+struct platform_device led_pdev = {
+ .name = "leds-msm-pdm",
+ /* use pdev id to represent pdm id */
+ .id = 0,
+ .num_resources = ARRAY_SIZE(resources_led),
+ .resource = resources_led,
+ .dev = {
+ .platform_data = &msm_kpbl_pdm_led_pdata,
+ },
+};
+
+static struct msm_acpu_clock_platform_data msm7x2x_clock_data = {
+ .acpu_switch_time_us = 50,
+ .max_speed_delta_khz = 400000,
+ .vdd_switch_time_us = 62,
+ .max_axi_khz = 200000,
+};
+
+int __init msm7x2x_misc_init(void)
+{
+ if (socinfo_init() < 0)
+ pr_err("%s: socinfo_init() failed!\n", __func__);
+
+ msm_clock_init(msm_clocks_7x27a, msm_num_clocks_7x27a);
+ msm_acpu_clock_init(&msm7x2x_clock_data);
+
+ return 0;
+}
+
+#ifdef CONFIG_CACHE_L2X0
+static int __init msm7x27x_cache_init(void)
+{
+ int aux_ctrl = 0;
+
+ /* Way Size 010(0x2) 32KB */
+ aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | \
+ (0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | \
+ (0x1 << L2X0_AUX_CTRL_EVNT_MON_BUS_EN_SHIFT);
+
+ l2x0_init(MSM_L2CC_BASE, aux_ctrl, L2X0_AUX_CTRL_MASK);
+
+ return 0;
+}
+#else
+static int __init msm_cache_init(void){ return 0; }
+#endif
+
+void __init msm_common_io_init(void)
+{
+ msm_map_common_io();
+ msm7x27x_cache_init();
+}
+
+struct platform_device *msm_footswitch_devices[] = {
+ FS_PCOM(FS_GFX3D, "fs_gfx3d"),
+};
+unsigned msm_num_footswitch_devices = ARRAY_SIZE(msm_footswitch_devices);