Initial Contribution
msm-2.6.38: tag AU_LINUX_ANDROID_GINGERBREAD.02.03.04.00.142
Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c
index 689e78c..04124c5 100644
--- a/arch/arm/mach-msm/sirc.c
+++ b/arch/arm/mach-msm/sirc.c
@@ -1,25 +1,29 @@
-/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
+/* linux/arch/arm/mach-msm/irq.c
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
+ * Copyright (c) 2009-2011 Code Aurora Forum. All rights reserved.
+ * Copyright (C) 2009 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- *
*/
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
+#include <linux/irqdesc.h>
#include <asm/irq.h>
+#include <asm/io.h>
+#include <mach/fiq.h>
+#include <mach/msm_iomap.h>
+
+#include "sirc.h"
static unsigned int int_enable;
static unsigned int wake_enable;
@@ -37,9 +41,13 @@
{
.int_status = SPSS_SIRC_IRQ_STATUS,
.cascade_irq = INT_SIRC_0,
+ .cascade_fiq = INT_SIRC_1,
}
};
+static unsigned int save_type;
+static unsigned int save_polarity;
+
/* Mask off the given interrupt. Keep the int_enable mask in sync with
the enable reg, so it can be restored after power collapse. */
static void sirc_irq_mask(struct irq_data *d)
@@ -49,6 +57,7 @@
mask = 1 << (d->irq - FIRST_SIRC_IRQ);
writel(mask, sirc_regs.int_enable_clear);
int_enable &= ~mask;
+ mb();
return;
}
@@ -60,6 +69,7 @@
mask = 1 << (d->irq - FIRST_SIRC_IRQ);
writel(mask, sirc_regs.int_enable_set);
+ mb();
int_enable |= mask;
return;
}
@@ -70,6 +80,7 @@
mask = 1 << (d->irq - FIRST_SIRC_IRQ);
writel(mask, sirc_regs.int_clear);
+ mb();
return;
}
@@ -105,17 +116,35 @@
val = readl(sirc_regs.int_type);
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
val |= mask;
- __irq_set_handler_locked(d->irq, handle_edge_irq);
} else {
val &= ~mask;
- __irq_set_handler_locked(d->irq, handle_level_irq);
}
writel(val, sirc_regs.int_type);
+ mb();
return 0;
}
+#if defined(CONFIG_MSM_FIQ_SUPPORT)
+void sirc_fiq_select(int irq, bool enable)
+{
+ uint32_t mask = 1 << (irq - FIRST_SIRC_IRQ);
+ uint32_t val;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ val = readl(SPSS_SIRC_INT_SELECT);
+ if (enable)
+ val |= mask;
+ else
+ val &= ~mask;
+ writel(val, SPSS_SIRC_INT_SELECT);
+ mb();
+ local_irq_restore(flags);
+}
+#endif
+
/* Finds the pending interrupt on the passed cascade irq and redrives it */
static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc)
{
@@ -127,6 +156,12 @@
(sirc_reg_table[reg].cascade_irq != irq))
reg++;
+ if (reg == ARRAY_SIZE(sirc_reg_table)) {
+ printk(KERN_ERR "%s: incorrect irq %d called\n",
+ __func__, irq);
+ return;
+ }
+
status = readl(sirc_reg_table[reg].int_status);
status &= SIRC_MASK;
if (status == 0)
@@ -138,16 +173,34 @@
;
generic_handle_irq(sirq+FIRST_SIRC_IRQ);
- desc->irq_data.chip->irq_ack(&desc->irq_data);
+ irq_desc_get_chip(desc)->irq_ack(irq_get_irq_data(irq));
+}
+
+void msm_sirc_enter_sleep(void)
+{
+ save_type = readl(sirc_regs.int_type);
+ save_polarity = readl(sirc_regs.int_polarity);
+ writel(wake_enable, sirc_regs.int_enable);
+ mb();
+ return;
+}
+
+void msm_sirc_exit_sleep(void)
+{
+ writel(save_type, sirc_regs.int_type);
+ writel(save_polarity, sirc_regs.int_polarity);
+ writel(int_enable, sirc_regs.int_enable);
+ mb();
+ return;
}
static struct irq_chip sirc_irq_chip = {
- .name = "sirc",
- .irq_ack = sirc_irq_ack,
- .irq_mask = sirc_irq_mask,
- .irq_unmask = sirc_irq_unmask,
- .irq_set_wake = sirc_irq_set_wake,
- .irq_set_type = sirc_irq_set_type,
+ .name = "sirc",
+ .irq_ack = sirc_irq_ack,
+ .irq_mask = sirc_irq_mask,
+ .irq_unmask = sirc_irq_unmask,
+ .irq_set_wake = sirc_irq_set_wake,
+ .irq_set_type = sirc_irq_set_type,
};
void __init msm_init_sirc(void)
@@ -166,6 +219,10 @@
irq_set_chained_handler(sirc_reg_table[i].cascade_irq,
sirc_irq_handler);
irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
+#if defined(CONFIG_MSM_FIQ_SUPPORT)
+ msm_fiq_select(sirc_reg_table[i].cascade_fiq);
+ msm_fiq_enable(sirc_reg_table[i].cascade_fiq);
+#endif
}
return;
}