Initial Contribution
msm-2.6.38: tag AU_LINUX_ANDROID_GINGERBREAD.02.03.04.00.142
Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 0074b8d..e862f63 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -588,6 +588,9 @@
config CPU_TLB_V7
bool
+config EMULATE_DOMAIN_MANAGER_V7
+ bool
+
config VERIFY_PERMISSION_FAULT
bool
endif
@@ -738,6 +741,19 @@
If your SoC is configured to have a different size, define the value
here with proper conditions.
+config CPU_CACHE_ERR_REPORT
+ bool "Report errors in the L1 and L2 caches"
+ depends on ARCH_MSM_SCORPION
+ default n
+ help
+ The Scorpion processor supports reporting L2 errors, L1 icache parity
+ errors, and L1 dcache parity errors as imprecise external aborts. If
+ this option is not enabled these errors will go unreported and data
+ corruption will occur.
+
+ Say Y here to have errors in the L1 and L2 caches reported as
+ imprecise data aborts.
+
config CPU_DCACHE_WRITETHROUGH
bool "Force write through D-cache"
depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
@@ -821,7 +837,7 @@
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
- ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
+ ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_MSM7X27
default y
select OUTER_CACHE
select OUTER_CACHE_SYNC
@@ -889,3 +905,30 @@
help
This option allows the use of custom mandatory barriers
included via the mach/barriers.h file.
+
+config VCM_MM
+ bool
+
+config VCM
+ bool "Virtual Contiguous Memory (VCM) Layer"
+ depends on MMU
+ select GENERIC_ALLOCATOR
+ select VCM_MM
+ default n
+ help
+ Virtual Contiguous Memory layer. This is the layer that is intended to
+ replace PMEM.
+
+ If you don't know what this is, say N here.
+
+config STRICT_MEMORY_RWX
+ bool "restrict kernel memory permissions as much as possible"
+ default n
+ help
+ If this is set, kernel text will be made RX, kernel data and stack
+ RW, rodata R (otherwise all of the kernel 1-to-1 mapping is
+ made RWX).
+ The tradeoff is that several sections are padded to
+ 1M boundaries (because their permissions are different and
+ splitting the 1M pages into 4K ones causes TLB performance
+ problems), wasting memory.