Initial Contribution
msm-2.6.38: tag AU_LINUX_ANDROID_GINGERBREAD.02.03.04.00.142
Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 44c0867..25a4260 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -2,6 +2,7 @@
* arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
*
* Copyright (C) 2007 ARM Limited
+ * Copyright (c) 2009, 2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -26,6 +27,7 @@
#define CACHE_LINE_SIZE 32
static void __iomem *l2x0_base;
+static uint32_t aux_ctrl_save;
static DEFINE_SPINLOCK(l2x0_lock);
static uint32_t l2x0_way_mask; /* Bitmask of active ways */
static uint32_t l2x0_size;
@@ -111,13 +113,9 @@
}
#endif
-static void l2x0_cache_sync(void)
+void l2x0_cache_sync(void)
{
- unsigned long flags;
-
- spin_lock_irqsave(&l2x0_lock, flags);
cache_sync();
- spin_unlock_irqrestore(&l2x0_lock, flags);
}
static void __l2x0_flush_all(void)
@@ -204,6 +202,27 @@
spin_unlock_irqrestore(&l2x0_lock, flags);
}
+static void l2x0_inv_range_atomic(unsigned long start, unsigned long end)
+{
+ unsigned long addr;
+
+ if (start & (CACHE_LINE_SIZE - 1)) {
+ start &= ~(CACHE_LINE_SIZE - 1);
+ writel_relaxed(start, l2x0_base + L2X0_CLEAN_INV_LINE_PA);
+ start += CACHE_LINE_SIZE;
+ }
+
+ if (end & (CACHE_LINE_SIZE - 1)) {
+ end &= ~(CACHE_LINE_SIZE - 1);
+ writel_relaxed(end, l2x0_base + L2X0_CLEAN_INV_LINE_PA);
+ }
+
+ for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
+ writel_relaxed(addr, l2x0_base + L2X0_INV_LINE_PA);
+
+ mb();
+}
+
static void l2x0_clean_range(unsigned long start, unsigned long end)
{
void __iomem *base = l2x0_base;
@@ -234,6 +253,17 @@
spin_unlock_irqrestore(&l2x0_lock, flags);
}
+static void l2x0_clean_range_atomic(unsigned long start, unsigned long end)
+{
+ unsigned long addr;
+
+ start &= ~(CACHE_LINE_SIZE - 1);
+ for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
+ writel_relaxed(addr, l2x0_base + L2X0_CLEAN_LINE_PA);
+
+ mb();
+}
+
static void l2x0_flush_range(unsigned long start, unsigned long end)
{
void __iomem *base = l2x0_base;
@@ -266,6 +296,17 @@
spin_unlock_irqrestore(&l2x0_lock, flags);
}
+void l2x0_flush_range_atomic(unsigned long start, unsigned long end)
+{
+ unsigned long addr;
+
+ start &= ~(CACHE_LINE_SIZE - 1);
+ for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
+ writel_relaxed(addr, l2x0_base + L2X0_CLEAN_INV_LINE_PA);
+
+ mb();
+}
+
static void l2x0_disable(void)
{
unsigned long flags;
@@ -279,15 +320,19 @@
void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
{
- __u32 aux;
+ __u32 aux, bits;
__u32 cache_id;
__u32 way_size = 0;
int ways;
const char *type;
l2x0_base = base;
-
cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+
+ bits = readl_relaxed(l2x0_base + L2X0_CTRL);
+ bits &= ~0x01; /* clear bit 0 */
+ writel_relaxed(bits, l2x0_base + L2X0_CTRL);
+
aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
aux &= aux_mask;
@@ -312,7 +357,7 @@
type = "L2x0 series";
break;
}
-
+ writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
l2x0_way_mask = (1 << ways) - 1;
/*
@@ -322,32 +367,76 @@
way_size = 1 << (way_size + 3);
l2x0_size = ways * way_size * SZ_1K;
- /*
- * Check if l2x0 controller is already enabled.
- * If you are booting from non-secure mode
- * accessing the below registers will fault.
- */
- if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
+ l2x0_inv_all();
- /* l2x0 controller is disabled */
- writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
+ /* enable L2X0 */
+ bits = readl_relaxed(l2x0_base + L2X0_CTRL);
+ bits |= 0x01; /* set bit 0 */
+ writel_relaxed(bits, l2x0_base + L2X0_CTRL);
- l2x0_inv_all();
-
- /* enable L2X0 */
- writel_relaxed(1, l2x0_base + L2X0_CTRL);
+ switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+ case L2X0_CACHE_ID_PART_L220:
+ outer_cache.inv_range = l2x0_inv_range;
+ outer_cache.clean_range = l2x0_clean_range;
+ outer_cache.flush_range = l2x0_flush_range;
+ printk(KERN_INFO "L220 cache controller enabled\n");
+ break;
+ case L2X0_CACHE_ID_PART_L310:
+ outer_cache.inv_range = l2x0_inv_range;
+ outer_cache.clean_range = l2x0_clean_range;
+ outer_cache.flush_range = l2x0_flush_range;
+ printk(KERN_INFO "L310 cache controller enabled\n");
+ break;
+ case L2X0_CACHE_ID_PART_L210:
+ default:
+ outer_cache.inv_range = l2x0_inv_range_atomic;
+ outer_cache.clean_range = l2x0_clean_range_atomic;
+ outer_cache.flush_range = l2x0_flush_range_atomic;
+ printk(KERN_INFO "L210 cache controller enabled\n");
+ break;
}
- outer_cache.inv_range = l2x0_inv_range;
- outer_cache.clean_range = l2x0_clean_range;
- outer_cache.flush_range = l2x0_flush_range;
outer_cache.sync = l2x0_cache_sync;
+
outer_cache.flush_all = l2x0_flush_all;
outer_cache.inv_all = l2x0_inv_all;
outer_cache.disable = l2x0_disable;
outer_cache.set_debug = l2x0_set_debug;
+ mb();
printk(KERN_INFO "%s cache controller enabled\n", type);
printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
ways, cache_id, aux, l2x0_size);
}
+
+void l2x0_suspend(void)
+{
+ /* Save aux control register value */
+ aux_ctrl_save = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+ /* Flush all cache */
+ l2x0_flush_all();
+ /* Disable the cache */
+ writel_relaxed(0, l2x0_base + L2X0_CTRL);
+
+ /* Memory barrier */
+ dmb();
+}
+
+void l2x0_resume(int collapsed)
+{
+ if (collapsed) {
+ /* Disable the cache */
+ writel_relaxed(0, l2x0_base + L2X0_CTRL);
+
+ /* Restore aux control register value */
+ writel_relaxed(aux_ctrl_save, l2x0_base + L2X0_AUX_CTRL);
+
+ /* Invalidate the cache */
+ l2x0_inv_all();
+ }
+
+ /* Enable the cache */
+ writel_relaxed(1, l2x0_base + L2X0_CTRL);
+
+ mb();
+}