Initial Contribution
msm-2.6.38: tag AU_LINUX_ANDROID_GINGERBREAD.02.03.04.00.142
Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 089c0b5..449d463 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
+#include <asm/domain.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
@@ -61,7 +62,14 @@
*/
.align 5
ENTRY(cpu_v7_reset)
- mov pc, r0
+ mrc p15, 0, r1, c1, c0, 0 @ ctrl register
+ bic r1, r1, #0x0001 @ ...............m
+ mcr p15, 0, r1, c1, c0, 0 @ Turn off MMU
+ mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D,flush TLB
+ mcr p15, 0, ip, c7, c5, 6 @ flush BTC
+ dsb
+ isb
+ mov pc,r0
ENDPROC(cpu_v7_reset)
/*
@@ -101,6 +109,11 @@
*/
ENTRY(cpu_v7_switch_mm)
#ifdef CONFIG_MMU
+#ifdef CONFIG_EMULATE_DOMAIN_MANAGER_V7
+ ldr r2, =cpu_v7_switch_mm_private
+ b emulate_domain_manager_switch_mm
+cpu_v7_switch_mm_private:
+#endif
mov r2, #0
ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
@@ -280,9 +293,8 @@
* - cache type register is implemented
*/
__v7_ca9mp_setup:
-#ifdef CONFIG_SMP
- ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
- ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
+#if defined(CONFIG_SMP)
+ mrc p15, 0, r0, c1, c0, 1
tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
@@ -375,6 +387,35 @@
ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
mcr p15, 0, r8, c2, c0, 1 @ load TTB1
+#ifndef CONFIG_EMULATE_DOMAIN_MANAGER_V7
+ mov r10, #0x1f @ domains 0, 1 = manager
+ mcr p15, 0, r10, c3, c0, 0 @ load domain access register
+#endif
+#if defined(CONFIG_ARCH_MSM_SCORPION) && !defined(CONFIG_MSM_SMP)
+ mov r0, #0x33
+ mcr p15, 3, r0, c15, c0, 3 @ set L2CR1
+#endif
+#if defined (CONFIG_ARCH_MSM_SCORPION)
+ mrc p15, 0, r0, c1, c0, 1 @ read ACTLR
+#ifdef CONFIG_CPU_CACHE_ERR_REPORT
+ orr r0, r0, #0x37 @ turn on L1/L2 error reporting
+#else
+ bic r0, r0, #0x37
+#endif
+#if defined (CONFIG_ARCH_MSM_SCORPIONMP)
+ orr r0, r0, #0x1 << 24 @ optimal setting for Scorpion MP
+#endif
+#ifndef CONFIG_ARCH_MSM_KRAIT
+ mcr p15, 0, r0, c1, c0, 1 @ write ACTLR
+#endif
+#endif
+
+#if defined (CONFIG_ARCH_MSM_SCORPIONMP)
+ mrc p15, 3, r0, c15, c0, 2 @ optimal setting for Scorpion MP
+ orr r0, r0, #0x1 << 21
+ mcr p15, 3, r0, c15, c0, 2
+#endif
+
ldr r5, =PRRR @ PRRR
ldr r6, =NMRR @ NMRR
mcr p15, 0, r5, c10, c2, 0 @ write PRRR