Initial Contribution
msm-2.6.38: tag AU_LINUX_ANDROID_GINGERBREAD.02.03.04.00.142
Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
diff --git a/drivers/crypto/msm/inc/qce.h b/drivers/crypto/msm/inc/qce.h
new file mode 100644
index 0000000..7230036
--- /dev/null
+++ b/drivers/crypto/msm/inc/qce.h
@@ -0,0 +1,160 @@
+/* Qualcomm Crypto Engine driver API
+ *
+ * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef __CRYPTO_MSM_QCE_H
+#define __CRYPTO_MSM_QCE_H
+
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/crypto.h>
+
+#include <crypto/algapi.h>
+#include <crypto/aes.h>
+#include <crypto/des.h>
+#include <crypto/sha.h>
+#include <crypto/aead.h>
+#include <crypto/authenc.h>
+#include <crypto/scatterwalk.h>
+
+/* SHA digest size in bytes */
+#define SHA256_DIGESTSIZE 32
+#define SHA1_DIGESTSIZE 20
+
+/* key size in bytes */
+#define HMAC_KEY_SIZE (SHA1_DIGESTSIZE) /* hmac-sha1 */
+#define SHA_HMAC_KEY_SIZE 64
+#define DES_KEY_SIZE 8
+#define TRIPLE_DES_KEY_SIZE 24
+#define AES128_KEY_SIZE 16
+#define AES192_KEY_SIZE 24
+#define AES256_KEY_SIZE 32
+#define MAX_CIPHER_KEY_SIZE AES256_KEY_SIZE
+
+/* iv length in bytes */
+#define AES_IV_LENGTH 16
+#define DES_IV_LENGTH 8
+#define MAX_IV_LENGTH AES_IV_LENGTH
+
+/* Maximum number of bytes per transfer */
+#define QCE_MAX_OPER_DATA 0x8000
+
+/* Maximum Nonce bytes */
+#define MAX_NONCE 16
+
+typedef void (*qce_comp_func_ptr_t)(void *areq,
+ unsigned char *icv, unsigned char *iv, int ret);
+
+/* Cipher algorithms supported */
+enum qce_cipher_alg_enum {
+ CIPHER_ALG_DES = 0,
+ CIPHER_ALG_3DES = 1,
+ CIPHER_ALG_AES = 2,
+ CIPHER_ALG_LAST
+};
+
+/* Hash and hmac algorithms supported */
+enum qce_hash_alg_enum {
+ QCE_HASH_SHA1 = 0,
+ QCE_HASH_SHA256 = 1,
+ QCE_HASH_SHA1_HMAC = 2,
+ QCE_HASH_SHA256_HMAC = 3,
+ QCE_HASH_AES_CMAC = 4,
+ QCE_HASH_LAST
+};
+
+/* Cipher encryption/decryption operations */
+enum qce_cipher_dir_enum {
+ QCE_ENCRYPT = 0,
+ QCE_DECRYPT = 1,
+ QCE_CIPHER_DIR_LAST
+};
+
+/* Cipher algorithms modes */
+enum qce_cipher_mode_enum {
+ QCE_MODE_CBC = 0,
+ QCE_MODE_ECB = 1,
+ QCE_MODE_CTR = 2,
+ QCE_MODE_XTS = 3,
+ QCE_MODE_CCM = 4,
+ QCE_CIPHER_MODE_LAST
+};
+
+/* Cipher operation type */
+enum qce_req_op_enum {
+ QCE_REQ_ABLK_CIPHER = 0,
+ QCE_REQ_ABLK_CIPHER_NO_KEY = 1,
+ QCE_REQ_AEAD = 2,
+ QCE_REQ_LAST
+};
+
+/* Algorithms/features supported in CE HW engine */
+struct ce_hw_support {
+ bool sha1_hmac_20; /* Supports 20 bytes of HMAC key*/
+ bool sha1_hmac; /* supports max HMAC key of 64 bytes*/
+ bool sha256_hmac; /* supports max HMAC key of 64 bytes*/
+ bool sha_hmac; /* supports SHA1 and SHA256 MAX HMAC key of 64 bytes*/
+ bool cmac;
+ bool aes_key_192;
+ bool aes_xts;
+ bool aes_ccm;
+ bool ota;
+};
+
+/* Sha operation parameters */
+struct qce_sha_req {
+ qce_comp_func_ptr_t qce_cb; /* call back */
+ enum qce_hash_alg_enum alg; /* sha algorithm */
+ unsigned char *digest; /* sha digest */
+ struct scatterlist *src; /* pointer to scatter list entry */
+ uint32_t auth_data[4]; /* byte count */
+ unsigned char *authkey; /* auth key */
+ unsigned int authklen; /* auth key length */
+ bool first_blk; /* first block indicator */
+ bool last_blk; /* last block indicator */
+ unsigned int size; /* data length in bytes */
+ void *areq;
+};
+
+struct qce_req {
+ enum qce_req_op_enum op; /* operation type */
+ qce_comp_func_ptr_t qce_cb; /* call back */
+ void *areq;
+ enum qce_cipher_alg_enum alg; /* cipher algorithms*/
+ enum qce_cipher_dir_enum dir; /* encryption? decryption? */
+ enum qce_cipher_mode_enum mode; /* algorithm mode */
+ unsigned char *authkey; /* authentication key */
+ unsigned int authklen; /* authentication key kength */
+ unsigned int authsize; /* authentication key kength */
+ unsigned char nonce[MAX_NONCE];/* nonce for ccm mode */
+ unsigned char *assoc; /* Ptr to formatted associated data */
+ unsigned int assoclen; /* Formatted associated data length */
+ struct scatterlist *asg; /* Formatted associated data sg */
+ unsigned char *enckey; /* cipher key */
+ unsigned int encklen; /* cipher key length */
+ unsigned char *iv; /* initialization vector */
+ unsigned int ivsize; /* initialization vector size*/
+ unsigned int cryptlen; /* data length */
+ unsigned int use_pmem; /* is source of data PMEM allocated? */
+ struct qcedev_pmem_info *pmem; /* pointer to pmem_info structure*/
+};
+
+void *qce_open(struct platform_device *pdev, int *rc);
+int qce_close(void *handle);
+int qce_aead_req(void *handle, struct qce_req *req);
+int qce_ablk_cipher_req(void *handle, struct qce_req *req);
+int qce_hw_support(void *handle, struct ce_hw_support *support);
+int qce_process_sha_req(void *handle, struct qce_sha_req *s_req);
+
+#endif /* __CRYPTO_MSM_QCE_H */
diff --git a/drivers/crypto/msm/inc/qce_ota.h b/drivers/crypto/msm/inc/qce_ota.h
new file mode 100644
index 0000000..f21bd0b
--- /dev/null
+++ b/drivers/crypto/msm/inc/qce_ota.h
@@ -0,0 +1,31 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* Qualcomm Crypto Engine driver OTA APIi */
+
+#ifndef __CRYPTO_MSM_QCE_OTA_H
+#define __CRYPTO_MSM_QCE_OTA_H
+
+#include <linux/platform_device.h>
+#include <linux/qcota.h>
+#include <inc/qce.h>
+
+
+int qce_f8_req(void *handle, struct qce_f8_req *req,
+ void *cookie, qce_comp_func_ptr_t qce_cb);
+int qce_f8_multi_pkt_req(void *handle, struct qce_f8_multi_pkt_req *req,
+ void *cookie, qce_comp_func_ptr_t qce_cb);
+int qce_f9_req(void *handle, struct qce_f9_req *req,
+ void *cookie, qce_comp_func_ptr_t qce_cb);
+
+#endif /* __CRYPTO_MSM_QCE_OTA_H */
diff --git a/drivers/crypto/msm/inc/qcedev.h b/drivers/crypto/msm/inc/qcedev.h
new file mode 100644
index 0000000..893251f
--- /dev/null
+++ b/drivers/crypto/msm/inc/qcedev.h
@@ -0,0 +1,267 @@
+/* Qualcomm Crypto Engine driver QCEDEV API
+ *
+ * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __QCEDEV__H
+#define __QCEDEV__H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#define QCEDEV_MAX_SHA_BLOCK_SIZE 64
+#define QCEDEV_MAX_BEARER 31
+#define QCEDEV_MAX_KEY_SIZE 64
+#define QCEDEV_MAX_IV_SIZE 32
+
+#define QCEDEV_MAX_BUFFERS 16
+#define QCEDEV_MAX_SHA_DIGEST 32
+
+#define QCEDEV_USE_PMEM 1
+#define QCEDEV_NO_PMEM 0
+
+#define QCEDEV_AES_KEY_128 16
+#define QCEDEV_AES_KEY_192 24
+#define QCEDEV_AES_KEY_256 32
+/**
+*qcedev_oper_enum: Operation types
+* @QCEDEV_OPER_ENC: Encrypt
+* @QCEDEV_OPER_DEC: Decrypt
+* @QCEDEV_OPER_ENC_NO_KEY: Encrypt. Do not need key to be specified by
+* user. Key already set by an external processor.
+* @QCEDEV_OPER_DEC_NO_KEY: Decrypt. Do not need the key to be specified by
+* user. Key already set by an external processor.
+*/
+enum qcedev_oper_enum {
+ QCEDEV_OPER_DEC = 0,
+ QCEDEV_OPER_ENC = 1,
+ QCEDEV_OPER_DEC_NO_KEY = 2,
+ QCEDEV_OPER_ENC_NO_KEY = 3,
+ QCEDEV_OPER_LAST
+};
+
+/**
+*qcedev_oper_enum: Cipher algorithm types
+* @QCEDEV_ALG_DES: DES
+* @QCEDEV_ALG_3DES: 3DES
+* @QCEDEV_ALG_AES: AES
+*/
+enum qcedev_cipher_alg_enum {
+ QCEDEV_ALG_DES = 0,
+ QCEDEV_ALG_3DES = 1,
+ QCEDEV_ALG_AES = 2,
+ QCEDEV_ALG_LAST
+};
+
+/**
+*qcedev_cipher_mode_enum : AES mode
+* @QCEDEV_AES_MODE_CBC: CBC
+* @QCEDEV_AES_MODE_ECB: ECB
+* @QCEDEV_AES_MODE_CTR: CTR
+* @QCEDEV_AES_MODE_XTS: XTS
+* @QCEDEV_AES_MODE_CCM: CCM
+* @QCEDEV_DES_MODE_CBC: CBC
+* @QCEDEV_DES_MODE_ECB: ECB
+*/
+enum qcedev_cipher_mode_enum {
+ QCEDEV_AES_MODE_CBC = 0,
+ QCEDEV_AES_MODE_ECB = 1,
+ QCEDEV_AES_MODE_CTR = 2,
+ QCEDEV_AES_MODE_XTS = 3,
+ QCEDEV_AES_MODE_CCM = 4,
+ QCEDEV_DES_MODE_CBC = 5,
+ QCEDEV_DES_MODE_ECB = 6,
+ QCEDEV_AES_DES_MODE_LAST
+};
+
+/**
+*enum qcedev_sha_alg_enum : Secure Hashing Algorithm
+* @QCEDEV_ALG_SHA1: Digest returned: 20 bytes (160 bits)
+* @QCEDEV_ALG_SHA256: Digest returned: 32 bytes (256 bit)
+* @QCEDEV_ALG_SHA1_HMAC: HMAC returned 20 bytes (160 bits)
+* @QCEDEV_ALG_SHA256_HMAC: HMAC returned 32 bytes (256 bit)
+* @QCEDEV_ALG_AES_CMAC: Configurable MAC size
+*/
+enum qcedev_sha_alg_enum {
+ QCEDEV_ALG_SHA1 = 0,
+ QCEDEV_ALG_SHA256 = 1,
+ QCEDEV_ALG_SHA1_HMAC = 2,
+ QCEDEV_ALG_SHA256_HMAC = 3,
+ QCEDEV_ALG_AES_CMAC = 4,
+ QCEDEV_ALG_SHA_ALG_LAST
+};
+
+/**
+* struct buf_info - Buffer information
+* @offset: Offset from the base address of the buffer
+* (Used when buffer is allocated using PMEM)
+* @vaddr: Virtual buffer address pointer
+* @len: Size of the buffer
+*/
+struct buf_info {
+ union{
+ uint32_t offset;
+ uint8_t *vaddr;
+ };
+ uint32_t len;
+};
+
+/**
+* struct qcedev_vbuf_info - Source and destination Buffer information
+* @src: Array of buf_info for input/source
+* @dst: Array of buf_info for output/destination
+*/
+struct qcedev_vbuf_info {
+ struct buf_info src[QCEDEV_MAX_BUFFERS];
+ struct buf_info dst[QCEDEV_MAX_BUFFERS];
+};
+
+struct qcedev_sha_ctxt{
+ uint32_t auth_data[4];
+ uint8_t digest[QCEDEV_MAX_SHA_DIGEST];
+ uint32_t diglen;
+ uint8_t trailing_buf[64];
+ uint32_t trailing_buf_len;
+ uint8_t first_blk;
+ uint8_t last_blk;
+ uint8_t authkey[QCEDEV_MAX_SHA_BLOCK_SIZE];
+};
+
+/**
+* struct qcedev_pmem_info - Stores PMEM buffer information
+* @fd_src: Handle to /dev/adsp_pmem used to allocate
+* memory for input/src buffer
+* @src: Array of buf_info for input/source
+* @fd_dst: Handle to /dev/adsp_pmem used to allocate
+* memory for output/dst buffer
+* @dst: Array of buf_info for output/destination
+* @pmem_src_offset: The offset from input/src buffer
+* (allocated by PMEM)
+*/
+struct qcedev_pmem_info{
+ int fd_src;
+ struct buf_info src[QCEDEV_MAX_BUFFERS];
+ int fd_dst;
+ struct buf_info dst[QCEDEV_MAX_BUFFERS];
+};
+
+/**
+* struct qcedev_cipher_op_req - Holds the ciphering request information
+* @use_pmem (IN): Flag to indicate if buffer source is PMEM
+* QCEDEV_USE_PMEM/QCEDEV_NO_PMEM
+* @pmem (IN): Stores PMEM buffer information.
+* Refer struct qcedev_pmem_info
+* @vbuf (IN/OUT): Stores Source and destination Buffer information
+* Refer to struct qcedev_vbuf_info
+* @data_len (IN): Total Length of input/src and output/dst in bytes
+* @in_place_op (IN): Indicates whether the operation is inplace where
+* source == destination
+* When using PMEM allocated memory, must set this to 1
+* @enckey (IN): 128 bits of confidentiality key
+* enckey[0] bit 127-120, enckey[1] bit 119-112,..
+* enckey[15] bit 7-0
+* @encklen (IN): Length of the encryption key(set to 128 bits/16
+* bytes in the driver)
+* @iv (IN/OUT): Initialisation vector data
+* This is updated by the driver, incremented by
+* number of blocks encrypted/decrypted.
+* @ivlen (IN): Length of the IV
+* @byteoffset (IN): Offset in the Cipher BLOCK (applicable and to be set
+* for AES-128 CTR mode only)
+* @alg (IN): Type of ciphering algorithm: AES/DES/3DES
+* @mode (IN): Mode use when using AES algorithm: ECB/CBC/CTR
+* Apllicabel when using AES algorithm only
+* @op (IN): Type of operation: QCEDEV_OPER_DEC/QCEDEV_OPER_ENC or
+* QCEDEV_OPER_ENC_NO_KEY/QCEDEV_OPER_DEC_NO_KEY
+*
+*If use_pmem is set to 0, the driver assumes that memory was not allocated
+* via PMEM, and kernel will need to allocate memory and copy data from user
+* space buffer (data_src/dta_dst) and process accordingly and copy data back
+* to the user space buffer
+*
+* If use_pmem is set to 1, the driver assumes that memory was allocated via
+* PMEM.
+* The kernel driver will use the fd_src to determine the kernel virtual address
+* base that maps to the user space virtual address base for the buffer
+* allocated in user space.
+* The final input/src and output/dst buffer pointer will be determined
+* by adding the offsets to the kernel virtual addr.
+*
+* If use of hardware key is supported in the target, user can configure the
+* key paramters (encklen, enckey) to use the hardware key.
+* In order to use the hardware key, set encklen to 0 and set the enckey
+* data array to 0.
+*/
+struct qcedev_cipher_op_req {
+ uint8_t use_pmem;
+ union{
+ struct qcedev_pmem_info pmem;
+ struct qcedev_vbuf_info vbuf;
+ };
+ uint32_t entries;
+ uint32_t data_len;
+ uint8_t in_place_op;
+ uint8_t enckey[QCEDEV_MAX_KEY_SIZE];
+ uint32_t encklen;
+ uint8_t iv[QCEDEV_MAX_IV_SIZE];
+ uint32_t ivlen;
+ uint32_t byteoffset;
+ enum qcedev_cipher_alg_enum alg;
+ enum qcedev_cipher_mode_enum mode;
+ enum qcedev_oper_enum op;
+};
+
+/**
+* struct qcedev_sha_op_req - Holds the hashing request information
+* @data (IN): Array of pointers to the data to be hashed
+* @entries (IN): Number of buf_info entries in the data array
+* @data_len (IN): Length of data to be hashed
+* @digest (IN/OUT): Returns the hashed data information
+* @diglen (OUT): Size of the hashed/digest data
+* @authkey (IN): Pointer to authentication key for HMAC
+* @authklen (IN): Size of the authentication key
+* @alg (IN): Secure Hash algorithm
+* @ctxt (Reserved): RESERVED: User should not modify this data.
+*/
+struct qcedev_sha_op_req {
+ struct buf_info data[QCEDEV_MAX_BUFFERS];
+ uint32_t entries;
+ uint32_t data_len;
+ uint8_t digest[QCEDEV_MAX_SHA_DIGEST];
+ uint32_t diglen;
+ uint8_t *authkey;
+ uint32_t authklen;
+ enum qcedev_sha_alg_enum alg;
+ struct qcedev_sha_ctxt ctxt;
+};
+
+
+#define QCEDEV_IOC_MAGIC 0x87
+
+#define QCEDEV_IOCTL_ENC_REQ \
+ _IOWR(QCEDEV_IOC_MAGIC, 1, struct qcedev_cipher_op_req)
+#define QCEDEV_IOCTL_DEC_REQ \
+ _IOWR(QCEDEV_IOC_MAGIC, 2, struct qcedev_cipher_op_req)
+#define QCEDEV_IOCTL_SHA_INIT_REQ \
+ _IOWR(QCEDEV_IOC_MAGIC, 3, struct qcedev_sha_op_req)
+#define QCEDEV_IOCTL_SHA_UPDATE_REQ \
+ _IOWR(QCEDEV_IOC_MAGIC, 4, struct qcedev_sha_op_req)
+#define QCEDEV_IOCTL_SHA_FINAL_REQ \
+ _IOWR(QCEDEV_IOC_MAGIC, 5, struct qcedev_sha_op_req)
+#define QCEDEV_IOCTL_GET_SHA_REQ \
+ _IOWR(QCEDEV_IOC_MAGIC, 6, struct qcedev_sha_op_req)
+#define QCEDEV_IOCTL_LOCK_CE \
+ _IO(QCEDEV_IOC_MAGIC, 7)
+#define QCEDEV_IOCTL_UNLOCK_CE \
+ _IO(QCEDEV_IOC_MAGIC, 8)
+#define QCEDEV_IOCTL_GET_CMAC_REQ \
+ _IOWR(QCEDEV_IOC_MAGIC, 9, struct qcedev_cipher_op_req)
+#endif /* _QCEDEV__H */
diff --git a/drivers/crypto/msm/inc/qcryptohw_30.h b/drivers/crypto/msm/inc/qcryptohw_30.h
new file mode 100644
index 0000000..edbee71
--- /dev/null
+++ b/drivers/crypto/msm/inc/qcryptohw_30.h
@@ -0,0 +1,308 @@
+/* Copyright (c)2009- 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DRIVERS_CRYPTO_MSM_QCRYPTOHW_30_H_
+#define _DRIVERS_CRYPTO_MSM_QCRYPTOHW_30_H_
+
+#define QCE_AUTH_REG_BYTE_COUNT 2
+#define CRYPTO_DATA_IN_REG 0x0
+#define CRYPTO_DATA_OUT_REG 0x10
+#define CRYPTO_STATUS_REG 0x20
+#define CRYPTO_CONFIG_REG 0x24
+#define CRYPTO_DEBUG_REG 0x28
+#define CRYPTO_REGISTER_LOCK_REG 0x2C
+#define CRYPTO_SEG_CFG_REG 0x30
+#define CRYPTO_ENCR_SEG_CFG_REG 0x34
+#define CRYPTO_AUTH_SEG_CFG_REG 0x38
+#define CRYPTO_SEG_SIZE_REG 0x3C
+#define CRYPTO_GOPROC_REG 0x40
+#define CRYPTO_ENGINES_AVAIL 0x44
+
+#define CRYPTO_DES_KEY0_REG 0x50
+#define CRYPTO_DES_KEY1_REG 0x54
+#define CRYPTO_DES_KEY2_REG 0x58
+#define CRYPTO_DES_KEY3_REG 0x5C
+#define CRYPTO_DES_KEY4_REG 0x60
+#define CRYPTO_DES_KEY5_REG 0x64
+
+#define CRYPTO_CNTR0_IV0_REG 0x70
+#define CRYPTO_CNTR1_IV1_REG 0x74
+#define CRYPTO_CNTR2_IV2_REG 0x78
+#define CRYPTO_CNTR3_IV3_REG 0x7C
+#define CRYPTO_CNTR_MASK_REG 0x80
+
+#define CRYPTO_AUTH_BYTECNT0_REG 0x90
+#define CRYPTO_AUTH_BYTECNT1_REG 0x94
+#define CRYPTO_AUTH_BYTECNT2_REG 0x98
+#define CRYPTO_AUTH_BYTECNT3_REG 0x9C
+
+#define CRYPTO_AUTH_IV0_REG 0x100
+#define CRYPTO_AUTH_IV1_REG 0x104
+#define CRYPTO_AUTH_IV2_REG 0x108
+#define CRYPTO_AUTH_IV3_REG 0x10C
+#define CRYPTO_AUTH_IV4_REG 0x110
+#define CRYPTO_AUTH_IV5_REG 0x114
+#define CRYPTO_AUTH_IV6_REG 0x118
+#define CRYPTO_AUTH_IV7_REG 0x11C
+#define CRYPTO_AUTH_IV8_REG 0x120
+#define CRYPTO_AUTH_IV9_REG 0x124
+#define CRYPTO_AUTH_IV10_REG 0x128
+#define CRYPTO_AUTH_IV11_REG 0x12C
+#define CRYPTO_AUTH_IV12_REG 0x130
+#define CRYPTO_AUTH_IV13_REG 0x134
+#define CRYPTO_AUTH_IV14_REG 0x138
+#define CRYPTO_AUTH_IV15_REG 0x13C
+
+#define CRYPTO_AES_RNDKEY0 0x200
+#define CRYPTO_AES_RNDKEY1 0x204
+#define CRYPTO_AES_RNDKEY2 0x208
+#define CRYPTO_AES_RNDKEY3 0x20C
+#define CRYPTO_AES_RNDKEY4 0x210
+#define CRYPTO_AES_RNDKEY5 0x214
+#define CRYPTO_AES_RNDKEY6 0x218
+#define CRYPTO_AES_RNDKEY7 0x21C
+#define CRYPTO_AES_RNDKEY8 0x220
+#define CRYPTO_AES_RNDKEY9 0x224
+#define CRYPTO_AES_RNDKEY10 0x228
+#define CRYPTO_AES_RNDKEY11 0x22c
+#define CRYPTO_AES_RNDKEY12 0x230
+#define CRYPTO_AES_RNDKEY13 0x234
+#define CRYPTO_AES_RNDKEY14 0x238
+#define CRYPTO_AES_RNDKEY15 0x23C
+#define CRYPTO_AES_RNDKEY16 0x240
+#define CRYPTO_AES_RNDKEY17 0x244
+#define CRYPTO_AES_RNDKEY18 0x248
+#define CRYPTO_AES_RNDKEY19 0x24C
+#define CRYPTO_AES_RNDKEY20 0x250
+#define CRYPTO_AES_RNDKEY21 0x254
+#define CRYPTO_AES_RNDKEY22 0x258
+#define CRYPTO_AES_RNDKEY23 0x25C
+#define CRYPTO_AES_RNDKEY24 0x260
+#define CRYPTO_AES_RNDKEY25 0x264
+#define CRYPTO_AES_RNDKEY26 0x268
+#define CRYPTO_AES_RNDKEY27 0x26C
+#define CRYPTO_AES_RNDKEY28 0x270
+#define CRYPTO_AES_RNDKEY29 0x274
+#define CRYPTO_AES_RNDKEY30 0x278
+#define CRYPTO_AES_RNDKEY31 0x27C
+#define CRYPTO_AES_RNDKEY32 0x280
+#define CRYPTO_AES_RNDKEY33 0x284
+#define CRYPTO_AES_RNDKEY34 0x288
+#define CRYPTO_AES_RNDKEY35 0x28c
+#define CRYPTO_AES_RNDKEY36 0x290
+#define CRYPTO_AES_RNDKEY37 0x294
+#define CRYPTO_AES_RNDKEY38 0x298
+#define CRYPTO_AES_RNDKEY39 0x29C
+#define CRYPTO_AES_RNDKEY40 0x2A0
+#define CRYPTO_AES_RNDKEY41 0x2A4
+#define CRYPTO_AES_RNDKEY42 0x2A8
+#define CRYPTO_AES_RNDKEY43 0x2AC
+#define CRYPTO_AES_RNDKEY44 0x2B0
+#define CRYPTO_AES_RNDKEY45 0x2B4
+#define CRYPTO_AES_RNDKEY46 0x2B8
+#define CRYPTO_AES_RNDKEY47 0x2BC
+#define CRYPTO_AES_RNDKEY48 0x2C0
+#define CRYPTO_AES_RNDKEY49 0x2C4
+#define CRYPTO_AES_RNDKEY50 0x2C8
+#define CRYPTO_AES_RNDKEY51 0x2CC
+#define CRYPTO_AES_RNDKEY52 0x2D0
+#define CRYPTO_AES_RNDKEY53 0x2D4
+#define CRYPTO_AES_RNDKEY54 0x2D8
+#define CRYPTO_AES_RNDKEY55 0x2DC
+#define CRYPTO_AES_RNDKEY56 0x2E0
+#define CRYPTO_AES_RNDKEY57 0x2E4
+#define CRYPTO_AES_RNDKEY58 0x2E8
+#define CRYPTO_AES_RNDKEY59 0x2EC
+
+#define CRYPTO_DATA_SHADOW0 0x8000
+#define CRYPTO_DATA_SHADOW8191 0x8FFC
+
+/* status reg */
+#define CRYPTO_CORE_REV 28 /* bit 31-28 */
+#define CRYPTO_CORE_REV_MASK (0xf << CRYPTO_CORE_REV)
+#define CRYPTO_DOUT_SIZE_AVAIL 22 /* bit 24-22 */
+#define CRYPTO_DOUT_SIZE_AVAIL_MASK (0x7 << CRYPTO_DOUT_SIZE_AVAIL)
+#define CRYPTO_DIN_SIZE_AVAIL 19 /* bit 21-19 */
+#define CRYPTO_DIN_SIZE_AVAIL_MASK (0x7 << CRYPTO_DIN_SIZE_AVAIL)
+#define CRYPTO_ACCESS_VIOL 18
+#define CRYPTO_SEG_CHNG_ERR 17
+#define CRYPTO_CFH_CHNG_ERR 16
+#define CRYPTO_DOUT_ERR 15
+#define CRYPTO_DIN_ERR 14
+#define CRYPTO_LOCKED 13
+#define CRYPTO_CRYPTO_STATE 10 /* bit 12-10 */
+#define CRYPTO_CRYPTO_STATE_MASK (0x7 << CRYPTO_CRYPTO_STATE)
+#define CRYPTO_ENCR_BUSY 9
+#define CRYPTO_AUTH_BUSY 8
+#define CRYPTO_DOUT_INTR 7
+#define CRYPTO_DIN_INTR 6
+#define CRYPTO_AUTH_DONE_INTR 5
+#define CRYPTO_ERR_INTR 4
+#define CRYPTO_DOUT_RDY 3
+#define CRYPTO_DIN_RDY 2
+#define CRYPTO_AUTH_DONE 1
+#define CRYPTO_SW_ERR 0
+
+#define CRYPTO_CRYPTO_STATE_IDLE 0
+#define CRYPTO_CRYPTO_STATE_LOCKED 1
+#define CRYPTO_CRYPTO_STATE_GO 3
+#define CRYPTO_CRYPTO_STATE_PROCESSING 4
+#define CRYPTO_CRYPTO_STATE_FINAL_READ 5
+#define CRYPTO_CRYPTO_STATE_CTXT_CLEARING 6
+#define CRYPTO_CRYPTO_STATE_UNLOCKING 7
+
+/* config reg */
+#define CRYPTO_HIGH_SPD_HASH_EN_N 15
+#define CRYPTO_HIGH_SPD_OUT_EN_N 14
+#define CRYPTO_HIGH_SPD_IN_EN_N 13
+#define CRYPTO_DBG_EN 12
+#define CRYPTO_DBG_SEL 7 /* bit 11:7 */
+#define CRYPTO_DBG_SEL_MASK (0x1F << CRYPTO_DBG_SEL)
+#define CRYPTO_MASK_DOUT_INTR 6
+#define CRYPTO_MASK_DIN_INTR 5
+#define CRYPTO_MASK_AUTH_DONE_INTR 4
+#define CRYPTO_MASK_ERR_INTR 3
+#define CRYPTO_AUTO_SHUTDOWN_EN 2
+#define CRYPTO_CLK_EN_N 1
+#define CRYPTO_SW_RST 0
+
+/* seg_cfg reg */
+#define CRYPTO_F8_KEYSTREAM_ENABLE 25
+#define CRYPTO_F9_DIRECTION 24
+#define CRYPTO_F8_DIRECTION 23
+#define CRYPTO_USE_HW_KEY 22
+
+#define CRYPTO_CNTR_ALG 20 /* bit 21-20 */
+#define CRYPTO_CNTR_ALG_MASK (3 << efine CRYPTO_CNTR_ALG)
+
+#define CRYPTO_CLR_CNTXT 19
+#define CRYPTO_LAST 18
+#define CRYPTO_FIRST 17
+#define CRYPTO_ENCODE 16
+
+#define CRYPTO_AUTH_POS 14 /* bit 15-14 */
+#define CRYPTO_AUTH_POS_MASK (3 << CRYPTO_AUTH_POS)
+
+#define CRYPTO_AUTH_SIZE 11 /* bit 13-11 */
+#define CRYPTO_AUTH_SIZE_MASK (7 << CRYPTO_AUTH_SIZE)
+
+#define CRYPTO_AUTH_ALG 9 /* bit 10-9 */
+#define CRYPTO_AUTH_ALG_MASK (3 << CRYPTO_AUTH_ALG)
+
+#define CRYPTO_ENCR_MODE 6 /* bit 8-6 */
+#define CRYPTO_ENCR_MODE_MASK (7 << CRYPTO_ENCR_MODE)
+
+#define CRYPTO_ENCR_KEY_SZ 3 /* bit 5-3 */
+#define CRYPTO_ENCR_KEY_SZ_MASK (7 << CRYPTO_ENCR_KEY_SZ)
+
+#define CRYPTO_ENCR_ALG 0 /* bit 2-0 */
+#define CRYPTO_ENCR_ALG_MASK (7 << CRYPTO_ENCR_ALG)
+
+#define CRYPTO_CNTR_ALG_NIST 0
+#define CRYPTO_CNTR_ALG_UMB 1
+#define CRYPTO_CNTR_ALG_VAR2 2
+
+#define CRYPTO_AUTH_POS_BEFORE 0
+#define CRYPTO_AUTH_POS_AFTER 1
+
+#define CRYPTO_AUTH_SIZE_SHA1 0
+#define CRYPTO_AUTH_SIZE_SHA256 1
+#define CRYPTO_AUTH_SIZE_SHA384 2
+#define CRYPTO_AUTH_SIZE_SHA512 3
+#define CRYPTO_AUTH_SIZE_HMAC_SHA1 4
+
+#define CRYPTO_AUTH_SIZE_UIA1 0
+#define CRYPTO_AUTH_SIZE_UIA2 1
+
+#define CRYPTO_AUTH_ALG_NONE 0
+#define CRYPTO_AUTH_ALG_SHA 1
+#define CRYPTO_AUTH_ALG_F9 2
+#define CRYPTO_AUTH_ALG_RESERVED1 3
+
+#define CRYPTO_ENCR_MODE_ECB 0
+#define CRYPTO_ENCR_MODE_CBC 1
+/* only valid when AES */
+#define CRYPTO_ENCR_MODE_CTR 2
+
+
+#define CRYPTO_ENCR_KEY_SZ_DES 0
+#define CRYPTO_ENCR_KEY_SZ_3DES 1
+
+#define CRYPTO_ENCR_KEY_SZ_AES128 0
+#define CRYPTO_ENCR_KEY_SZ_AES192 1
+#define CRYPTO_ENCR_KEY_SZ_AES256 2
+
+#define CRYPTO_ENCR_KEY_SZ_UEA1 0
+#define CRYPTO_ENCR_KEY_SZ_UEA2 1
+
+#define CRYPTO_ENCR_ALG_NONE 0
+#define CRYPTO_ENCR_ALG_DES 1
+#define CRYPTO_ENCR_ALG_AES 2
+#define CRYPTO_ENCR_ALG_C2 3
+#define CRYPTO_ENCR_ALG_F8 4
+
+/* encr_seg_cfg reg */
+#define CRYPTO_ENCR_SEG_SIZE 16 /* bit 31-16 */
+#define CRYPTO_ENCR_SEG_SIZE_MASK (0xffff << CRYPTO_ENCR_SEG_SIZE)
+
+#define CRYPTO_ENCR_START 0
+#define CRYPTO_ENCR_START_MASK (0xffff << CRYPTO_ENCR_START)
+
+/* auth_seg_cfg reg */
+#define CRYPTO_AUTH_SEG_SIZE 16 /* bit 31-16 */
+#define CRYPTO_AUTH_SEG_SIZE_MASK (0xffff << CRYPTO_AUTH_SEG_SIZE)
+
+#define CRYPTO_AUTH_START 0
+#define CRYPTO_AUTH_START_MASK (0xffff << CRYPTO_AUTH_START)
+
+
+/* seg_size reg */
+#define CRYPTO_SEG_SIZE 0
+#define CRYPTO_SEG_SIZE_MASK (0xffff << CRYPTO_SEG_SIZE)
+
+/* goproc reg */
+#define CRYPTO_GO 0
+
+/* engines_avail */
+#define CRYPTO_F9_SEL 8
+#define CRYPTO_F8_SEL 7
+#define CRYPTO_HMAC_SEL 6
+#define CRYPTO_SHA512_SEL 5
+#define CRYPTO_SHA_SEL 4
+#define CRYPTO_DES_SEL 3
+#define CRYPTO_C2_SEL 2
+
+#define CRYPTO_AES_SEL 0 /* bit 1-0 */
+#define CRYPTO_AES_SEL_MASK (3 << CRYPTO_AES_SEL)
+#define CRYPTO_AES_SEL_NO 0
+#define CRYPTO_AES_SEL_SLOW 1
+#define CRYPTO_AES_SEL_FAST 2
+#define CRYPTO_AES_SEL_RESERVED 3
+
+/* F8 definition of CRYPTO_CNTR1_IV1_REG */
+#define CRYPTO_CNTR1_IV1_REG_F8_PKT_CNT 16 /* bit 31 - 16 */
+#define CRYPTO_CNTR1_IV1_REG_F8_PKT_CNT_MASK \
+ (0xffff << CRYPTO_CNTR1_IV1_REG_F8_PKT_CNT)
+
+#define CRYPTO_CNTR1_IV1_REG_F8_BEARER 0 /* bit 4 - 0 */
+#define CRYPTO_CNTR1_IV1_REG_F8_BEARER_MASK \
+ (0x1f << CRYPTO_CNTR1_IV1_REG_F8_BEARER)
+
+/* F9 definition of CRYPTO_AUTH_IV4_REG */
+#define CRYPTO_AUTH_IV4_REG_F9_VALID_BIS 0 /* bit 2 - 0 */
+#define CRYPTO_AUTH_IV4_REG_F9_VALID_BIS_MASK \
+ (0x7 << CRYPTO_AUTH_IV4_REG_F9_VALID_BIS)
+
+/* misc */
+#define CRYPTO_AES_RNDKEYS 60
+
+#endif /* _DRIVERS_CRYPTO_MSM_QCRYPTOHW_30_H_ */
diff --git a/drivers/crypto/msm/inc/qcryptohw_40.h b/drivers/crypto/msm/inc/qcryptohw_40.h
new file mode 100644
index 0000000..367bdaa
--- /dev/null
+++ b/drivers/crypto/msm/inc/qcryptohw_40.h
@@ -0,0 +1,316 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DRIVERS_CRYPTO_MSM_QCRYPTOHW_40_H_
+#define _DRIVERS_CRYPTO_MSM_QCRYPTOHW_40_H_
+
+
+#define QCE_AUTH_REG_BYTE_COUNT 4
+#define CRYPTO_VERSION_REG 0x0
+#define CRYPTO_DATA_IN_REG 0x008
+#define CRYPTO_DATA_OUT_REG 0x010
+#define CRYPTO_STATUS_REG 0x100
+#define CRYPTO_ENGINES_AVAIL 0x104
+#define CRYPTO3_VERSION_REG 0x108
+#define CRYPTO_SEG_SIZE_REG 0x200
+#define CRYPTO_GOPROC_REG 0x204
+#define CRYPTO_ENCR_SEG_CFG_REG 0x300
+
+#define CRYPTO_ENCR_SEG_SIZE_REG 0x304
+#define CRYPTO_ENCR_SEG_START_REG 0x308
+
+#define CRYPTO_ENCR_KEY0_REG 0x310
+#define CRYPTO_ENCR_KEY1_REG 0x314
+#define CRYPTO_ENCR_KEY2_REG 0x318
+#define CRYPTO_ENCR_KEY3_REG 0x31C
+#define CRYPTO_ENCR_KEY4_REG 0x320
+#define CRYPTO_ENCR_KEY5_REG 0x324
+#define CRYPTO_ENCR_KEY6_REG 0x328
+#define CRYPTO_ENCR_KEY7_REG 0x32C
+
+#define CRYPTO_ENCR_XTS_KEY0_REG 0x330
+#define CRYPTO_ENCR_XTS_KEY1_REG 0x334
+#define CRYPTO_ENCR_XTS_KEY2_REG 0x338
+#define CRYPTO_ENCR_XTS_KEY3_REG 0x33C
+#define CRYPTO_ENCR_XTS_KEY4_REG 0x340
+#define CRYPTO_ENCR_XTS_KEY5_REG 0x344
+#define CRYPTO_ENCR_XTS_KEY6_REG 0x348
+#define CRYPTO_ENCR_XTS_KEY7_REG 0x34C
+
+#define CRYPTO_CNTR0_IV0_REG 0x350
+#define CRYPTO_CNTR1_IV1_REG 0x354
+#define CRYPTO_CNTR2_IV2_REG 0x358
+#define CRYPTO_CNTR3_IV3_REG 0x35C
+
+#define CRYPTO_CNTR_MASK_REG 0x360
+
+#define CRYPTO_ENCR_XTS_DU_SIZE_REG 0x364
+
+#define CRYPTO_AUTH_SEG_CFG_REG 0x400
+#define CRYPTO_AUTH_SEG_SIZE_REG 0x404
+#define CRYPTO_AUTH_SEG_START_REG 0x408
+
+#define CRYPTO_AUTH_KEY0_REG 0x410
+#define CRYPTO_AUTH_KEY1_REG 0x414
+#define CRYPTO_AUTH_KEY2_REG 0x418
+#define CRYPTO_AUTH_KEY3_REG 0x41C
+#define CRYPTO_AUTH_KEY4_REG 0x420
+#define CRYPTO_AUTH_KEY5_REG 0x424
+#define CRYPTO_AUTH_KEY6_REG 0x428
+#define CRYPTO_AUTH_KEY7_REG 0x42C
+#define CRYPTO_AUTH_KEY8_REG 0x430
+#define CRYPTO_AUTH_KEY9_REG 0x434
+#define CRYPTO_AUTH_KEY10_REG 0x438
+#define CRYPTO_AUTH_KEY11_REG 0x43C
+#define CRYPTO_AUTH_KEY12_REG 0x440
+#define CRYPTO_AUTH_KEY13_REG 0x444
+#define CRYPTO_AUTH_KEY14_REG 0x448
+#define CRYPTO_AUTH_KEY15_REG 0x44C
+
+#define CRYPTO_AUTH_IV0_REG 0x450
+#define CRYPTO_AUTH_IV1_REG 0x454
+#define CRYPTO_AUTH_IV2_REG 0x458
+#define CRYPTO_AUTH_IV3_REG 0x45C
+#define CRYPTO_AUTH_IV4_REG 0x460
+#define CRYPTO_AUTH_IV5_REG 0x464
+#define CRYPTO_AUTH_IV6_REG 0x468
+#define CRYPTO_AUTH_IV7_REG 0x46C
+#define CRYPTO_AUTH_IV8_REG 0x470
+#define CRYPTO_AUTH_IV9_REG 0x474
+#define CRYPTO_AUTH_IV10_REG 0x478
+#define CRYPTO_AUTH_IV11_REG 0x47C
+#define CRYPTO_AUTH_IV12_REG 0x480
+#define CRYPTO_AUTH_IV13_REG 0x484
+#define CRYPTO_AUTH_IV14_REG 0x488
+#define CRYPTO_AUTH_IV15_REG 0x48C
+
+#define CRYPTO_AUTH_INFO_NONCE0_REG 0x490
+#define CRYPTO_AUTH_INFO_NONCE1_REG 0x494
+#define CRYPTO_AUTH_INFO_NONCE2_REG 0x498
+#define CRYPTO_AUTH_INFO_NONCE3_REG 0x49C
+
+#define CRYPTO_AUTH_BYTECNT0_REG 0x4A0
+#define CRYPTO_AUTH_BYTECNT1_REG 0x4A4
+#define CRYPTO_AUTH_BYTECNT2_REG 0x4A8
+#define CRYPTO_AUTH_BYTECNT3_REG 0x4AC
+
+#define CRYPTO_AUTH_EXP_MAC0_REG 0x4B0
+#define CRYPTO_AUTH_EXP_MAC1_REG 0x4B4
+#define CRYPTO_AUTH_EXP_MAC2_REG 0x4B8
+#define CRYPTO_AUTH_EXP_MAC3_REG 0x4BC
+#define CRYPTO_AUTH_EXP_MAC4_REG 0x4C0
+#define CRYPTO_AUTH_EXP_MAC5_REG 0x4C4
+#define CRYPTO_AUTH_EXP_MAC6_REG 0x4C8
+#define CRYPTO_AUTH_EXP_MAC7_REG 0x4CC
+
+#define CRYPTO_CONFIG_REG 0x500
+#define CRYPTO_SACR_REG 0x504
+#define CRYPTO_DEBUG_REG 0x508
+
+#define CRYPTO_DATA_SHADOW0 0x8000
+#define CRYPTO_DATA_SHADOW8191 0x8FFC
+
+
+/* Register bits */
+
+#define CRYPTO_CORE_MAJOR_REV 4 /* bit 7-4 */
+#define CRYPTO_CORE_MAJOR_REV_MASK (0xF << CRYPTO_CORE_MAJOR_REV)
+#define CRYPTO_CORE_MINOR_REV 0 /* bit 3-0 */
+#define CRYPTO_CORE_MINOR_REV_MASK (0xF << CRYPTO_CORE_MINOR_REV)
+#define CRYPTO_CORE_REV_MASK 0xFF
+
+/* status reg */
+#define CRYPTO_MAC_FAILED 25
+#define CRYPTO_DOUT_SIZE_AVAIL 22 /* bit 24-22 */
+#define CRYPTO_DOUT_SIZE_AVAIL_MASK (0x7 << CRYPTO_DOUT_SIZE_AVAIL)
+#define CRYPTO_DIN_SIZE_AVAIL 19 /* bit 21-19 */
+#define CRYPTO_DIN_SIZE_AVAIL_MASK (0x7 << CRYPTO_DIN_SIZE_AVAIL)
+#define CRYPTO_ACCESS_VIOL 18
+#define CRYPTO_SEG_CHNG_ERR 17
+#define CRYPTO_CFH_CHNG_ERR 16
+#define CRYPTO_DOUT_ERR 15
+#define CRYPTO_DIN_ERR 14
+#define CRYPTO_LOCKED 13
+#define CRYPTO_CRYPTO_STATE 10 /* bit 12-10 */
+#define CRYPTO_CRYPTO_STATE_MASK (0x7 << CRYPTO_CRYPTO_STATE)
+#define CRYPTO_ENCR_BUSY 9
+#define CRYPTO_AUTH_BUSY 8
+#define CRYPTO_DOUT_INTR 7
+#define CRYPTO_DIN_INTR 6
+#define CRYPTO_OP_DONE_INTR 5
+#define CRYPTO_ERR_INTR 4
+#define CRYPTO_DOUT_RDY 3
+#define CRYPTO_DIN_RDY 2
+#define CRYPTO_OPERATION_DONE 1
+#define CRYPTO_SW_ERR 0
+
+/* config reg */
+#define CRYPTO_REQ_SIZE 30 /* bit 31-30 */
+#define CRYPTO_REQ_SIZE_MASK (0x3 << CRYPTO_REQ_SIZE)
+#define CRYPTO_REQ_SIZE_ENUM_16_BYTES 0
+#define CRYPTO_REQ_SIZE_ENUM_32_BYTES 1
+#define CRYPTO_REQ_SIZE_ENUM_64_BYTES 2
+
+#define CRYPTO_MAX_QUEUED_REQ 27 /* bit 29-27 */
+#define CRYPTO_MAX_QUEUED_REQ_MASK (0x7 << CRYPTO_MAX_QUEUED_REQ)
+#define CRYPTO_ENUM1_QUEUED_REQS 0
+#define CRYPTO_ENUM2_QUEUED_REQS 1
+#define CRYPTO_ENUM3_QUEUED_REQS 2
+#define CRYPTO_ENUM4_QUEUED_REQS 3
+
+#define CRYPTO_FIFO_THRESHOLD 24 /* bit 26-24 */
+#define CRYPTO_FIFO_THRESHOLD_MASK (0x7 << CRYPTO_FIFO_THRESHOLD)
+#define CRYPTO_FIFO_ENUM_16_BYTES 0
+#define CRYPTO_FIFO_ENUM_32_BYTES 1
+#define CRYPTO_FIFO_ENUM_48_BYTES 2
+#define CRYPTO_FIFO_ENUM_64_BYTES 3
+
+#define CRYPTO_IRQ_ENABLES 20 /* bit 23-20 */
+#define CRYPTO_IRQ_ENABLES_MASK (0xF << CRYPTO_IRQ_ENABLES)
+
+#define CRYPTO_ACR_EN 18
+#define CRYPTO_BAM_MODE 17
+#define CRYPTO_LITTLE_ENDIAN_MODE 16
+#define CRYPTO_HIGH_SPD_OUT_EN_N 14
+#define CRYPTO_HIGH_SPD_IN_EN_N 13
+#define CRYPTO_DBG_EN 12
+
+#define CRYPTO_DBG_SEL 7 /* bit 11:7 */
+#define CRYPTO_DBG_SEL_MASK (0x1F << CRYPTO_DBG_SEL)
+
+#define CRYPTO_MASK_DOUT_INTR 6
+#define CRYPTO_MASK_DIN_INTR 5
+#define CRYPTO_MASK_OP_DONE_INTR 4
+#define CRYPTO_MASK_ERR_INTR 3
+#define CRYPTO_AUTO_SHUTDOWN_EN 2
+#define CRYPTO_CLK_EN_N 1
+
+/* auth_seg_cfg reg */
+#define CRYPTO_COMP_EXP_MAC 20
+#define CRYPTO_COMP_EXP_MAC_DISABLED 0
+#define CRYPTO_COMP_EXP_MAC_ENABLED 1
+
+#define CRYPTO_F9_DIRECTION 19
+#define CRYPTO_F9_DIRECTION_UPLINK 0
+#define CRYPTO_F9_DIRECTION_DOWNLINK 1
+
+#define CRYPTO_AUTH_NONCE_NUM_WORDS 16
+#define CRYPTO_AUTH_NONCE_NUM_WORDS_MASK \
+ (0x7 << CRYPTO_AUTH_NONCE_NUM_WORDS)
+
+#define CRYPTO_USE_HW_KEY_AUTH 15
+
+#define CRYPTO_LAST 14
+
+#define CRYPTO_AUTH_POS 12 /* bit 13 .. 12*/
+#define CRYPTO_AUTH_POS_MASK (0x3 << CRYPTO_AUTH_POS)
+#define CRYPTO_AUTH_POS_BEFORE 0
+#define CRYPTO_AUTH_POS_AFTER 1
+
+#define CRYPTO_AUTH_SIZE 9 /* bits 11 .. 9*/
+#define CRYPTO_AUTH_SIZE_MASK (0x7 << CRYPTO_AUTH_SIZE)
+#define CRYPTO_AUTH_SIZE_SHA1 0
+#define CRYPTO_AUTH_SIZE_SHA256 1
+#define CRYPTO_AUTH_SIZE_ENUM_4_BYTES 0
+#define CRYPTO_AUTH_SIZE_ENUM_6_BYTES 1
+#define CRYPTO_AUTH_SIZE_ENUM_8_BYTES 2
+#define CRYPTO_AUTH_SIZE_ENUM_10_BYTES 3
+#define CRYPTO_AUTH_SIZE_ENUM_12_BYTES 4
+#define CRYPTO_AUTH_SIZE_ENUM_14_BYTES 5
+#define CRYPTO_AUTH_SIZE_ENUM_16_BYTES 6
+
+#define CRYPTO_AUTH_MODE 6 /* bit 8 .. 6*/
+#define CRYPTO_AUTH_MODE_MASK (0x7 << CRYPTO_AUTH_MODE)
+#define CRYPTO_AUTH_MODE_HASH 0
+#define CRYPTO_AUTH_MODE_HMAC 1
+#define CRYPTO_AUTH_MODE_CCM 0
+#define CRYPTO_AUTH_MODE_CMAC 1
+
+#define CRYPTO_AUTH_KEY_SIZE 3
+#define CRYPTO_AUTH_KEY_SIZE_MASK (0x7 << CRYPTO_AUTH_KEY_SIZE)
+#define CRYPTO_AUTH_KEY_SZ_AES128 0
+#define CRYPTO_AUTH_KEY_SZ_AES256 2
+
+#define CRYPTO_AUTH_ALG 0 /* bit 2 .. 0*/
+#define CRYPTO_AUTH_ALG_MASK 7
+#define CRYPTO_AUTH_ALG_NONE 0
+#define CRYPTO_AUTH_ALG_SHA 1
+#define CRYPTO_AUTH_ALG_AES 2
+#define CRYPTO_AUTH_ALG_KASUMI 3
+#define CRYPTO_AUTH_ALG_SNOW3G 4
+
+/* encr_xts_du_size reg */
+#define CRYPTO_ENCR_XTS_DU_SIZE 0 /* bit 19-0 */
+#define CRYPTO_ENCR_XTS_DU_SIZE_MASK 0xfffff
+
+/* encr_seg_cfg reg */
+#define CRYPTO_F8_KEYSTREAM_ENABLE 15
+#define CRYPTO_F8_KEYSTREAM_DISABLED 0
+#define CRYPTO_F8_KEYSTREAM_ENABLED 1
+
+#define CRYPTO_F8_DIRECTION 14
+#define CRYPTO_F8_DIRECTION_UPLINK 0
+#define CRYPTO_F8_DIRECTION_DOWNLINK 1
+
+#define CRYPTO_USE_HW_KEY_ENCR 13
+#define CRYPTO_USE_HW_KEY_REG 0
+#define CRYPTO_USE_HW_KEY 1
+
+#define CRYPTO_CNTR_ALG 11 /* bit 12-11 */
+#define CRYPTO_CNTR_ALG_MASK (3 << CRYPTO_CNTR_ALG)
+#define CRYPTO_CNTR_ALG_NIST 0
+
+#define CRYPTO_ENCODE 10
+
+#define CRYPTO_ENCR_MODE 6 /* bit 9-6 */
+#define CRYPTO_ENCR_MODE_MASK (0xF << CRYPTO_ENCR_MODE)
+/* only valid when AES */
+#define CRYPTO_ENCR_MODE_ECB 0
+#define CRYPTO_ENCR_MODE_CBC 1
+#define CRYPTO_ENCR_MODE_CTR 2
+#define CRYPTO_ENCR_MODE_XTS 3
+#define CRYPTO_ENCR_MODE_CCM 4
+
+#define CRYPTO_ENCR_KEY_SZ 3 /* bit 5-3 */
+#define CRYPTO_ENCR_KEY_SZ_MASK (7 << CRYPTO_ENCR_KEY_SZ)
+#define CRYPTO_ENCR_KEY_SZ_DES 0
+#define CRYPTO_ENCR_KEY_SZ_3DES 1
+#define CRYPTO_ENCR_KEY_SZ_AES128 0
+#define CRYPTO_ENCR_KEY_SZ_AES256 2
+#define CRYPTO_ENCR_KEY_SZ_UEA1 0
+#define CRYPTO_ENCR_KEY_SZ_UEA2 1
+
+#define CRYPTO_ENCR_ALG 0 /* bit 2-0 */
+#define CRYPTO_ENCR_ALG_MASK (7 << CRYPTO_ENCR_ALG)
+#define CRYPTO_ENCR_ALG_NONE 0
+#define CRYPTO_ENCR_ALG_DES 1
+#define CRYPTO_ENCR_ALG_AES 2
+#define CRYPTO_ENCR_ALG_KASUMI 3
+#define CRYPTO_ENCR_ALG_SNOW_3G 5
+
+/* goproc reg */
+#define CRYPTO_GO 0
+#define CRYPTO_CLR_CNTXT 1
+
+/* engines_avail */
+#define CRYPTO_ENCR_AES_SEL 0
+#define CRYPTO_DES_SEL 3
+#define CRYPTO_ENCR_SNOW3G_SEL 4
+#define CRYPTO_ENCR_KASUMI_SEL 5
+#define CRYPTO_SHA_SEL 6
+#define CRYPTO_SHA512_SEL 7
+#define CRYPTO_AUTH_AES_SEL 8
+#define CRYPTO_AUTH_SNOW3G_SEL 9
+#define CRYPTO_AUTH_KASUMI_SEL 10
+#define CRYPTO_BAM_SEL 11
+
+#endif /* _DRIVERS_CRYPTO_MSM_QCRYPTOHW_40_H_ */