Initial Contribution
msm-2.6.38: tag AU_LINUX_ANDROID_GINGERBREAD.02.03.04.00.142
Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index d7ed20f..3ebf2aa 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -303,5 +303,47 @@
help
This driver supports TPS65910 voltage regulator chips.
+config REGULATOR_PMIC8058
+ tristate "PMIC8058 regulator driver"
+ depends on PMIC8058 && (ARCH_MSM8X60 || ARCH_FSM9XXX)
+ default y if PMIC8058 && (ARCH_MSM8X60 || ARCH_FSM9XXX)
+ help
+ Say Y here to support the voltage regulators on PMIC8058
+
+config REGULATOR_PMIC8901
+ tristate "PMIC8901 regulator driver"
+ depends on PMIC8901 && ARCH_MSM8X60
+ default y if PMIC8901 && ARCH_MSM8X60
+ help
+ Say Y here to support the voltage regulators on PMIC8901
+
+config REGULATOR_PM8921
+ tristate "Qualcomm PM8921 PMIC Power regulators"
+ depends on MFD_PM8921_CORE
+ default y if MFD_PM8921_CORE
+ help
+ This driver supports voltage regulators in the Qualcomm PM8921 PMIC
+ chip. The PM8921 provides several different varieties of LDO and
+ switching regulators. It also provides a negative charge pump and
+ voltage switches.
+
+config REGULATOR_GPIO
+ tristate "GPIO regulator"
+ depends on GPIOLIB
+ help
+ This driver provides a regulator wrapper around a GPIO pin that is set
+ to output. It is intended to be used for GPIO pins that provide the
+ enable signal to a physical regulator. The GPIO enable signal can
+ be configured to be active high (default) or active low.
+
+config REGULATOR_PM8058_XO
+ tristate "PM8058 XO Buffer driver"
+ depends on PMIC8058
+ default n
+ help
+ This driver supports xo buffer control in the Qualcomm PM8058 PMIC
+ chip. It is only supposed to be used when Linux on application
+ processor is the master in control of XO buffers.
+
endif
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 3932d2e..1dfaa3c 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -43,5 +43,10 @@
obj-$(CONFIG_REGULATOR_AB8500) += ab8500.o
obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
obj-$(CONFIG_REGULATOR_TPS65910) += tps65910-regulator.o
+obj-$(CONFIG_REGULATOR_PMIC8058) += pmic8058-regulator.o
+obj-$(CONFIG_REGULATOR_PMIC8901) += pmic8901-regulator.o
+obj-$(CONFIG_REGULATOR_PM8921) += pm8921-regulator.o
+obj-$(CONFIG_REGULATOR_GPIO) += gpio-regulator.o
+obj-$(CONFIG_REGULATOR_PM8058_XO) += pm8058-xo.o
ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index d3e3879..d4d055d 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -24,6 +24,9 @@
#include <linux/mutex.h>
#include <linux/suspend.h>
#include <linux/delay.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/uaccess.h>
#include <linux/regulator/consumer.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
@@ -47,6 +50,7 @@
static LIST_HEAD(regulator_map_list);
static bool has_full_constraints;
static bool board_wants_dummy_regulator;
+static int suppress_info_printing;
#ifdef CONFIG_DEBUG_FS
static struct dentry *debugfs_root;
@@ -75,6 +79,7 @@
int uA_load;
int min_uV;
int max_uV;
+ int enabled;
char *supply_name;
struct device_attribute dev_attr;
struct regulator_dev *rdev;
@@ -138,6 +143,15 @@
return -EPERM;
}
+ /* check if requested voltage range actually overlaps the constraints */
+ if (*max_uV < rdev->constraints->min_uV ||
+ *min_uV > rdev->constraints->max_uV) {
+ rdev_err(rdev, "requested voltage range [%d, %d] does not fit "
+ "within constraints: [%d, %d]\n", *min_uV, *max_uV,
+ rdev->constraints->min_uV, rdev->constraints->max_uV);
+ return -EINVAL;
+ }
+
if (*max_uV > rdev->constraints->max_uV)
*max_uV = rdev->constraints->max_uV;
if (*min_uV < rdev->constraints->min_uV)
@@ -587,13 +601,87 @@
.dev_attrs = regulator_dev_attrs,
};
+static int regulator_check_voltage_update(struct regulator_dev *rdev)
+{
+ if (!rdev->constraints)
+ return -ENODEV;
+ if (!(rdev->constraints->valid_ops_mask & REGULATOR_CHANGE_VOLTAGE))
+ return -EPERM;
+ if (!rdev->desc->ops->set_voltage)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int update_voltage(struct regulator *regulator, int min_uV, int max_uV)
+{
+ struct regulator_dev *rdev = regulator->rdev;
+ struct regulator *sibling;
+ int ret = 0;
+
+ list_for_each_entry(sibling, &rdev->consumer_list, list) {
+ if (regulator == sibling || !sibling->enabled)
+ continue;
+ if (max_uV < sibling->min_uV || min_uV > sibling->max_uV) {
+ printk(KERN_ERR "%s: requested voltage range [%d, %d] "
+ "for %s does not fit within previously voted "
+ "range: [%d, %d]\n",
+ __func__, min_uV, max_uV,
+ rdev_get_name(regulator->rdev),
+ sibling->min_uV,
+ sibling->max_uV);
+ ret = -EINVAL;
+ goto out;
+ }
+ if (sibling->max_uV < max_uV)
+ max_uV = sibling->max_uV;
+ if (sibling->min_uV > min_uV)
+ min_uV = sibling->min_uV;
+ }
+
+ ret = _regulator_do_set_voltage(rdev, min_uV, max_uV);
+ if (!ret)
+ goto out;
+
+ _notifier_call_chain(rdev, REGULATOR_EVENT_VOLTAGE_CHANGE, NULL);
+
+out:
+ return ret;
+}
+
+static int update_voltage_prev(struct regulator_dev *rdev)
+{
+ int ret, min_uV = INT_MIN, max_uV = INT_MAX;
+ struct regulator *consumer;
+
+ list_for_each_entry(consumer, &rdev->consumer_list, list) {
+ if (!consumer->enabled)
+ continue;
+ if (consumer->max_uV < max_uV)
+ max_uV = consumer->max_uV;
+ if (consumer->min_uV > min_uV)
+ min_uV = consumer->min_uV;
+ }
+
+ if (min_uV == INT_MIN)
+ return 0;
+
+ ret = _regulator_do_set_voltage(rdev, min_uV, max_uV);
+ if (!ret)
+ return ret;
+
+ _notifier_call_chain(rdev, REGULATOR_EVENT_VOLTAGE_CHANGE, NULL);
+
+ return ret;
+}
+
/* Calculate the new optimum regulator operating mode based on the new total
* consumer load. All locks held by caller */
static void drms_uA_update(struct regulator_dev *rdev)
{
struct regulator *sibling;
int current_uA = 0, output_uV, input_uV, err;
- unsigned int mode;
+ unsigned int regulator_curr_mode, mode;
err = regulator_check_drms(rdev);
if (err < 0 || !rdev->desc->ops->get_optimum_mode ||
@@ -626,6 +714,14 @@
/* check the new mode is allowed */
err = regulator_mode_constrain(rdev, &mode);
+ /* return if the same mode is requested */
+ if (rdev->desc->ops->get_mode) {
+ regulator_curr_mode = rdev->desc->ops->get_mode(rdev);
+ if (regulator_curr_mode == mode)
+ return;
+ } else
+ return;
+
if (err == 0)
rdev->desc->ops->set_mode(rdev, mode);
}
@@ -914,7 +1010,8 @@
}
}
- print_constraints(rdev);
+ if (!suppress_info_printing)
+ print_constraints(rdev);
out:
return ret;
}
@@ -1389,7 +1486,33 @@
int ret = 0;
mutex_lock(&rdev->mutex);
+
+ if (!regulator_check_voltage_update(rdev)) {
+ if (regulator->min_uV < rdev->constraints->min_uV ||
+ regulator->max_uV > rdev->constraints->max_uV) {
+ rdev_err(rdev, "invalid input - constraint: [%d, %d], "
+ "set point: [%d, %d]\n",
+ rdev->constraints->min_uV,
+ rdev->constraints->max_uV,
+ regulator->min_uV,
+ regulator->max_uV);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ret = update_voltage(regulator, regulator->min_uV,
+ regulator->max_uV);
+ if (ret)
+ goto out;
+ }
+
ret = _regulator_enable(rdev);
+ if (ret)
+ goto out;
+
+ regulator->enabled++;
+
+out:
mutex_unlock(&rdev->mutex);
return ret;
}
@@ -1463,6 +1586,15 @@
mutex_lock(&rdev->mutex);
ret = _regulator_disable(rdev, &supply_rdev);
+ if (ret)
+ goto out;
+
+ regulator->enabled--;
+
+ if (!regulator_check_voltage_update(rdev))
+ update_voltage_prev(rdev);
+
+out:
mutex_unlock(&rdev->mutex);
/* decrease our supplies ref count and disable if required */
@@ -1770,15 +1902,16 @@
ret = regulator_check_voltage(rdev, &min_uV, &max_uV);
if (ret < 0)
goto out;
+
+ if (regulator->enabled) {
+ ret = update_voltage(regulator, min_uV, max_uV);
+ if (ret)
+ goto out;
+ }
+
regulator->min_uV = min_uV;
regulator->max_uV = max_uV;
- ret = regulator_check_consumers(rdev, &min_uV, &max_uV);
- if (ret < 0)
- goto out;
-
- ret = _regulator_do_set_voltage(rdev, min_uV, max_uV);
-
out:
mutex_unlock(&rdev->mutex);
return ret;
@@ -2514,22 +2647,356 @@
return status;
}
+#ifdef CONFIG_DEBUG_FS
+
+#define MAX_DEBUG_BUF_LEN 50
+
+static DEFINE_MUTEX(debug_buf_mutex);
+static char debug_buf[MAX_DEBUG_BUF_LEN];
+
+static int reg_debug_enable_set(void *data, u64 val)
+{
+ int err_info;
+ if (IS_ERR(data) || data == NULL) {
+ pr_err("Function Input Error %ld\n", PTR_ERR(data));
+ return -ENOMEM;
+ }
+
+ if (val)
+ err_info = regulator_enable(data);
+ else
+ err_info = regulator_disable(data);
+
+ return err_info;
+}
+
+static int reg_debug_enable_get(void *data, u64 *val)
+{
+ if (IS_ERR(data) || data == NULL) {
+ pr_err("Function Input Error %ld\n", PTR_ERR(data));
+ return -ENOMEM;
+ }
+
+ *val = regulator_is_enabled(data);
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(reg_enable_fops, reg_debug_enable_get,
+ reg_debug_enable_set, "%llu\n");
+
+static int reg_debug_fdisable_set(void *data, u64 val)
+{
+ int err_info;
+ if (IS_ERR(data) || data == NULL) {
+ pr_err("Function Input Error %ld\n", PTR_ERR(data));
+ return -ENOMEM;
+ }
+
+ if (val > 0)
+ err_info = regulator_force_disable(data);
+ else
+ err_info = 0;
+
+ return err_info;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(reg_fdisable_fops, reg_debug_enable_get,
+ reg_debug_fdisable_set, "%llu\n");
+
+static ssize_t reg_debug_volt_set(struct file *file, const char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ int err_info, filled;
+ int min, max = -1;
+ if (IS_ERR(file) || file == NULL) {
+ pr_err("Function Input Error %ld\n", PTR_ERR(file));
+ return -ENOMEM;
+ }
+
+ if (count < MAX_DEBUG_BUF_LEN) {
+ mutex_lock(&debug_buf_mutex);
+
+ if (copy_from_user(debug_buf, (void __user *) buf, count))
+ return -EFAULT;
+
+ debug_buf[count] = '\0';
+ filled = sscanf(debug_buf, "%d %d", &min, &max);
+
+ mutex_unlock(&debug_buf_mutex);
+ /* check that user entered two numbers */
+ if (filled < 2 || min < 0 || max < min) {
+ pr_info("Error, correct format: 'echo \"min max\""
+ " > voltage");
+ return -ENOMEM;
+ } else {
+ err_info = regulator_set_voltage(file->private_data,
+ min, max);
+ }
+ } else {
+ pr_err("Error-Input voltage pair"
+ " string exceeds maximum buffer length");
+
+ return -ENOMEM;
+ }
+
+ return count;
+}
+
+static ssize_t reg_debug_volt_get(struct file *file, char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ int voltage, output, rc;
+ if (IS_ERR(file) || file == NULL) {
+ pr_err("Function Input Error %ld\n", PTR_ERR(file));
+ return -ENOMEM;
+ }
+
+ voltage = regulator_get_voltage(file->private_data);
+ mutex_lock(&debug_buf_mutex);
+
+ output = snprintf(debug_buf, MAX_DEBUG_BUF_LEN-1, "%d\n", voltage);
+ rc = simple_read_from_buffer((void __user *) buf, output, ppos,
+ (void *) debug_buf, output);
+
+ mutex_unlock(&debug_buf_mutex);
+
+ return rc;
+}
+
+static int reg_debug_volt_open(struct inode *inode, struct file *file)
+{
+ if (IS_ERR(file) || file == NULL) {
+ pr_err("Function Input Error %ld\n", PTR_ERR(file));
+ return -ENOMEM;
+ }
+
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+static const struct file_operations reg_volt_fops = {
+ .write = reg_debug_volt_set,
+ .open = reg_debug_volt_open,
+ .read = reg_debug_volt_get,
+};
+
+static int reg_debug_mode_set(void *data, u64 val)
+{
+ int err_info;
+ if (IS_ERR(data) || data == NULL) {
+ pr_err("Function Input Error %ld\n", PTR_ERR(data));
+ return -ENOMEM;
+ }
+
+ err_info = regulator_set_mode(data, (unsigned int)val);
+
+ return err_info;
+}
+
+static int reg_debug_mode_get(void *data, u64 *val)
+{
+ int err_info;
+ if (IS_ERR(data) || data == NULL) {
+ pr_err("Function Input Error %ld\n", PTR_ERR(data));
+ return -ENOMEM;
+ }
+
+ err_info = regulator_get_mode(data);
+
+ if (err_info < 0) {
+ pr_err("Regulator_get_mode returned an error!\n");
+ return -ENOMEM;
+ } else {
+ *val = err_info;
+ return 0;
+ }
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(reg_mode_fops, reg_debug_mode_get,
+ reg_debug_mode_set, "%llu\n");
+
+static int reg_debug_optimum_mode_set(void *data, u64 val)
+{
+ int err_info;
+ if (IS_ERR(data) || data == NULL) {
+ pr_err("Function Input Error %ld\n", PTR_ERR(data));
+ return -ENOMEM;
+ }
+
+ err_info = regulator_set_optimum_mode(data, (unsigned int)val);
+
+ if (err_info < 0) {
+ pr_err("Regulator_set_optimum_mode returned an error!\n");
+ return err_info;
+ }
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(reg_optimum_mode_fops, reg_debug_mode_get,
+ reg_debug_optimum_mode_set, "%llu\n");
+
+static int reg_debug_consumers_show(struct seq_file *m, void *v)
+{
+ struct regulator_dev *rdev = m->private;
+ struct regulator *reg;
+ char *supply_name;
+
+ if (!rdev) {
+ pr_err("regulator device missing");
+ return -EINVAL;
+ }
+
+ mutex_lock(&rdev->mutex);
+
+ /* Print a header if there are consumers. */
+ if (rdev->open_count)
+ seq_printf(m, "Device-Supply "
+ "EN Min_uV Max_uV load_uA\n");
+
+ list_for_each_entry(reg, &rdev->consumer_list, list) {
+ if (reg->supply_name)
+ supply_name = reg->supply_name;
+ else
+ supply_name = "(null)-(null)";
+
+ seq_printf(m, "%-32s %c %8d %8d %8d\n", supply_name,
+ (reg->enabled ? 'Y' : 'N'), reg->min_uV, reg->max_uV,
+ reg->uA_load);
+ }
+
+ mutex_unlock(&rdev->mutex);
+
+ return 0;
+}
+
+static int reg_debug_consumers_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, reg_debug_consumers_show, inode->i_private);
+}
+
+static const struct file_operations reg_consumers_fops = {
+ .owner = THIS_MODULE,
+ .open = reg_debug_consumers_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
static void rdev_init_debugfs(struct regulator_dev *rdev)
{
-#ifdef CONFIG_DEBUG_FS
+ struct dentry *err_ptr = NULL;
+ struct regulator *reg;
+ struct regulator_ops *reg_ops;
+ mode_t mode;
+
+ if (IS_ERR(rdev) || rdev == NULL ||
+ IS_ERR(debugfs_root) || debugfs_root == NULL) {
+ pr_err("Error-Bad Function Input\n");
+ goto error;
+ }
+
rdev->debugfs = debugfs_create_dir(rdev_get_name(rdev), debugfs_root);
if (IS_ERR(rdev->debugfs) || !rdev->debugfs) {
rdev_warn(rdev, "Failed to create debugfs directory\n");
rdev->debugfs = NULL;
- return;
+ goto error;
}
debugfs_create_u32("use_count", 0444, rdev->debugfs,
&rdev->use_count);
debugfs_create_u32("open_count", 0444, rdev->debugfs,
&rdev->open_count);
-#endif
+ debugfs_create_file("consumers", 0444, rdev->debugfs, rdev,
+ ®_consumers_fops);
+
+ reg = regulator_get(NULL, rdev->desc->name);
+ if (IS_ERR(reg) || reg == NULL) {
+ pr_err("Error-Bad Function Input\n");
+ goto error;
+ }
+
+ reg_ops = rdev->desc->ops;
+ mode = S_IRUGO | S_IWUSR;
+ /* Enabled File */
+ if (mode)
+ err_ptr = debugfs_create_file("enable", mode, rdev->debugfs,
+ reg, ®_enable_fops);
+ if (IS_ERR(err_ptr)) {
+ pr_err("Error-Could not create enable file\n");
+ debugfs_remove_recursive(rdev->debugfs);
+ goto error;
+ }
+
+ mode = 0;
+ /* Force-Disable File */
+ if (reg_ops->is_enabled)
+ mode |= S_IRUGO;
+ if (reg_ops->enable || reg_ops->disable)
+ mode |= S_IWUSR;
+ if (mode)
+ err_ptr = debugfs_create_file("force_disable", mode,
+ rdev->debugfs, reg, ®_fdisable_fops);
+ if (IS_ERR(err_ptr)) {
+ pr_err("Error-Could not create force_disable file\n");
+ debugfs_remove_recursive(rdev->debugfs);
+ goto error;
+ }
+
+ mode = 0;
+ /* Voltage File */
+ if (reg_ops->get_voltage)
+ mode |= S_IRUGO;
+ if (reg_ops->set_voltage)
+ mode |= S_IWUSR;
+ if (mode)
+ err_ptr = debugfs_create_file("voltage", mode, rdev->debugfs,
+ reg, ®_volt_fops);
+ if (IS_ERR(err_ptr)) {
+ pr_err("Error-Could not create voltage file\n");
+ debugfs_remove_recursive(rdev->debugfs);
+ goto error;
+ }
+
+ mode = 0;
+ /* Mode File */
+ if (reg_ops->get_mode)
+ mode |= S_IRUGO;
+ if (reg_ops->set_mode)
+ mode |= S_IWUSR;
+ if (mode)
+ err_ptr = debugfs_create_file("mode", mode, rdev->debugfs,
+ reg, ®_mode_fops);
+ if (IS_ERR(err_ptr)) {
+ pr_err("Error-Could not create mode file\n");
+ debugfs_remove_recursive(rdev->debugfs);
+ goto error;
+ }
+
+ mode = 0;
+ /* Optimum Mode File */
+ if (reg_ops->get_mode)
+ mode |= S_IRUGO;
+ if (reg_ops->set_mode)
+ mode |= S_IWUSR;
+ if (mode)
+ err_ptr = debugfs_create_file("optimum_mode", mode,
+ rdev->debugfs, reg, ®_optimum_mode_fops);
+ if (IS_ERR(err_ptr)) {
+ pr_err("Error-Could not create optimum_mode file\n");
+ debugfs_remove_recursive(rdev->debugfs);
+ goto error;
+ }
+
+error:
+ return;
}
+#else
+static inline void rdev_init_debugfs(struct regulator_dev *rdev)
+{
+ return;
+}
+#endif
/**
* regulator_register - register regulator
@@ -2663,9 +3130,9 @@
list_add(&rdev->list, ®ulator_list);
- rdev_init_debugfs(rdev);
out:
mutex_unlock(®ulator_list_mutex);
+ rdev_init_debugfs(rdev);
return rdev;
unset_supplies:
@@ -2819,6 +3286,22 @@
EXPORT_SYMBOL_GPL(regulator_use_dummy_regulator);
/**
+ * regulator_suppress_info_printing - disable printing of info messages
+ *
+ * The regulator framework calls print_constraints() when a regulator is
+ * registered. It also prints a disable message for each unused regulator in
+ * regulator_init_complete().
+ *
+ * Calling this function ensures that such messages do not end up in the
+ * log.
+ */
+void regulator_suppress_info_printing(void)
+{
+ suppress_info_printing = 1;
+}
+EXPORT_SYMBOL_GPL(regulator_suppress_info_printing);
+
+/**
* rdev_get_drvdata - get rdev regulator driver data
* @rdev: regulator
*
@@ -2936,7 +3419,8 @@
if (has_full_constraints) {
/* We log since this may kill the system if it
* goes wrong. */
- rdev_info(rdev, "disabling\n");
+ if (!suppress_info_printing)
+ rdev_info(rdev, "disabling\n");
ret = ops->disable(rdev);
if (ret != 0) {
rdev_err(rdev, "couldn't disable: %d\n", ret);
@@ -2947,7 +3431,9 @@
* so warn even if we aren't going to do
* anything here.
*/
- rdev_warn(rdev, "incomplete constraints, leaving on\n");
+ if (!suppress_info_printing)
+ rdev_warn(rdev, "incomplete constraints, "
+ "leaving on\n");
}
unlock:
diff --git a/drivers/regulator/gpio-regulator.c b/drivers/regulator/gpio-regulator.c
new file mode 100644
index 0000000..b91e32f
--- /dev/null
+++ b/drivers/regulator/gpio-regulator.c
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/gpio-regulator.h>
+
+struct gpio_vreg {
+ struct regulator_desc desc;
+ struct regulator_dev *rdev;
+ char *gpio_label;
+ char *name;
+ unsigned gpio;
+ int active_low;
+ bool gpio_requested;
+};
+
+static int gpio_vreg_request_gpio(struct gpio_vreg *vreg)
+{
+ int rc = 0;
+
+ /* Request GPIO now if it hasn't been requested before. */
+ if (!vreg->gpio_requested) {
+ rc = gpio_request(vreg->gpio, vreg->gpio_label);
+ if (rc < 0)
+ pr_err("failed to request gpio %u (%s), rc=%d\n",
+ vreg->gpio, vreg->gpio_label, rc);
+ else
+ vreg->gpio_requested = true;
+
+ rc = gpio_sysfs_set_active_low(vreg->gpio, vreg->active_low);
+ if (rc < 0)
+ pr_err("active_low=%d failed for gpio %u, rc=%d\n",
+ vreg->active_low, vreg->gpio, rc);
+ }
+
+ return rc;
+}
+
+static int gpio_vreg_is_enabled(struct regulator_dev *rdev)
+{
+ struct gpio_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = gpio_vreg_request_gpio(vreg);
+ if (rc < 0)
+ return rc;
+
+ return (gpio_get_value_cansleep(vreg->gpio) ? 1 : 0) ^ vreg->active_low;
+}
+
+static int gpio_vreg_enable(struct regulator_dev *rdev)
+{
+ struct gpio_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = gpio_vreg_request_gpio(vreg);
+ if (rc < 0)
+ return rc;
+
+ return gpio_direction_output(vreg->gpio, !vreg->active_low);
+}
+
+static int gpio_vreg_disable(struct regulator_dev *rdev)
+{
+ struct gpio_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = gpio_vreg_request_gpio(vreg);
+ if (rc < 0)
+ return rc;
+
+ return gpio_direction_output(vreg->gpio, vreg->active_low);
+}
+
+static struct regulator_ops gpio_vreg_ops = {
+ .enable = gpio_vreg_enable,
+ .disable = gpio_vreg_disable,
+ .is_enabled = gpio_vreg_is_enabled,
+};
+
+static int __devinit gpio_vreg_probe(struct platform_device *pdev)
+{
+ const struct gpio_regulator_platform_data *pdata;
+ struct gpio_vreg *vreg;
+ int rc = 0;
+
+ pdata = pdev->dev.platform_data;
+
+ if (!pdata) {
+ pr_err("platform data required.\n");
+ return -EINVAL;
+ }
+
+ if (!pdata->gpio_label) {
+ pr_err("gpio_label required.\n");
+ return -EINVAL;
+ }
+
+ if (!pdata->regulator_name) {
+ pr_err("regulator_name required.\n");
+ return -EINVAL;
+ }
+
+ vreg = kzalloc(sizeof(struct gpio_vreg), GFP_KERNEL);
+ if (!vreg) {
+ pr_err("kzalloc failed.\n");
+ return -ENOMEM;
+ }
+
+ vreg->name = kstrdup(pdata->regulator_name, GFP_KERNEL);
+ if (!vreg->name) {
+ pr_err("kzalloc failed.\n");
+ rc = -ENOMEM;
+ goto free_vreg;
+ }
+
+ vreg->gpio_label = kstrdup(pdata->gpio_label, GFP_KERNEL);
+ if (!vreg->gpio_label) {
+ pr_err("kzalloc failed.\n");
+ rc = -ENOMEM;
+ goto free_name;
+ }
+
+ vreg->gpio = pdata->gpio;
+ vreg->active_low = (pdata->active_low ? 1 : 0);
+ vreg->gpio_requested = false;
+
+ vreg->desc.name = vreg->name;
+ vreg->desc.id = pdev->id;
+ vreg->desc.ops = &gpio_vreg_ops;
+ vreg->desc.type = REGULATOR_VOLTAGE;
+ vreg->desc.owner = THIS_MODULE;
+
+ vreg->rdev = regulator_register(&vreg->desc, &pdev->dev,
+ &pdata->init_data, vreg);
+ if (IS_ERR(vreg->rdev)) {
+ rc = PTR_ERR(vreg->rdev);
+ pr_err("%s: regulator_register failed, rc=%d.\n", vreg->name,
+ rc);
+ goto free_gpio_label;
+ }
+
+ platform_set_drvdata(pdev, vreg);
+
+ pr_info("id=%d, name=%s, gpio=%u, gpio_label=%s\n", pdev->id,
+ vreg->name, vreg->gpio, vreg->gpio_label);
+
+ return rc;
+
+free_gpio_label:
+ kfree(vreg->gpio_label);
+free_name:
+ kfree(vreg->name);
+free_vreg:
+ kfree(vreg);
+
+ return rc;
+}
+
+static int __devexit gpio_vreg_remove(struct platform_device *pdev)
+{
+ struct gpio_vreg *vreg = platform_get_drvdata(pdev);
+
+ if (vreg->gpio_requested)
+ gpio_free(vreg->gpio);
+
+ regulator_unregister(vreg->rdev);
+ kfree(vreg->name);
+ kfree(vreg->gpio_label);
+ kfree(vreg);
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static struct platform_driver gpio_vreg_driver = {
+ .probe = gpio_vreg_probe,
+ .remove = __devexit_p(gpio_vreg_remove),
+ .driver = {
+ .name = GPIO_REGULATOR_DEV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init gpio_vreg_init(void)
+{
+ return platform_driver_register(&gpio_vreg_driver);
+}
+
+static void __exit gpio_vreg_exit(void)
+{
+ platform_driver_unregister(&gpio_vreg_driver);
+}
+
+postcore_initcall(gpio_vreg_init);
+module_exit(gpio_vreg_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("GPIO regulator driver");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:" GPIO_REGULATOR_DEV_NAME);
diff --git a/drivers/regulator/pm8058-xo.c b/drivers/regulator/pm8058-xo.c
new file mode 100644
index 0000000..ac65395
--- /dev/null
+++ b/drivers/regulator/pm8058-xo.c
@@ -0,0 +1,215 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/bitops.h>
+#include <linux/mfd/pmic8058.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/pm8058-xo.h>
+
+/* XO buffer masks and values */
+
+#define XO_PULLDOWN_MASK 0x08
+#define XO_PULLDOWN_ENABLE 0x08
+#define XO_PULLDOWN_DISABLE 0x00
+
+#define XO_BUFFER_MASK 0x04
+#define XO_BUFFER_ENABLE 0x04
+#define XO_BUFFER_DISABLE 0x00
+
+#define XO_MODE_MASK 0x01
+#define XO_MODE_MANUAL 0x00
+
+#define XO_ENABLE_MASK (XO_MODE_MASK | XO_BUFFER_MASK)
+#define XO_ENABLE (XO_MODE_MANUAL | XO_BUFFER_ENABLE)
+#define XO_DISABLE (XO_MODE_MANUAL | XO_BUFFER_DISABLE)
+
+struct pm8058_xo_buffer {
+ struct pm8058_xo_pdata *pdata;
+ struct regulator_dev *rdev;
+ u16 ctrl_addr;
+ u8 ctrl_reg;
+};
+
+#define XO_BUFFER(_id, _ctrl_addr) \
+ [PM8058_XO_ID_##_id] = { \
+ .ctrl_addr = _ctrl_addr, \
+ }
+
+static struct pm8058_xo_buffer pm8058_xo_buffer[] = {
+ XO_BUFFER(A0, 0x185),
+ XO_BUFFER(A1, 0x186),
+};
+
+static int pm8058_xo_buffer_write(struct pm8058_chip *chip,
+ u16 addr, u8 val, u8 mask, u8 *reg_save)
+{
+ u8 reg;
+ int rc = 0;
+
+ reg = (*reg_save & ~mask) | (val & mask);
+ if (reg != *reg_save)
+ rc = pm8058_write(chip, addr, ®, 1);
+
+ if (rc)
+ pr_err("FAIL: pm8058_write: rc=%d\n", rc);
+ else
+ *reg_save = reg;
+ return rc;
+}
+
+static int pm8058_xo_buffer_enable(struct regulator_dev *dev)
+{
+ struct pm8058_xo_buffer *xo = rdev_get_drvdata(dev);
+ struct pm8058_chip *chip = dev_get_drvdata(dev->dev.parent);
+ int rc;
+
+ rc = pm8058_xo_buffer_write(chip, xo->ctrl_addr, XO_ENABLE,
+ XO_ENABLE_MASK, &xo->ctrl_reg);
+ if (rc)
+ pr_err("FAIL: pm8058_xo_buffer_write: rc=%d\n", rc);
+
+ return rc;
+}
+
+static int pm8058_xo_buffer_is_enabled(struct regulator_dev *dev)
+{
+ struct pm8058_xo_buffer *xo = rdev_get_drvdata(dev);
+
+ if (xo->ctrl_reg & XO_BUFFER_ENABLE)
+ return 1;
+ else
+ return 0;
+}
+
+static int pm8058_xo_buffer_disable(struct regulator_dev *dev)
+{
+ struct pm8058_xo_buffer *xo = rdev_get_drvdata(dev);
+ struct pm8058_chip *chip = dev_get_drvdata(dev->dev.parent);
+ int rc;
+
+ rc = pm8058_xo_buffer_write(chip, xo->ctrl_addr, XO_DISABLE,
+ XO_ENABLE_MASK, &xo->ctrl_reg);
+ if (rc)
+ pr_err("FAIL: pm8058_xo_buffer_write: rc=%d\n", rc);
+
+ return rc;
+}
+
+static struct regulator_ops pm8058_xo_ops = {
+ .enable = pm8058_xo_buffer_enable,
+ .disable = pm8058_xo_buffer_disable,
+ .is_enabled = pm8058_xo_buffer_is_enabled,
+};
+
+#define VREG_DESCRIP(_id, _name, _ops) \
+ [_id] = { \
+ .id = _id, \
+ .name = _name, \
+ .ops = _ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .owner = THIS_MODULE, \
+ }
+
+static struct regulator_desc pm8058_xo_buffer_desc[] = {
+ VREG_DESCRIP(PM8058_XO_ID_A0, "8058_xo_a0", &pm8058_xo_ops),
+ VREG_DESCRIP(PM8058_XO_ID_A1, "8058_xo_a1", &pm8058_xo_ops),
+};
+
+static int pm8058_init_xo_buffer(struct pm8058_chip *chip,
+ struct pm8058_xo_buffer *xo)
+{
+ int rc;
+
+ /* Save the current control register state */
+ rc = pm8058_read(chip, xo->ctrl_addr, &xo->ctrl_reg, 1);
+
+ if (rc)
+ pr_err("FAIL: pm8058_read: rc=%d\n", rc);
+ return rc;
+}
+
+static int __devinit pm8058_xo_buffer_probe(struct platform_device *pdev)
+{
+ struct regulator_desc *rdesc;
+ struct pm8058_chip *chip;
+ struct pm8058_xo_buffer *xo;
+ int rc = 0;
+
+ if (pdev == NULL)
+ return -EINVAL;
+
+ if (pdev->id >= 0 && pdev->id < PM8058_XO_ID_MAX) {
+ chip = platform_get_drvdata(pdev);
+ rdesc = &pm8058_xo_buffer_desc[pdev->id];
+ xo = &pm8058_xo_buffer[pdev->id];
+ xo->pdata = pdev->dev.platform_data;
+
+ rc = pm8058_init_xo_buffer(chip, xo);
+ if (rc)
+ goto bail;
+
+ xo->rdev = regulator_register(rdesc, &pdev->dev,
+ &xo->pdata->init_data, xo);
+ if (IS_ERR(xo->rdev)) {
+ rc = PTR_ERR(xo->rdev);
+ pr_err("FAIL: regulator_register(%s): rc=%d\n",
+ pm8058_xo_buffer_desc[pdev->id].name, rc);
+ }
+ } else {
+ rc = -ENODEV;
+ }
+
+bail:
+ if (rc)
+ pr_err("Error: xo-id=%d, rc=%d\n", pdev->id, rc);
+
+ return rc;
+}
+
+static int __devexit pm8058_xo_buffer_remove(struct platform_device *pdev)
+{
+ regulator_unregister(pm8058_xo_buffer[pdev->id].rdev);
+ return 0;
+}
+
+static struct platform_driver pm8058_xo_buffer_driver = {
+ .probe = pm8058_xo_buffer_probe,
+ .remove = __devexit_p(pm8058_xo_buffer_remove),
+ .driver = {
+ .name = PM8058_XO_BUFFER_DEV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pm8058_xo_buffer_init(void)
+{
+ return platform_driver_register(&pm8058_xo_buffer_driver);
+}
+
+static void __exit pm8058_xo_buffer_exit(void)
+{
+ platform_driver_unregister(&pm8058_xo_buffer_driver);
+}
+
+subsys_initcall(pm8058_xo_buffer_init);
+module_exit(pm8058_xo_buffer_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PMIC8058 XO buffer driver");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:" PM8058_XO_BUFFER_DEV_NAME);
diff --git a/drivers/regulator/pm8921-regulator.c b/drivers/regulator/pm8921-regulator.c
new file mode 100644
index 0000000..a2246eb
--- /dev/null
+++ b/drivers/regulator/pm8921-regulator.c
@@ -0,0 +1,3274 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/mutex.h>
+#include <linux/init.h>
+#include <linux/bitops.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/pm8921-regulator.h>
+#include <linux/mfd/pm8xxx/core.h>
+
+/* Debug Flag Definitions */
+enum {
+ PM8921_VREG_DEBUG_REQUEST = BIT(0),
+ PM8921_VREG_DEBUG_DUPLICATE = BIT(1),
+ PM8921_VREG_DEBUG_INIT = BIT(2),
+ PM8921_VREG_DEBUG_WRITES = BIT(3), /* SSBI writes */
+};
+
+static int pm8921_vreg_debug_mask;
+module_param_named(
+ debug_mask, pm8921_vreg_debug_mask, int, S_IRUSR | S_IWUSR
+);
+
+#define REGULATOR_TYPE_PLDO 0
+#define REGULATOR_TYPE_NLDO 1
+#define REGULATOR_TYPE_NLDO1200 2
+#define REGULATOR_TYPE_SMPS 3
+#define REGULATOR_TYPE_FTSMPS 4
+#define REGULATOR_TYPE_VS 5
+#define REGULATOR_TYPE_VS300 6
+#define REGULATOR_TYPE_NCP 7
+
+/* Common Masks */
+#define REGULATOR_ENABLE_MASK 0x80
+#define REGULATOR_ENABLE 0x80
+#define REGULATOR_DISABLE 0x00
+
+#define REGULATOR_BANK_MASK 0xF0
+#define REGULATOR_BANK_SEL(n) ((n) << 4)
+#define REGULATOR_BANK_WRITE 0x80
+
+#define LDO_TEST_BANKS 7
+#define NLDO1200_TEST_BANKS 5
+#define SMPS_TEST_BANKS 8
+#define REGULATOR_TEST_BANKS_MAX SMPS_TEST_BANKS
+
+/*
+ * This voltage in uV is returned by get_voltage functions when there is no way
+ * to determine the current voltage level. It is needed because the regulator
+ * framework treats a 0 uV voltage as an error.
+ */
+#define VOLTAGE_UNKNOWN 1
+
+/* LDO masks and values */
+
+/* CTRL register */
+#define LDO_ENABLE_MASK 0x80
+#define LDO_DISABLE 0x00
+#define LDO_ENABLE 0x80
+#define LDO_PULL_DOWN_ENABLE_MASK 0x40
+#define LDO_PULL_DOWN_ENABLE 0x40
+
+#define LDO_CTRL_PM_MASK 0x20
+#define LDO_CTRL_PM_HPM 0x00
+#define LDO_CTRL_PM_LPM 0x20
+
+#define LDO_CTRL_VPROG_MASK 0x1F
+
+/* TEST register bank 0 */
+#define LDO_TEST_LPM_MASK 0x40
+#define LDO_TEST_LPM_SEL_CTRL 0x00
+#define LDO_TEST_LPM_SEL_TCXO 0x40
+
+/* TEST register bank 2 */
+#define LDO_TEST_VPROG_UPDATE_MASK 0x08
+#define LDO_TEST_RANGE_SEL_MASK 0x04
+#define LDO_TEST_FINE_STEP_MASK 0x02
+#define LDO_TEST_FINE_STEP_SHIFT 1
+
+/* TEST register bank 4 */
+#define LDO_TEST_RANGE_EXT_MASK 0x01
+
+/* TEST register bank 5 */
+#define LDO_TEST_PIN_CTRL_MASK 0x0F
+#define LDO_TEST_PIN_CTRL_EN3 0x08
+#define LDO_TEST_PIN_CTRL_EN2 0x04
+#define LDO_TEST_PIN_CTRL_EN1 0x02
+#define LDO_TEST_PIN_CTRL_EN0 0x01
+
+/* TEST register bank 6 */
+#define LDO_TEST_PIN_CTRL_LPM_MASK 0x0F
+
+
+/*
+ * If a given voltage could be output by two ranges, then the preferred one must
+ * be determined by the range limits. Specified voltage ranges should must
+ * not overlap.
+ *
+ * Allowable voltage ranges:
+ */
+#define PLDO_LOW_UV_MIN 750000
+#define PLDO_LOW_UV_MAX 1487500
+#define PLDO_LOW_UV_FINE_STEP 12500
+
+#define PLDO_NORM_UV_MIN 1500000
+#define PLDO_NORM_UV_MAX 3075000
+#define PLDO_NORM_UV_FINE_STEP 25000
+
+#define PLDO_HIGH_UV_MIN 1750000
+#define PLDO_HIGH_UV_SET_POINT_MIN 3100000
+#define PLDO_HIGH_UV_MAX 4900000
+#define PLDO_HIGH_UV_FINE_STEP 50000
+
+#define PLDO_LOW_SET_POINTS ((PLDO_LOW_UV_MAX - PLDO_LOW_UV_MIN) \
+ / PLDO_LOW_UV_FINE_STEP + 1)
+#define PLDO_NORM_SET_POINTS ((PLDO_NORM_UV_MAX - PLDO_NORM_UV_MIN) \
+ / PLDO_NORM_UV_FINE_STEP + 1)
+#define PLDO_HIGH_SET_POINTS ((PLDO_HIGH_UV_MAX \
+ - PLDO_HIGH_UV_SET_POINT_MIN) \
+ / PLDO_HIGH_UV_FINE_STEP + 1)
+#define PLDO_SET_POINTS (PLDO_LOW_SET_POINTS \
+ + PLDO_NORM_SET_POINTS \
+ + PLDO_HIGH_SET_POINTS)
+
+#define NLDO_UV_MIN 750000
+#define NLDO_UV_MAX 1537500
+#define NLDO_UV_FINE_STEP 12500
+
+#define NLDO_SET_POINTS ((NLDO_UV_MAX - NLDO_UV_MIN) \
+ / NLDO_UV_FINE_STEP + 1)
+
+/* NLDO1200 masks and values */
+
+/* CTRL register */
+#define NLDO1200_ENABLE_MASK 0x80
+#define NLDO1200_DISABLE 0x00
+#define NLDO1200_ENABLE 0x80
+
+/* Legacy mode */
+#define NLDO1200_LEGACY_PM_MASK 0x20
+#define NLDO1200_LEGACY_PM_HPM 0x00
+#define NLDO1200_LEGACY_PM_LPM 0x20
+
+/* Advanced mode */
+#define NLDO1200_CTRL_RANGE_MASK 0x40
+#define NLDO1200_CTRL_RANGE_HIGH 0x00
+#define NLDO1200_CTRL_RANGE_LOW 0x40
+#define NLDO1200_CTRL_VPROG_MASK 0x3F
+
+#define NLDO1200_LOW_UV_MIN 375000
+#define NLDO1200_LOW_UV_MAX 743750
+#define NLDO1200_LOW_UV_STEP 6250
+
+#define NLDO1200_HIGH_UV_MIN 750000
+#define NLDO1200_HIGH_UV_MAX 1537500
+#define NLDO1200_HIGH_UV_STEP 12500
+
+#define NLDO1200_LOW_SET_POINTS ((NLDO1200_LOW_UV_MAX \
+ - NLDO1200_LOW_UV_MIN) \
+ / NLDO1200_LOW_UV_STEP + 1)
+#define NLDO1200_HIGH_SET_POINTS ((NLDO1200_HIGH_UV_MAX \
+ - NLDO1200_HIGH_UV_MIN) \
+ / NLDO1200_HIGH_UV_STEP + 1)
+#define NLDO1200_SET_POINTS (NLDO1200_LOW_SET_POINTS \
+ + NLDO1200_HIGH_SET_POINTS)
+
+/* TEST register bank 0 */
+#define NLDO1200_TEST_LPM_MASK 0x04
+#define NLDO1200_TEST_LPM_SEL_CTRL 0x00
+#define NLDO1200_TEST_LPM_SEL_TCXO 0x04
+
+/* TEST register bank 1 */
+#define NLDO1200_PULL_DOWN_ENABLE_MASK 0x02
+#define NLDO1200_PULL_DOWN_ENABLE 0x02
+
+/* TEST register bank 2 */
+#define NLDO1200_ADVANCED_MODE_MASK 0x08
+#define NLDO1200_ADVANCED_MODE 0x00
+#define NLDO1200_LEGACY_MODE 0x08
+
+/* Advanced mode power mode control */
+#define NLDO1200_ADVANCED_PM_MASK 0x02
+#define NLDO1200_ADVANCED_PM_HPM 0x00
+#define NLDO1200_ADVANCED_PM_LPM 0x02
+
+#define NLDO1200_IN_ADVANCED_MODE(vreg) \
+ ((vreg->test_reg[2] & NLDO1200_ADVANCED_MODE_MASK) \
+ == NLDO1200_ADVANCED_MODE)
+
+/* SMPS masks and values */
+
+/* CTRL register */
+
+/* Legacy mode */
+#define SMPS_LEGACY_ENABLE_MASK 0x80
+#define SMPS_LEGACY_DISABLE 0x00
+#define SMPS_LEGACY_ENABLE 0x80
+#define SMPS_LEGACY_PULL_DOWN_ENABLE 0x40
+#define SMPS_LEGACY_VREF_SEL_MASK 0x20
+#define SMPS_LEGACY_VPROG_MASK 0x1F
+
+/* Advanced mode */
+#define SMPS_ADVANCED_BAND_MASK 0xC0
+#define SMPS_ADVANCED_BAND_OFF 0x00
+#define SMPS_ADVANCED_BAND_1 0x40
+#define SMPS_ADVANCED_BAND_2 0x80
+#define SMPS_ADVANCED_BAND_3 0xC0
+#define SMPS_ADVANCED_VPROG_MASK 0x3F
+
+/* Legacy mode voltage ranges */
+#define SMPS_MODE3_UV_MIN 375000
+#define SMPS_MODE3_UV_MAX 725000
+#define SMPS_MODE3_UV_STEP 25000
+
+#define SMPS_MODE2_UV_MIN 750000
+#define SMPS_MODE2_UV_MAX 1475000
+#define SMPS_MODE2_UV_STEP 25000
+
+#define SMPS_MODE1_UV_MIN 1500000
+#define SMPS_MODE1_UV_MAX 3050000
+#define SMPS_MODE1_UV_STEP 50000
+
+#define SMPS_MODE3_SET_POINTS ((SMPS_MODE3_UV_MAX \
+ - SMPS_MODE3_UV_MIN) \
+ / SMPS_MODE3_UV_STEP + 1)
+#define SMPS_MODE2_SET_POINTS ((SMPS_MODE2_UV_MAX \
+ - SMPS_MODE2_UV_MIN) \
+ / SMPS_MODE2_UV_STEP + 1)
+#define SMPS_MODE1_SET_POINTS ((SMPS_MODE1_UV_MAX \
+ - SMPS_MODE1_UV_MIN) \
+ / SMPS_MODE1_UV_STEP + 1)
+#define SMPS_LEGACY_SET_POINTS (SMPS_MODE3_SET_POINTS \
+ + SMPS_MODE2_SET_POINTS \
+ + SMPS_MODE1_SET_POINTS)
+
+/* Advanced mode voltage ranges */
+#define SMPS_BAND1_UV_MIN 375000
+#define SMPS_BAND1_UV_MAX 737500
+#define SMPS_BAND1_UV_STEP 12500
+
+#define SMPS_BAND2_UV_MIN 750000
+#define SMPS_BAND2_UV_MAX 1487500
+#define SMPS_BAND2_UV_STEP 12500
+
+#define SMPS_BAND3_UV_MIN 1500000
+#define SMPS_BAND3_UV_MAX 3075000
+#define SMPS_BAND3_UV_STEP 25000
+
+#define SMPS_BAND1_SET_POINTS ((SMPS_BAND1_UV_MAX \
+ - SMPS_BAND1_UV_MIN) \
+ / SMPS_BAND1_UV_STEP + 1)
+#define SMPS_BAND2_SET_POINTS ((SMPS_BAND2_UV_MAX \
+ - SMPS_BAND2_UV_MIN) \
+ / SMPS_BAND2_UV_STEP + 1)
+#define SMPS_BAND3_SET_POINTS ((SMPS_BAND3_UV_MAX \
+ - SMPS_BAND3_UV_MIN) \
+ / SMPS_BAND3_UV_STEP + 1)
+#define SMPS_ADVANCED_SET_POINTS (SMPS_BAND1_SET_POINTS \
+ + SMPS_BAND2_SET_POINTS \
+ + SMPS_BAND3_SET_POINTS)
+
+/* Test2 register bank 1 */
+#define SMPS_LEGACY_VLOW_SEL_MASK 0x01
+
+/* Test2 register bank 6 */
+#define SMPS_ADVANCED_PULL_DOWN_ENABLE 0x08
+
+/* Test2 register bank 7 */
+#define SMPS_ADVANCED_MODE_MASK 0x02
+#define SMPS_ADVANCED_MODE 0x02
+#define SMPS_LEGACY_MODE 0x00
+
+#define SMPS_IN_ADVANCED_MODE(vreg) \
+ ((vreg->test_reg[7] & SMPS_ADVANCED_MODE_MASK) == SMPS_ADVANCED_MODE)
+
+/* BUCK_SLEEP_CNTRL register */
+#define SMPS_PIN_CTRL_MASK 0xF0
+#define SMPS_PIN_CTRL_EN3 0x80
+#define SMPS_PIN_CTRL_EN2 0x40
+#define SMPS_PIN_CTRL_EN1 0x20
+#define SMPS_PIN_CTRL_EN0 0x10
+
+#define SMPS_PIN_CTRL_LPM_MASK 0x0F
+#define SMPS_PIN_CTRL_LPM_EN3 0x08
+#define SMPS_PIN_CTRL_LPM_EN2 0x04
+#define SMPS_PIN_CTRL_LPM_EN1 0x02
+#define SMPS_PIN_CTRL_LPM_EN0 0x01
+
+/* BUCK_CLOCK_CNTRL register */
+#define SMPS_CLK_DIVIDE2 0x40
+
+#define SMPS_CLK_CTRL_MASK 0x30
+#define SMPS_CLK_CTRL_FOLLOW_TCXO 0x00
+#define SMPS_CLK_CTRL_PWM 0x10
+#define SMPS_CLK_CTRL_PFM 0x20
+
+/* FTSMPS masks and values */
+
+/* CTRL register */
+#define FTSMPS_VCTRL_BAND_MASK 0xC0
+#define FTSMPS_VCTRL_BAND_OFF 0x00
+#define FTSMPS_VCTRL_BAND_1 0x40
+#define FTSMPS_VCTRL_BAND_2 0x80
+#define FTSMPS_VCTRL_BAND_3 0xC0
+#define FTSMPS_VCTRL_VPROG_MASK 0x3F
+
+#define FTSMPS_BAND1_UV_MIN 350000
+#define FTSMPS_BAND1_UV_MAX 650000
+/* 3 LSB's of program voltage must be 0 in band 1. */
+/* Logical step size */
+#define FTSMPS_BAND1_UV_LOG_STEP 50000
+/* Physical step size */
+#define FTSMPS_BAND1_UV_PHYS_STEP 6250
+
+#define FTSMPS_BAND2_UV_MIN 700000
+#define FTSMPS_BAND2_UV_MAX 1400000
+#define FTSMPS_BAND2_UV_STEP 12500
+
+#define FTSMPS_BAND3_UV_MIN 1400000
+#define FTSMPS_BAND3_UV_SET_POINT_MIN 1500000
+#define FTSMPS_BAND3_UV_MAX 3300000
+#define FTSMPS_BAND3_UV_STEP 50000
+
+#define FTSMPS_BAND1_SET_POINTS ((FTSMPS_BAND1_UV_MAX \
+ - FTSMPS_BAND1_UV_MIN) \
+ / FTSMPS_BAND1_UV_LOG_STEP + 1)
+#define FTSMPS_BAND2_SET_POINTS ((FTSMPS_BAND2_UV_MAX \
+ - FTSMPS_BAND2_UV_MIN) \
+ / FTSMPS_BAND2_UV_STEP + 1)
+#define FTSMPS_BAND3_SET_POINTS ((FTSMPS_BAND3_UV_MAX \
+ - FTSMPS_BAND3_UV_SET_POINT_MIN) \
+ / FTSMPS_BAND3_UV_STEP + 1)
+#define FTSMPS_SET_POINTS (FTSMPS_BAND1_SET_POINTS \
+ + FTSMPS_BAND2_SET_POINTS \
+ + FTSMPS_BAND3_SET_POINTS)
+
+/* FTS_CNFG1 register bank 0 */
+#define FTSMPS_CNFG1_PM_MASK 0x0C
+#define FTSMPS_CNFG1_PM_PWM 0x00
+#define FTSMPS_CNFG1_PM_PFM 0x08
+
+/* PWR_CNFG register */
+#define FTSMPS_PULL_DOWN_ENABLE_MASK 0x40
+#define FTSMPS_PULL_DOWN_ENABLE 0x40
+
+/* VS masks and values */
+
+/* CTRL register */
+#define VS_ENABLE_MASK 0x80
+#define VS_DISABLE 0x00
+#define VS_ENABLE 0x80
+#define VS_PULL_DOWN_ENABLE_MASK 0x40
+#define VS_PULL_DOWN_ENABLE 0x40
+
+#define VS_PIN_CTRL_MASK 0x0F
+#define VS_PIN_CTRL_EN0 0x08
+#define VS_PIN_CTRL_EN1 0x04
+#define VS_PIN_CTRL_EN2 0x02
+#define VS_PIN_CTRL_EN3 0x01
+
+/* VS300 masks and values */
+
+/* CTRL register */
+#define VS300_CTRL_ENABLE_MASK 0xC0
+#define VS300_CTRL_DISABLE 0x00
+#define VS300_CTRL_ENABLE 0x40
+
+#define VS300_PULL_DOWN_ENABLE_MASK 0x20
+#define VS300_PULL_DOWN_ENABLE 0x20
+
+/* NCP masks and values */
+
+/* CTRL register */
+#define NCP_ENABLE_MASK 0x80
+#define NCP_DISABLE 0x00
+#define NCP_ENABLE 0x80
+#define NCP_VPROG_MASK 0x1F
+
+#define NCP_UV_MIN 1500000
+#define NCP_UV_MAX 3050000
+#define NCP_UV_STEP 50000
+
+#define NCP_SET_POINTS ((NCP_UV_MAX - NCP_UV_MIN) \
+ / NCP_UV_STEP + 1)
+
+#define IS_REAL_REGULATOR(id) ((id) >= 0 && \
+ (id) < PM8921_VREG_ID_L1_PC)
+
+struct pm8921_vreg {
+ /* Configuration data */
+ struct regulator_dev *rdev;
+ struct regulator_dev *rdev_pc;
+ struct device *dev;
+ struct device *dev_pc;
+ const char *name;
+ struct pm8921_regulator_platform_data pdata;
+ const int hpm_min_load;
+ const u16 ctrl_addr;
+ const u16 test_addr;
+ const u16 clk_ctrl_addr;
+ const u16 sleep_ctrl_addr;
+ const u16 pfm_ctrl_addr;
+ const u16 pwr_cnfg_addr;
+ const u8 type;
+ /* State data */
+ struct mutex pc_lock;
+ int save_uV;
+ int mode;
+ u32 write_count;
+ u32 prev_write_count;
+ bool is_enabled;
+ bool is_enabled_pc;
+ u8 test_reg[REGULATOR_TEST_BANKS_MAX];
+ u8 ctrl_reg;
+ u8 clk_ctrl_reg;
+ u8 sleep_ctrl_reg;
+ u8 pfm_ctrl_reg;
+ u8 pwr_cnfg_reg;
+};
+
+#define vreg_err(vreg, fmt, ...) \
+ pr_err("%s: " fmt, vreg->name, ##__VA_ARGS__)
+
+#define PLDO(_id, _ctrl_addr, _test_addr, _hpm_min_load) \
+ [PM8921_VREG_ID_##_id] = { \
+ .type = REGULATOR_TYPE_PLDO, \
+ .ctrl_addr = _ctrl_addr, \
+ .test_addr = _test_addr, \
+ .hpm_min_load = PM8921_VREG_##_hpm_min_load##_HPM_MIN_LOAD, \
+ }
+
+#define NLDO(_id, _ctrl_addr, _test_addr, _hpm_min_load) \
+ [PM8921_VREG_ID_##_id] = { \
+ .type = REGULATOR_TYPE_NLDO, \
+ .ctrl_addr = _ctrl_addr, \
+ .test_addr = _test_addr, \
+ .hpm_min_load = PM8921_VREG_##_hpm_min_load##_HPM_MIN_LOAD, \
+ }
+
+#define NLDO1200(_id, _ctrl_addr, _test_addr, _hpm_min_load) \
+ [PM8921_VREG_ID_##_id] = { \
+ .type = REGULATOR_TYPE_NLDO1200, \
+ .ctrl_addr = _ctrl_addr, \
+ .test_addr = _test_addr, \
+ .hpm_min_load = PM8921_VREG_##_hpm_min_load##_HPM_MIN_LOAD, \
+ }
+
+#define SMPS(_id, _ctrl_addr, _test_addr, _clk_ctrl_addr, _sleep_ctrl_addr, \
+ _hpm_min_load) \
+ [PM8921_VREG_ID_##_id] = { \
+ .type = REGULATOR_TYPE_SMPS, \
+ .ctrl_addr = _ctrl_addr, \
+ .test_addr = _test_addr, \
+ .clk_ctrl_addr = _clk_ctrl_addr, \
+ .sleep_ctrl_addr = _sleep_ctrl_addr, \
+ .hpm_min_load = PM8921_VREG_##_hpm_min_load##_HPM_MIN_LOAD, \
+ }
+
+#define FTSMPS(_id, _pwm_ctrl_addr, _fts_cnfg1_addr, _pfm_ctrl_addr, \
+ _pwr_cnfg_addr, _hpm_min_load) \
+ [PM8921_VREG_ID_##_id] = { \
+ .type = REGULATOR_TYPE_FTSMPS, \
+ .ctrl_addr = _pwm_ctrl_addr, \
+ .test_addr = _fts_cnfg1_addr, \
+ .pfm_ctrl_addr = _pfm_ctrl_addr, \
+ .pwr_cnfg_addr = _pwr_cnfg_addr, \
+ .hpm_min_load = PM8921_VREG_##_hpm_min_load##_HPM_MIN_LOAD, \
+ }
+
+#define VS(_id, _ctrl_addr) \
+ [PM8921_VREG_ID_##_id] = { \
+ .type = REGULATOR_TYPE_VS, \
+ .ctrl_addr = _ctrl_addr, \
+ }
+
+#define VS300(_id, _ctrl_addr) \
+ [PM8921_VREG_ID_##_id] = { \
+ .type = REGULATOR_TYPE_VS300, \
+ .ctrl_addr = _ctrl_addr, \
+ }
+
+#define NCP(_id, _ctrl_addr) \
+ [PM8921_VREG_ID_##_id] = { \
+ .type = REGULATOR_TYPE_NCP, \
+ .ctrl_addr = _ctrl_addr, \
+ }
+
+static struct pm8921_vreg pm8921_vreg[] = {
+ /* id ctrl test hpm_min */
+ NLDO(L1, 0x0AE, 0x0AF, LDO_150),
+ NLDO(L2, 0x0B0, 0x0B1, LDO_150),
+ PLDO(L3, 0x0B2, 0x0B3, LDO_150),
+ PLDO(L4, 0x0B4, 0x0B5, LDO_50),
+ PLDO(L5, 0x0B6, 0x0B7, LDO_300),
+ PLDO(L6, 0x0B8, 0x0B9, LDO_600),
+ PLDO(L7, 0x0BA, 0x0BB, LDO_150),
+ PLDO(L8, 0x0BC, 0x0BD, LDO_300),
+ PLDO(L9, 0x0BE, 0x0BF, LDO_300),
+ PLDO(L10, 0x0C0, 0x0C1, LDO_600),
+ PLDO(L11, 0x0C2, 0x0C3, LDO_150),
+ NLDO(L12, 0x0C4, 0x0C5, LDO_150),
+ PLDO(L14, 0x0C8, 0x0C9, LDO_50),
+ PLDO(L15, 0x0CA, 0x0CB, LDO_150),
+ PLDO(L16, 0x0CC, 0x0CD, LDO_300),
+ PLDO(L17, 0x0CE, 0x0CF, LDO_150),
+ NLDO(L18, 0x0D0, 0x0D1, LDO_150),
+ PLDO(L21, 0x0D6, 0x0D7, LDO_150),
+ PLDO(L22, 0x0D8, 0x0D9, LDO_150),
+ PLDO(L23, 0x0DA, 0x0DB, LDO_150),
+
+ /* id ctrl test hpm_min */
+ NLDO1200(L24, 0x0DC, 0x0DD, LDO_1200),
+ NLDO1200(L25, 0x0DE, 0x0DF, LDO_1200),
+ NLDO1200(L26, 0x0E0, 0x0E1, LDO_1200),
+ NLDO1200(L27, 0x0E2, 0x0E3, LDO_1200),
+ NLDO1200(L28, 0x0E4, 0x0E5, LDO_1200),
+
+ /* id ctrl test hpm_min */
+ PLDO(L29, 0x0E6, 0x0E7, LDO_150),
+
+ /* id ctrl test2 clk sleep hpm_min */
+ SMPS(S1, 0x1D0, 0x1D5, 0x009, 0x1D2, SMPS_1500),
+ SMPS(S2, 0x1D8, 0x1DD, 0x00A, 0x1DA, SMPS_1500),
+ SMPS(S3, 0x1E0, 0x1E5, 0x00B, 0x1E2, SMPS_1500),
+ SMPS(S4, 0x1E8, 0x1ED, 0x011, 0x1EA, SMPS_1500),
+
+ /* id ctrl fts_cnfg1 pfm pwr_cnfg hpm_min */
+ FTSMPS(S5, 0x025, 0x02E, 0x026, 0x032, SMPS_2000),
+ FTSMPS(S6, 0x036, 0x03F, 0x037, 0x043, SMPS_2000),
+
+ /* id ctrl test2 clk sleep hpm_min */
+ SMPS(S7, 0x1F0, 0x1F5, 0x012, 0x1F2, SMPS_1500),
+ SMPS(S8, 0x1F8, 0x1FD, 0x013, 0x1FA, SMPS_1500),
+
+ /* id ctrl */
+ VS(LVS1, 0x060),
+ VS300(LVS2, 0x062),
+ VS(LVS3, 0x064),
+ VS(LVS4, 0x066),
+ VS(LVS5, 0x068),
+ VS(LVS6, 0x06A),
+ VS(LVS7, 0x06C),
+ VS300(USB_OTG, 0x06E),
+ VS300(HDMI_MVS, 0x070),
+
+ /* id ctrl */
+ NCP(NCP, 0x090),
+};
+
+/* Determines which label to add to the print. */
+enum pm8921_regulator_action {
+ PM8921_REGULATOR_ACTION_INIT,
+ PM8921_REGULATOR_ACTION_ENABLE,
+ PM8921_REGULATOR_ACTION_DISABLE,
+ PM8921_REGULATOR_ACTION_VOLTAGE,
+ PM8921_REGULATOR_ACTION_MODE,
+ PM8921_REGULATOR_ACTION_PIN_CTRL,
+};
+
+/* Debug state printing */
+static void pm8921_vreg_show_state(struct regulator_dev *rdev,
+ enum pm8921_regulator_action action);
+
+/*
+ * Perform a masked write to a PMIC register only if the new value differs
+ * from the last value written to the register. This removes redundant
+ * register writing.
+ *
+ * No locking is required because registers are not shared between regulators.
+ */
+static int pm8921_vreg_masked_write(struct pm8921_vreg *vreg, u16 addr, u8 val,
+ u8 mask, u8 *reg_save)
+{
+ int rc = 0;
+ u8 reg;
+
+ reg = (*reg_save & ~mask) | (val & mask);
+ if (reg != *reg_save) {
+ rc = pm8xxx_writeb(vreg->dev->parent, addr, reg);
+
+ if (rc) {
+ pr_err("%s: pm8xxx_writeb failed; addr=0x%03X, rc=%d\n",
+ vreg->name, addr, rc);
+ } else {
+ *reg_save = reg;
+ vreg->write_count++;
+ if (pm8921_vreg_debug_mask & PM8921_VREG_DEBUG_WRITES)
+ pr_info("%s: write(0x%03X)=0x%02X", vreg->name,
+ addr, reg);
+ }
+ }
+
+ return rc;
+}
+
+/*
+ * Perform a masked write to a PMIC register without checking the previously
+ * written value. This is needed for registers that must be rewritten even if
+ * the value hasn't changed in order for changes in other registers to take
+ * effect.
+ */
+static int pm8921_vreg_masked_write_forced(struct pm8921_vreg *vreg, u16 addr,
+ u8 val, u8 mask, u8 *reg_save)
+{
+ int rc = 0;
+ u8 reg;
+
+ reg = (*reg_save & ~mask) | (val & mask);
+ rc = pm8xxx_writeb(vreg->dev->parent, addr, reg);
+
+ if (rc) {
+ pr_err("%s: pm8xxx_writeb failed; addr=0x%03X, rc=%d\n",
+ vreg->name, addr, rc);
+ } else {
+ *reg_save = reg;
+ vreg->write_count++;
+ if (pm8921_vreg_debug_mask & PM8921_VREG_DEBUG_WRITES)
+ pr_info("%s: write(0x%03X)=0x%02X", vreg->name,
+ addr, reg);
+ }
+
+ return rc;
+}
+
+static int pm8921_vreg_is_pin_controlled(struct pm8921_vreg *vreg)
+{
+ int ret = 0;
+
+ switch (vreg->type) {
+ case REGULATOR_TYPE_PLDO:
+ case REGULATOR_TYPE_NLDO:
+ ret = ((vreg->test_reg[5] & LDO_TEST_PIN_CTRL_MASK) << 4)
+ | (vreg->test_reg[6] & LDO_TEST_PIN_CTRL_LPM_MASK);
+ break;
+ case REGULATOR_TYPE_SMPS:
+ ret = vreg->sleep_ctrl_reg
+ & (SMPS_PIN_CTRL_MASK | SMPS_PIN_CTRL_LPM_MASK);
+ break;
+ case REGULATOR_TYPE_VS:
+ ret = vreg->ctrl_reg & VS_PIN_CTRL_MASK;
+ break;
+ }
+
+ return ret;
+}
+
+/*
+ * Returns the logical pin control enable state because the pin control options
+ * present in the hardware out of restart could be different from those desired
+ * by the consumer.
+ */
+static int pm8921_vreg_pin_control_is_enabled(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int enabled;
+
+ mutex_lock(&vreg->pc_lock);
+ enabled = vreg->is_enabled_pc;
+ mutex_unlock(&vreg->pc_lock);
+
+ return enabled;
+}
+
+/* Returns the physical enable state of the regulator. */
+static int _pm8921_vreg_is_enabled(struct pm8921_vreg *vreg)
+{
+ int rc = 0;
+
+ /*
+ * All regulator types except advanced mode SMPS, FTSMPS, and VS300 have
+ * enable bit in bit 7 of the control register.
+ */
+ switch (vreg->type) {
+ case REGULATOR_TYPE_FTSMPS:
+ if ((vreg->ctrl_reg & FTSMPS_VCTRL_BAND_MASK)
+ != FTSMPS_VCTRL_BAND_OFF)
+ rc = 1;
+ break;
+ case REGULATOR_TYPE_VS300:
+ if ((vreg->ctrl_reg & VS300_CTRL_ENABLE_MASK)
+ != VS300_CTRL_DISABLE)
+ rc = 1;
+ break;
+ case REGULATOR_TYPE_SMPS:
+ if (SMPS_IN_ADVANCED_MODE(vreg)) {
+ if ((vreg->ctrl_reg & SMPS_ADVANCED_BAND_MASK)
+ != SMPS_ADVANCED_BAND_OFF)
+ rc = 1;
+ break;
+ }
+ /* Fall through for legacy mode SMPS. */
+ default:
+ if ((vreg->ctrl_reg & REGULATOR_ENABLE_MASK)
+ == REGULATOR_ENABLE)
+ rc = 1;
+ }
+
+ return rc;
+}
+
+/*
+ * Returns the logical enable state of the regulator which may be different from
+ * the physical enable state thanks to HPM/LPM pin control.
+ */
+static int pm8921_vreg_is_enabled(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int enabled;
+
+ if (vreg->type == REGULATOR_TYPE_PLDO
+ || vreg->type == REGULATOR_TYPE_NLDO
+ || vreg->type == REGULATOR_TYPE_SMPS
+ || vreg->type == REGULATOR_TYPE_VS) {
+ /* Pin controllable */
+ mutex_lock(&vreg->pc_lock);
+ enabled = vreg->is_enabled;
+ mutex_unlock(&vreg->pc_lock);
+ } else {
+ /* Not pin controlable */
+ enabled = _pm8921_vreg_is_enabled(vreg);
+ }
+
+ return enabled;
+}
+
+static int pm8921_pldo_get_voltage(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int vmin, fine_step;
+ u8 range_ext, range_sel, vprog, fine_step_reg;
+
+ mutex_lock(&vreg->pc_lock);
+
+ fine_step_reg = vreg->test_reg[2] & LDO_TEST_FINE_STEP_MASK;
+ range_sel = vreg->test_reg[2] & LDO_TEST_RANGE_SEL_MASK;
+ range_ext = vreg->test_reg[4] & LDO_TEST_RANGE_EXT_MASK;
+ vprog = vreg->ctrl_reg & LDO_CTRL_VPROG_MASK;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ vprog = (vprog << 1) | (fine_step_reg >> LDO_TEST_FINE_STEP_SHIFT);
+
+ if (range_sel) {
+ /* low range mode */
+ fine_step = PLDO_LOW_UV_FINE_STEP;
+ vmin = PLDO_LOW_UV_MIN;
+ } else if (!range_ext) {
+ /* normal mode */
+ fine_step = PLDO_NORM_UV_FINE_STEP;
+ vmin = PLDO_NORM_UV_MIN;
+ } else {
+ /* high range mode */
+ fine_step = PLDO_HIGH_UV_FINE_STEP;
+ vmin = PLDO_HIGH_UV_MIN;
+ }
+
+ return fine_step * vprog + vmin;
+}
+
+static int pm8921_pldo_list_voltage(struct regulator_dev *rdev,
+ unsigned selector)
+{
+ int uV;
+
+ if (selector >= PLDO_SET_POINTS)
+ return 0;
+
+ if (selector < PLDO_LOW_SET_POINTS)
+ uV = selector * PLDO_LOW_UV_FINE_STEP + PLDO_LOW_UV_MIN;
+ else if (selector < (PLDO_LOW_SET_POINTS + PLDO_NORM_SET_POINTS))
+ uV = (selector - PLDO_LOW_SET_POINTS) * PLDO_NORM_UV_FINE_STEP
+ + PLDO_NORM_UV_MIN;
+ else
+ uV = (selector - PLDO_LOW_SET_POINTS - PLDO_NORM_SET_POINTS)
+ * PLDO_HIGH_UV_FINE_STEP
+ + PLDO_HIGH_UV_SET_POINT_MIN;
+
+ return uV;
+}
+
+static int pm8921_pldo_set_voltage(struct regulator_dev *rdev, int min_uV,
+ int max_uV, unsigned *selector)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc = 0, uV = min_uV;
+ int vmin;
+ unsigned vprog, fine_step;
+ u8 range_ext, range_sel, fine_step_reg, prev_reg;
+ bool reg_changed = false;
+
+ if (uV < PLDO_LOW_UV_MIN && max_uV >= PLDO_LOW_UV_MIN)
+ uV = PLDO_LOW_UV_MIN;
+
+ if (uV < PLDO_LOW_UV_MIN || uV > PLDO_HIGH_UV_MAX) {
+ vreg_err(vreg,
+ "request v=[%d, %d] is outside possible v=[%d, %d]\n",
+ min_uV, max_uV, PLDO_LOW_UV_MIN, PLDO_HIGH_UV_MAX);
+ return -EINVAL;
+ }
+
+ if (uV > PLDO_NORM_UV_MAX) {
+ vmin = PLDO_HIGH_UV_MIN;
+ fine_step = PLDO_HIGH_UV_FINE_STEP;
+ range_ext = LDO_TEST_RANGE_EXT_MASK;
+ range_sel = 0;
+ } else if (uV > PLDO_LOW_UV_MAX) {
+ vmin = PLDO_NORM_UV_MIN;
+ fine_step = PLDO_NORM_UV_FINE_STEP;
+ range_ext = 0;
+ range_sel = 0;
+ } else {
+ vmin = PLDO_LOW_UV_MIN;
+ fine_step = PLDO_LOW_UV_FINE_STEP;
+ range_ext = 0;
+ range_sel = LDO_TEST_RANGE_SEL_MASK;
+ }
+
+ vprog = (uV - vmin + fine_step - 1) / fine_step;
+ uV = vprog * fine_step + vmin;
+ fine_step_reg = (vprog & 1) << LDO_TEST_FINE_STEP_SHIFT;
+ vprog >>= 1;
+
+ if (uV > max_uV) {
+ vreg_err(vreg,
+ "request v=[%d, %d] cannot be met by any set point\n",
+ min_uV, max_uV);
+ return -EINVAL;
+ }
+
+ mutex_lock(&vreg->pc_lock);
+
+ /* Write fine step, range select and program voltage update. */
+ prev_reg = vreg->test_reg[2];
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ fine_step_reg | range_sel | REGULATOR_BANK_SEL(2)
+ | REGULATOR_BANK_WRITE | LDO_TEST_VPROG_UPDATE_MASK,
+ LDO_TEST_FINE_STEP_MASK | LDO_TEST_RANGE_SEL_MASK
+ | REGULATOR_BANK_MASK | LDO_TEST_VPROG_UPDATE_MASK,
+ &vreg->test_reg[2]);
+ if (rc)
+ goto bail;
+ if (prev_reg != vreg->test_reg[2])
+ reg_changed = true;
+
+ /* Write range extension. */
+ prev_reg = vreg->test_reg[4];
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ range_ext | REGULATOR_BANK_SEL(4)
+ | REGULATOR_BANK_WRITE,
+ LDO_TEST_RANGE_EXT_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[4]);
+ if (rc)
+ goto bail;
+ if (prev_reg != vreg->test_reg[4])
+ reg_changed = true;
+
+ /* Write new voltage. */
+ if (reg_changed) {
+ /*
+ * Force a CTRL register write even if the value hasn't changed.
+ * This is neccessary because range select, range extension, and
+ * fine step will not update until a value is written into the
+ * control register.
+ */
+ rc = pm8921_vreg_masked_write_forced(vreg, vreg->ctrl_addr,
+ vprog, LDO_CTRL_VPROG_MASK, &vreg->ctrl_reg);
+ } else {
+ /* Only write to control register if new value is different. */
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, vprog,
+ LDO_CTRL_VPROG_MASK, &vreg->ctrl_reg);
+ }
+bail:
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_VOLTAGE);
+
+ return rc;
+}
+
+static int pm8921_nldo_get_voltage(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ u8 vprog, fine_step_reg;
+
+ mutex_lock(&vreg->pc_lock);
+
+ fine_step_reg = vreg->test_reg[2] & LDO_TEST_FINE_STEP_MASK;
+ vprog = vreg->ctrl_reg & LDO_CTRL_VPROG_MASK;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ vprog = (vprog << 1) | (fine_step_reg >> LDO_TEST_FINE_STEP_SHIFT);
+
+ return NLDO_UV_FINE_STEP * vprog + NLDO_UV_MIN;
+}
+
+static int pm8921_nldo_list_voltage(struct regulator_dev *rdev,
+ unsigned selector)
+{
+ if (selector >= NLDO_SET_POINTS)
+ return 0;
+
+ return selector * NLDO_UV_FINE_STEP + NLDO_UV_MIN;
+}
+
+static int pm8921_nldo_set_voltage(struct regulator_dev *rdev, int min_uV,
+ int max_uV, unsigned *selector)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ unsigned vprog, fine_step_reg, prev_reg;
+ int rc;
+ int uV = min_uV;
+
+ if (uV < NLDO_UV_MIN && max_uV >= NLDO_UV_MIN)
+ uV = NLDO_UV_MIN;
+
+ if (uV < NLDO_UV_MIN || uV > NLDO_UV_MAX) {
+ vreg_err(vreg,
+ "request v=[%d, %d] is outside possible v=[%d, %d]\n",
+ min_uV, max_uV, NLDO_UV_MIN, NLDO_UV_MAX);
+ return -EINVAL;
+ }
+
+ vprog = (uV - NLDO_UV_MIN + NLDO_UV_FINE_STEP - 1) / NLDO_UV_FINE_STEP;
+ uV = vprog * NLDO_UV_FINE_STEP + NLDO_UV_MIN;
+ fine_step_reg = (vprog & 1) << LDO_TEST_FINE_STEP_SHIFT;
+ vprog >>= 1;
+
+ if (uV > max_uV) {
+ vreg_err(vreg,
+ "request v=[%d, %d] cannot be met by any set point\n",
+ min_uV, max_uV);
+ return -EINVAL;
+ }
+
+ mutex_lock(&vreg->pc_lock);
+
+ /* Write fine step. */
+ prev_reg = vreg->test_reg[2];
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ fine_step_reg | REGULATOR_BANK_SEL(2)
+ | REGULATOR_BANK_WRITE | LDO_TEST_VPROG_UPDATE_MASK,
+ LDO_TEST_FINE_STEP_MASK | REGULATOR_BANK_MASK
+ | LDO_TEST_VPROG_UPDATE_MASK,
+ &vreg->test_reg[2]);
+ if (rc)
+ goto bail;
+
+ /* Write new voltage. */
+ if (prev_reg != vreg->test_reg[2]) {
+ /*
+ * Force a CTRL register write even if the value hasn't changed.
+ * This is neccessary because fine step will not update until a
+ * value is written into the control register.
+ */
+ rc = pm8921_vreg_masked_write_forced(vreg, vreg->ctrl_addr,
+ vprog, LDO_CTRL_VPROG_MASK, &vreg->ctrl_reg);
+ } else {
+ /* Only write to control register if new value is different. */
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, vprog,
+ LDO_CTRL_VPROG_MASK, &vreg->ctrl_reg);
+ }
+bail:
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_VOLTAGE);
+
+ return rc;
+}
+
+static int _pm8921_nldo1200_get_voltage(struct pm8921_vreg *vreg)
+{
+ int uV = 0;
+ int vprog;
+
+ if (!NLDO1200_IN_ADVANCED_MODE(vreg)) {
+ pr_warn("%s: currently in legacy mode; voltage unknown.\n",
+ vreg->name);
+ return vreg->save_uV;
+ }
+
+ vprog = vreg->ctrl_reg & NLDO1200_CTRL_VPROG_MASK;
+
+ if ((vreg->ctrl_reg & NLDO1200_CTRL_RANGE_MASK)
+ == NLDO1200_CTRL_RANGE_LOW)
+ uV = vprog * NLDO1200_LOW_UV_STEP + NLDO1200_LOW_UV_MIN;
+ else
+ uV = vprog * NLDO1200_HIGH_UV_STEP + NLDO1200_HIGH_UV_MIN;
+
+ return uV;
+}
+
+static int pm8921_nldo1200_get_voltage(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+
+ return _pm8921_nldo1200_get_voltage(vreg);
+}
+
+static int pm8921_nldo1200_list_voltage(struct regulator_dev *rdev,
+ unsigned selector)
+{
+ int uV;
+
+ if (selector >= NLDO1200_SET_POINTS)
+ return 0;
+
+ if (selector < NLDO1200_LOW_SET_POINTS)
+ uV = selector * NLDO1200_LOW_UV_STEP + NLDO1200_LOW_UV_MIN;
+ else
+ uV = (selector - NLDO1200_LOW_SET_POINTS)
+ * NLDO1200_HIGH_UV_STEP
+ + NLDO1200_HIGH_UV_MIN;
+
+ return uV;
+}
+
+static int _pm8921_nldo1200_set_voltage(struct pm8921_vreg *vreg, int min_uV,
+ int max_uV)
+{
+ u8 vprog, range;
+ int rc;
+ int uV = min_uV;
+
+ if (uV < NLDO1200_LOW_UV_MIN && max_uV >= NLDO1200_LOW_UV_MIN)
+ uV = NLDO1200_LOW_UV_MIN;
+
+ if (uV < NLDO1200_LOW_UV_MIN || uV > NLDO1200_HIGH_UV_MAX) {
+ vreg_err(vreg,
+ "request v=[%d, %d] is outside possible v=[%d, %d]\n",
+ min_uV, max_uV, NLDO_UV_MIN, NLDO_UV_MAX);
+ return -EINVAL;
+ }
+
+ if (uV > NLDO1200_LOW_UV_MAX) {
+ vprog = (uV - NLDO1200_HIGH_UV_MIN + NLDO1200_HIGH_UV_STEP - 1)
+ / NLDO1200_HIGH_UV_STEP;
+ uV = vprog * NLDO1200_HIGH_UV_STEP + NLDO1200_HIGH_UV_MIN;
+ vprog &= NLDO1200_CTRL_VPROG_MASK;
+ range = NLDO1200_CTRL_RANGE_HIGH;
+ } else {
+ vprog = (uV - NLDO1200_LOW_UV_MIN + NLDO1200_LOW_UV_STEP - 1)
+ / NLDO1200_LOW_UV_STEP;
+ uV = vprog * NLDO1200_LOW_UV_STEP + NLDO1200_LOW_UV_MIN;
+ vprog &= NLDO1200_CTRL_VPROG_MASK;
+ range = NLDO1200_CTRL_RANGE_LOW;
+ }
+
+ if (uV > max_uV) {
+ vreg_err(vreg,
+ "request v=[%d, %d] cannot be met by any set point\n",
+ min_uV, max_uV);
+ return -EINVAL;
+ }
+
+ /* Set to advanced mode */
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ NLDO1200_ADVANCED_MODE | REGULATOR_BANK_SEL(2)
+ | REGULATOR_BANK_WRITE, NLDO1200_ADVANCED_MODE_MASK
+ | REGULATOR_BANK_MASK, &vreg->test_reg[2]);
+ if (rc)
+ goto bail;
+
+ /* Set voltage and range selection. */
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, vprog | range,
+ NLDO1200_CTRL_VPROG_MASK | NLDO1200_CTRL_RANGE_MASK,
+ &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ vreg->save_uV = uV;
+
+bail:
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+
+ return rc;
+}
+
+static int pm8921_nldo1200_set_voltage(struct regulator_dev *rdev, int min_uV,
+ int max_uV, unsigned *selector)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = _pm8921_nldo1200_set_voltage(vreg, min_uV, max_uV);
+
+ if (!rc)
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_VOLTAGE);
+
+ return rc;
+}
+
+static int pm8921_smps_get_voltage_advanced(struct pm8921_vreg *vreg)
+{
+ u8 vprog, band;
+ int uV = 0;
+
+ vprog = vreg->ctrl_reg & SMPS_ADVANCED_VPROG_MASK;
+ band = vreg->ctrl_reg & SMPS_ADVANCED_BAND_MASK;
+
+ if (band == SMPS_ADVANCED_BAND_1)
+ uV = vprog * SMPS_BAND1_UV_STEP + SMPS_BAND1_UV_MIN;
+ else if (band == SMPS_ADVANCED_BAND_2)
+ uV = vprog * SMPS_BAND2_UV_STEP + SMPS_BAND2_UV_MIN;
+ else if (band == SMPS_ADVANCED_BAND_3)
+ uV = vprog * SMPS_BAND3_UV_STEP + SMPS_BAND3_UV_MIN;
+ else if (vreg->save_uV > 0)
+ uV = vreg->save_uV;
+ else
+ uV = VOLTAGE_UNKNOWN;
+
+ return uV;
+}
+
+static int pm8921_smps_get_voltage_legacy(struct pm8921_vreg *vreg)
+{
+ u8 vlow, vref, vprog;
+ int uV;
+
+ vlow = vreg->test_reg[1] & SMPS_LEGACY_VLOW_SEL_MASK;
+ vref = vreg->ctrl_reg & SMPS_LEGACY_VREF_SEL_MASK;
+ vprog = vreg->ctrl_reg & SMPS_LEGACY_VPROG_MASK;
+
+ if (vlow && vref) {
+ /* mode 3 */
+ uV = vprog * SMPS_MODE3_UV_STEP + SMPS_MODE3_UV_MIN;
+ } else if (vref) {
+ /* mode 2 */
+ uV = vprog * SMPS_MODE2_UV_STEP + SMPS_MODE2_UV_MIN;
+ } else {
+ /* mode 1 */
+ uV = vprog * SMPS_MODE1_UV_STEP + SMPS_MODE1_UV_MIN;
+ }
+
+ return uV;
+}
+
+static int _pm8921_smps_get_voltage(struct pm8921_vreg *vreg)
+{
+ if (SMPS_IN_ADVANCED_MODE(vreg))
+ return pm8921_smps_get_voltage_advanced(vreg);
+
+ return pm8921_smps_get_voltage_legacy(vreg);
+}
+
+static int pm8921_smps_list_voltage(struct regulator_dev *rdev,
+ unsigned selector)
+{
+ int uV;
+
+ if (selector >= SMPS_ADVANCED_SET_POINTS)
+ return 0;
+
+ if (selector < SMPS_BAND1_SET_POINTS)
+ uV = selector * SMPS_BAND1_UV_STEP + SMPS_BAND1_UV_MIN;
+ else if (selector < (SMPS_BAND1_SET_POINTS + SMPS_BAND2_SET_POINTS))
+ uV = (selector - SMPS_BAND1_SET_POINTS) * SMPS_BAND2_UV_STEP
+ + SMPS_BAND2_UV_MIN;
+ else
+ uV = (selector - SMPS_BAND1_SET_POINTS - SMPS_BAND2_SET_POINTS)
+ * SMPS_BAND3_UV_STEP
+ + SMPS_BAND3_UV_MIN;
+
+ return uV;
+}
+
+static int pm8921_smps_get_voltage(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int uV;
+
+ mutex_lock(&vreg->pc_lock);
+ uV = _pm8921_smps_get_voltage(vreg);
+ mutex_unlock(&vreg->pc_lock);
+
+ return uV;
+}
+
+static int pm8921_smps_set_voltage_advanced(struct pm8921_vreg *vreg,
+ int min_uV, int max_uV, int force_on)
+{
+ u8 vprog, band;
+ int rc;
+ int uV = min_uV;
+
+ if (uV < SMPS_BAND1_UV_MIN && max_uV >= SMPS_BAND1_UV_MIN)
+ uV = SMPS_BAND1_UV_MIN;
+
+ if (uV < SMPS_BAND1_UV_MIN || uV > SMPS_BAND3_UV_MAX) {
+ vreg_err(vreg,
+ "request v=[%d, %d] is outside possible v=[%d, %d]\n",
+ min_uV, max_uV, SMPS_BAND1_UV_MIN, SMPS_BAND3_UV_MAX);
+ return -EINVAL;
+ }
+
+ if (uV > SMPS_BAND2_UV_MAX) {
+ vprog = (uV - SMPS_BAND3_UV_MIN + SMPS_BAND3_UV_STEP - 1)
+ / SMPS_BAND3_UV_STEP;
+ band = SMPS_ADVANCED_BAND_3;
+ uV = SMPS_BAND3_UV_MIN + vprog * SMPS_BAND3_UV_STEP;
+ } else if (uV > SMPS_BAND1_UV_MAX) {
+ vprog = (uV - SMPS_BAND2_UV_MIN + SMPS_BAND2_UV_STEP - 1)
+ / SMPS_BAND2_UV_STEP;
+ band = SMPS_ADVANCED_BAND_2;
+ uV = SMPS_BAND2_UV_MIN + vprog * SMPS_BAND2_UV_STEP;
+ } else {
+ vprog = (uV - SMPS_BAND1_UV_MIN + SMPS_BAND1_UV_STEP - 1)
+ / SMPS_BAND1_UV_STEP;
+ band = SMPS_ADVANCED_BAND_1;
+ uV = SMPS_BAND1_UV_MIN + vprog * SMPS_BAND1_UV_STEP;
+ }
+
+ if (uV > max_uV) {
+ vreg_err(vreg,
+ "request v=[%d, %d] cannot be met by any set point\n",
+ min_uV, max_uV);
+ return -EINVAL;
+ }
+
+ /* Do not set band if regulator currently disabled. */
+ if (!_pm8921_vreg_is_enabled(vreg) && !force_on)
+ band = SMPS_ADVANCED_BAND_OFF;
+
+ /* Set advanced mode bit to 1. */
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr, SMPS_ADVANCED_MODE
+ | REGULATOR_BANK_WRITE | REGULATOR_BANK_SEL(7),
+ SMPS_ADVANCED_MODE_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[7]);
+ if (rc)
+ goto bail;
+
+ /* Set voltage and voltage band. */
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, band | vprog,
+ SMPS_ADVANCED_BAND_MASK | SMPS_ADVANCED_VPROG_MASK,
+ &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ vreg->save_uV = uV;
+
+bail:
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+
+ return rc;
+}
+
+static int pm8921_smps_set_voltage_legacy(struct pm8921_vreg *vreg, int min_uV,
+ int max_uV)
+{
+ u8 vlow, vref, vprog, pd, en;
+ int rc;
+ int uV = min_uV;
+
+
+ if (uV < SMPS_MODE3_UV_MIN && max_uV >= SMPS_MODE3_UV_MIN)
+ uV = SMPS_MODE3_UV_MIN;
+
+ if (uV < SMPS_MODE3_UV_MIN || uV > SMPS_MODE1_UV_MAX) {
+ vreg_err(vreg,
+ "request v=[%d, %d] is outside possible v=[%d, %d]\n",
+ min_uV, max_uV, SMPS_MODE3_UV_MIN, SMPS_MODE1_UV_MAX);
+ return -EINVAL;
+ }
+
+ if (uV > SMPS_MODE2_UV_MAX) {
+ vprog = (uV - SMPS_MODE1_UV_MIN + SMPS_MODE1_UV_STEP - 1)
+ / SMPS_MODE1_UV_STEP;
+ vref = 0;
+ vlow = 0;
+ uV = SMPS_MODE1_UV_MIN + vprog * SMPS_MODE1_UV_STEP;
+ } else if (uV > SMPS_MODE3_UV_MAX) {
+ vprog = (uV - SMPS_MODE2_UV_MIN + SMPS_MODE2_UV_STEP - 1)
+ / SMPS_MODE2_UV_STEP;
+ vref = SMPS_LEGACY_VREF_SEL_MASK;
+ vlow = 0;
+ uV = SMPS_MODE2_UV_MIN + vprog * SMPS_MODE2_UV_STEP;
+ } else {
+ vprog = (uV - SMPS_MODE3_UV_MIN + SMPS_MODE3_UV_STEP - 1)
+ / SMPS_MODE3_UV_STEP;
+ vref = SMPS_LEGACY_VREF_SEL_MASK;
+ vlow = SMPS_LEGACY_VLOW_SEL_MASK;
+ uV = SMPS_MODE3_UV_MIN + vprog * SMPS_MODE3_UV_STEP;
+ }
+
+ if (uV > max_uV) {
+ vreg_err(vreg,
+ "request v=[%d, %d] cannot be met by any set point\n",
+ min_uV, max_uV);
+ return -EINVAL;
+ }
+
+ /* set vlow bit for ultra low voltage mode */
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ vlow | REGULATOR_BANK_WRITE | REGULATOR_BANK_SEL(1),
+ REGULATOR_BANK_MASK | SMPS_LEGACY_VLOW_SEL_MASK,
+ &vreg->test_reg[1]);
+ if (rc)
+ goto bail;
+
+ /* Set advanced mode bit to 0. */
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr, SMPS_LEGACY_MODE
+ | REGULATOR_BANK_WRITE | REGULATOR_BANK_SEL(7),
+ SMPS_ADVANCED_MODE_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[7]);
+ if (rc)
+ goto bail;
+
+ en = (_pm8921_vreg_is_enabled(vreg) ? SMPS_LEGACY_ENABLE : 0);
+ pd = (vreg->pdata.pull_down_enable ? SMPS_LEGACY_PULL_DOWN_ENABLE : 0);
+
+ /* Set voltage (and the rest of the control register). */
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ en | pd | vref | vprog,
+ SMPS_LEGACY_ENABLE_MASK | SMPS_LEGACY_PULL_DOWN_ENABLE
+ | SMPS_LEGACY_VREF_SEL_MASK | SMPS_LEGACY_VPROG_MASK,
+ &vreg->ctrl_reg);
+
+ vreg->save_uV = uV;
+
+bail:
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+
+ return rc;
+}
+
+static int pm8921_smps_set_voltage(struct regulator_dev *rdev, int min_uV,
+ int max_uV, unsigned *selector)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc = 0;
+
+ mutex_lock(&vreg->pc_lock);
+
+ if (SMPS_IN_ADVANCED_MODE(vreg) || !pm8921_vreg_is_pin_controlled(vreg))
+ rc = pm8921_smps_set_voltage_advanced(vreg, min_uV, max_uV, 0);
+ else
+ rc = pm8921_smps_set_voltage_legacy(vreg, min_uV, max_uV);
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (!rc)
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_VOLTAGE);
+
+ return rc;
+}
+
+static int _pm8921_ftsmps_get_voltage(struct pm8921_vreg *vreg)
+{
+ u8 vprog, band;
+ int uV = 0;
+
+ if ((vreg->test_reg[0] & FTSMPS_CNFG1_PM_MASK) == FTSMPS_CNFG1_PM_PFM) {
+ vprog = vreg->pfm_ctrl_reg & FTSMPS_VCTRL_VPROG_MASK;
+ band = vreg->pfm_ctrl_reg & FTSMPS_VCTRL_BAND_MASK;
+ if (band == FTSMPS_VCTRL_BAND_OFF && vprog == 0) {
+ /* PWM_VCTRL overrides PFM_VCTRL */
+ vprog = vreg->ctrl_reg & FTSMPS_VCTRL_VPROG_MASK;
+ band = vreg->ctrl_reg & FTSMPS_VCTRL_BAND_MASK;
+ }
+ } else {
+ vprog = vreg->ctrl_reg & FTSMPS_VCTRL_VPROG_MASK;
+ band = vreg->ctrl_reg & FTSMPS_VCTRL_BAND_MASK;
+ }
+
+ if (band == FTSMPS_VCTRL_BAND_1)
+ uV = vprog * FTSMPS_BAND1_UV_PHYS_STEP + FTSMPS_BAND1_UV_MIN;
+ else if (band == FTSMPS_VCTRL_BAND_2)
+ uV = vprog * FTSMPS_BAND2_UV_STEP + FTSMPS_BAND2_UV_MIN;
+ else if (band == FTSMPS_VCTRL_BAND_3)
+ uV = vprog * FTSMPS_BAND3_UV_STEP + FTSMPS_BAND3_UV_MIN;
+ else if (vreg->save_uV > 0)
+ uV = vreg->save_uV;
+ else
+ uV = VOLTAGE_UNKNOWN;
+
+ return uV;
+}
+
+static int pm8921_ftsmps_get_voltage(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+
+ return _pm8921_ftsmps_get_voltage(vreg);
+}
+
+static int pm8921_ftsmps_list_voltage(struct regulator_dev *rdev,
+ unsigned selector)
+{
+ int uV;
+
+ if (selector >= FTSMPS_SET_POINTS)
+ return 0;
+
+ if (selector < FTSMPS_BAND1_SET_POINTS)
+ uV = selector * FTSMPS_BAND1_UV_LOG_STEP + FTSMPS_BAND1_UV_MIN;
+ else if (selector < (FTSMPS_BAND1_SET_POINTS + FTSMPS_BAND2_SET_POINTS))
+ uV = (selector - FTSMPS_BAND1_SET_POINTS) * FTSMPS_BAND2_UV_STEP
+ + FTSMPS_BAND2_UV_MIN;
+ else
+ uV = (selector - FTSMPS_BAND1_SET_POINTS
+ - FTSMPS_BAND2_SET_POINTS)
+ * FTSMPS_BAND3_UV_STEP
+ + FTSMPS_BAND3_UV_SET_POINT_MIN;
+
+ return uV;
+}
+
+static int _pm8921_ftsmps_set_voltage(struct pm8921_vreg *vreg, int min_uV,
+ int max_uV, int force_on)
+{
+ int rc;
+ u8 vprog, band;
+ int uV = min_uV;
+
+ if (uV < FTSMPS_BAND1_UV_MIN && max_uV >= FTSMPS_BAND1_UV_MIN)
+ uV = FTSMPS_BAND1_UV_MIN;
+
+ if (uV < FTSMPS_BAND1_UV_MIN || uV > FTSMPS_BAND3_UV_MAX) {
+ vreg_err(vreg,
+ "request v=[%d, %d] is outside possible v=[%d, %d]\n",
+ min_uV, max_uV, FTSMPS_BAND1_UV_MIN,
+ FTSMPS_BAND3_UV_MAX);
+ return -EINVAL;
+ }
+
+ /* Round up for set points in the gaps between bands. */
+ if (uV > FTSMPS_BAND1_UV_MAX && uV < FTSMPS_BAND2_UV_MIN)
+ uV = FTSMPS_BAND2_UV_MIN;
+ else if (uV > FTSMPS_BAND2_UV_MAX
+ && uV < FTSMPS_BAND3_UV_SET_POINT_MIN)
+ uV = FTSMPS_BAND3_UV_SET_POINT_MIN;
+
+ if (uV > FTSMPS_BAND2_UV_MAX) {
+ vprog = (uV - FTSMPS_BAND3_UV_MIN + FTSMPS_BAND3_UV_STEP - 1)
+ / FTSMPS_BAND3_UV_STEP;
+ band = FTSMPS_VCTRL_BAND_3;
+ uV = FTSMPS_BAND3_UV_MIN + vprog * FTSMPS_BAND3_UV_STEP;
+ } else if (uV > FTSMPS_BAND1_UV_MAX) {
+ vprog = (uV - FTSMPS_BAND2_UV_MIN + FTSMPS_BAND2_UV_STEP - 1)
+ / FTSMPS_BAND2_UV_STEP;
+ band = FTSMPS_VCTRL_BAND_2;
+ uV = FTSMPS_BAND2_UV_MIN + vprog * FTSMPS_BAND2_UV_STEP;
+ } else {
+ vprog = (uV - FTSMPS_BAND1_UV_MIN
+ + FTSMPS_BAND1_UV_LOG_STEP - 1)
+ / FTSMPS_BAND1_UV_LOG_STEP;
+ uV = FTSMPS_BAND1_UV_MIN + vprog * FTSMPS_BAND1_UV_LOG_STEP;
+ vprog *= FTSMPS_BAND1_UV_LOG_STEP / FTSMPS_BAND1_UV_PHYS_STEP;
+ band = FTSMPS_VCTRL_BAND_1;
+ }
+
+ if (uV > max_uV) {
+ vreg_err(vreg,
+ "request v=[%d, %d] cannot be met by any set point\n",
+ min_uV, max_uV);
+ return -EINVAL;
+ }
+
+ /*
+ * Do not set voltage if regulator is currently disabled because doing
+ * so will enable it.
+ */
+ if (_pm8921_vreg_is_enabled(vreg) || force_on) {
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ band | vprog,
+ FTSMPS_VCTRL_BAND_MASK | FTSMPS_VCTRL_VPROG_MASK,
+ &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ /* Program PFM_VCTRL as 0x00 so that PWM_VCTRL overrides it. */
+ rc = pm8921_vreg_masked_write(vreg, vreg->pfm_ctrl_addr, 0x00,
+ FTSMPS_VCTRL_BAND_MASK | FTSMPS_VCTRL_VPROG_MASK,
+ &vreg->pfm_ctrl_reg);
+ if (rc)
+ goto bail;
+ }
+
+ vreg->save_uV = uV;
+
+bail:
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+
+ return rc;
+}
+
+static int pm8921_ftsmps_set_voltage(struct regulator_dev *rdev, int min_uV,
+ int max_uV, unsigned *selector)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = _pm8921_ftsmps_set_voltage(vreg, min_uV, max_uV, 0);
+
+ if (!rc)
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_VOLTAGE);
+
+ return rc;
+}
+
+static int pm8921_ncp_get_voltage(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ u8 vprog;
+
+ vprog = vreg->ctrl_reg & NCP_VPROG_MASK;
+
+ return NCP_UV_MIN + vprog * NCP_UV_STEP;
+}
+
+static int pm8921_ncp_list_voltage(struct regulator_dev *rdev,
+ unsigned selector)
+{
+ if (selector >= NCP_SET_POINTS)
+ return 0;
+
+ return selector * NCP_UV_STEP + NCP_UV_MIN;
+}
+
+static int pm8921_ncp_set_voltage(struct regulator_dev *rdev, int min_uV,
+ int max_uV, unsigned *selector)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+ int uV = min_uV;
+ u8 val;
+
+ if (uV < NCP_UV_MIN && max_uV >= NCP_UV_MIN)
+ uV = NCP_UV_MIN;
+
+ if (uV < NCP_UV_MIN || uV > NCP_UV_MAX) {
+ vreg_err(vreg,
+ "request v=[%d, %d] is outside possible v=[%d, %d]\n",
+ min_uV, max_uV, NCP_UV_MIN, NCP_UV_MAX);
+ return -EINVAL;
+ }
+
+ val = (uV - NCP_UV_MIN + NCP_UV_STEP - 1) / NCP_UV_STEP;
+ uV = val * NCP_UV_STEP + NCP_UV_MIN;
+
+ if (uV > max_uV) {
+ vreg_err(vreg,
+ "request v=[%d, %d] cannot be met by any set point\n",
+ min_uV, max_uV);
+ return -EINVAL;
+ }
+
+ /* voltage setting */
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, val,
+ NCP_VPROG_MASK, &vreg->ctrl_reg);
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_VOLTAGE);
+
+ return rc;
+}
+
+static unsigned int pm8921_ldo_get_mode(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ unsigned int mode = 0;
+
+ mutex_lock(&vreg->pc_lock);
+ mode = vreg->mode;
+ mutex_unlock(&vreg->pc_lock);
+
+ return mode;
+}
+
+static int pm8921_ldo_set_mode(struct regulator_dev *rdev, unsigned int mode)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc = 0;
+
+ if (mode != REGULATOR_MODE_NORMAL && mode != REGULATOR_MODE_IDLE) {
+ vreg_err(vreg, "invalid mode: %u\n", mode);
+ return -EINVAL;
+ }
+
+ mutex_lock(&vreg->pc_lock);
+
+ if (mode == REGULATOR_MODE_NORMAL
+ || (vreg->is_enabled_pc
+ && vreg->pdata.pin_fn == PM8921_VREG_PIN_FN_ENABLE)) {
+ /* HPM */
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ LDO_CTRL_PM_HPM, LDO_CTRL_PM_MASK, &vreg->ctrl_reg);
+ } else {
+ /* LPM */
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ LDO_CTRL_PM_LPM, LDO_CTRL_PM_MASK, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ LDO_TEST_LPM_SEL_CTRL | REGULATOR_BANK_WRITE
+ | REGULATOR_BANK_SEL(0),
+ LDO_TEST_LPM_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[0]);
+ }
+
+bail:
+ if (!rc)
+ vreg->mode = mode;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_MODE);
+
+ return rc;
+}
+
+static unsigned int pm8921_nldo1200_get_mode(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ unsigned int mode = 0;
+
+ if (NLDO1200_IN_ADVANCED_MODE(vreg)) {
+ /* Advanced mode */
+ if ((vreg->test_reg[2] & NLDO1200_ADVANCED_PM_MASK)
+ == NLDO1200_ADVANCED_PM_LPM)
+ mode = REGULATOR_MODE_IDLE;
+ else
+ mode = REGULATOR_MODE_NORMAL;
+ } else {
+ /* Legacy mode */
+ if ((vreg->ctrl_reg & NLDO1200_LEGACY_PM_MASK)
+ == NLDO1200_LEGACY_PM_LPM)
+ mode = REGULATOR_MODE_IDLE;
+ else
+ mode = REGULATOR_MODE_NORMAL;
+ }
+
+ return mode;
+}
+
+static int pm8921_nldo1200_set_mode(struct regulator_dev *rdev,
+ unsigned int mode)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc = 0;
+
+ if (mode != REGULATOR_MODE_NORMAL && mode != REGULATOR_MODE_IDLE) {
+ vreg_err(vreg, "invalid mode: %u\n", mode);
+ return -EINVAL;
+ }
+
+ /*
+ * Make sure that advanced mode is in use. If it isn't, then set it
+ * and update the voltage accordingly.
+ */
+ if (!NLDO1200_IN_ADVANCED_MODE(vreg)) {
+ rc = _pm8921_nldo1200_set_voltage(vreg, vreg->save_uV,
+ vreg->save_uV);
+ if (rc)
+ goto bail;
+ }
+
+ if (mode == REGULATOR_MODE_NORMAL) {
+ /* HPM */
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ NLDO1200_ADVANCED_PM_HPM | REGULATOR_BANK_WRITE
+ | REGULATOR_BANK_SEL(2), NLDO1200_ADVANCED_PM_MASK
+ | REGULATOR_BANK_MASK, &vreg->test_reg[2]);
+ } else {
+ /* LPM */
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ NLDO1200_ADVANCED_PM_LPM | REGULATOR_BANK_WRITE
+ | REGULATOR_BANK_SEL(2), NLDO1200_ADVANCED_PM_MASK
+ | REGULATOR_BANK_MASK, &vreg->test_reg[2]);
+ }
+
+bail:
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_MODE);
+
+ return rc;
+}
+
+static unsigned int pm8921_smps_get_mode(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ unsigned int mode = 0;
+
+ mutex_lock(&vreg->pc_lock);
+ mode = vreg->mode;
+ mutex_unlock(&vreg->pc_lock);
+
+ return mode;
+}
+
+static int pm8921_smps_set_mode(struct regulator_dev *rdev, unsigned int mode)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc = 0;
+
+ if (mode != REGULATOR_MODE_NORMAL && mode != REGULATOR_MODE_IDLE) {
+ vreg_err(vreg, "invalid mode: %u\n", mode);
+ return -EINVAL;
+ }
+
+ mutex_lock(&vreg->pc_lock);
+
+ if (mode == REGULATOR_MODE_NORMAL
+ || (vreg->is_enabled_pc
+ && vreg->pdata.pin_fn == PM8921_VREG_PIN_FN_ENABLE)) {
+ /* HPM */
+ rc = pm8921_vreg_masked_write(vreg, vreg->clk_ctrl_addr,
+ SMPS_CLK_CTRL_PWM, SMPS_CLK_CTRL_MASK,
+ &vreg->clk_ctrl_reg);
+ } else {
+ /* LPM */
+ rc = pm8921_vreg_masked_write(vreg, vreg->clk_ctrl_addr,
+ SMPS_CLK_CTRL_PFM, SMPS_CLK_CTRL_MASK,
+ &vreg->clk_ctrl_reg);
+ }
+
+ if (!rc)
+ vreg->mode = mode;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_MODE);
+
+ return rc;
+}
+
+static unsigned int pm8921_ftsmps_get_mode(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ unsigned int mode = 0;
+
+ if ((vreg->test_reg[0] & FTSMPS_CNFG1_PM_MASK) == FTSMPS_CNFG1_PM_PFM)
+ mode = REGULATOR_MODE_IDLE;
+ else
+ mode = REGULATOR_MODE_NORMAL;
+
+ return mode;
+}
+
+static int pm8921_ftsmps_set_mode(struct regulator_dev *rdev, unsigned int mode)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc = 0;
+
+ if (mode == REGULATOR_MODE_NORMAL) {
+ /* HPM */
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ FTSMPS_CNFG1_PM_PWM | REGULATOR_BANK_WRITE
+ | REGULATOR_BANK_SEL(0), FTSMPS_CNFG1_PM_MASK
+ | REGULATOR_BANK_MASK, &vreg->test_reg[0]);
+ } else if (mode == REGULATOR_MODE_IDLE) {
+ /* LPM */
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ FTSMPS_CNFG1_PM_PFM | REGULATOR_BANK_WRITE
+ | REGULATOR_BANK_SEL(0), FTSMPS_CNFG1_PM_MASK
+ | REGULATOR_BANK_MASK, &vreg->test_reg[0]);
+ } else {
+ vreg_err(vreg, "invalid mode: %u\n", mode);
+ return -EINVAL;
+ }
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_MODE);
+
+ return rc;
+}
+
+static unsigned int pm8921_vreg_get_optimum_mode(struct regulator_dev *rdev,
+ int input_uV, int output_uV, int load_uA)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ unsigned int mode;
+
+ if (load_uA + vreg->pdata.system_uA >= vreg->hpm_min_load)
+ mode = REGULATOR_MODE_NORMAL;
+ else
+ mode = REGULATOR_MODE_IDLE;
+
+ return mode;
+}
+
+static int pm8921_ldo_enable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc, val;
+
+ mutex_lock(&vreg->pc_lock);
+
+ /*
+ * Choose HPM if previously set to HPM or if pin control is enabled in
+ * on/off mode.
+ */
+ val = LDO_CTRL_PM_LPM;
+ if (vreg->mode == REGULATOR_MODE_NORMAL
+ || (vreg->is_enabled_pc
+ && vreg->pdata.pin_fn == PM8921_VREG_PIN_FN_ENABLE))
+ val = LDO_CTRL_PM_HPM;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, val | LDO_ENABLE,
+ LDO_ENABLE_MASK | LDO_CTRL_PM_MASK, &vreg->ctrl_reg);
+
+ if (!rc)
+ vreg->is_enabled = true;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_ENABLE);
+
+ return rc;
+}
+
+static int pm8921_ldo_disable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ mutex_lock(&vreg->pc_lock);
+
+ /*
+ * Only disable the regulator if it isn't still required for HPM/LPM
+ * pin control.
+ */
+ if (!vreg->is_enabled_pc
+ || vreg->pdata.pin_fn != PM8921_VREG_PIN_FN_MODE) {
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ LDO_DISABLE, LDO_ENABLE_MASK, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+ }
+
+ /* Change to LPM if HPM/LPM pin control is enabled. */
+ if (vreg->is_enabled_pc
+ && vreg->pdata.pin_fn == PM8921_VREG_PIN_FN_MODE) {
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ LDO_CTRL_PM_LPM, LDO_CTRL_PM_MASK, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ LDO_TEST_LPM_SEL_CTRL | REGULATOR_BANK_WRITE
+ | REGULATOR_BANK_SEL(0),
+ LDO_TEST_LPM_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[0]);
+ }
+
+ if (!rc)
+ vreg->is_enabled = false;
+bail:
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_DISABLE);
+
+ return rc;
+}
+
+static int pm8921_nldo1200_enable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, NLDO1200_ENABLE,
+ NLDO1200_ENABLE_MASK, &vreg->ctrl_reg);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_ENABLE);
+
+ return rc;
+}
+
+static int pm8921_nldo1200_disable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, NLDO1200_DISABLE,
+ NLDO1200_ENABLE_MASK, &vreg->ctrl_reg);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_DISABLE);
+
+ return rc;
+}
+
+static int pm8921_smps_enable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc = 0;
+ int val;
+
+ mutex_lock(&vreg->pc_lock);
+
+ if (SMPS_IN_ADVANCED_MODE(vreg)
+ || !pm8921_vreg_is_pin_controlled(vreg)) {
+ /* Enable in advanced mode if not using pin control. */
+ rc = pm8921_smps_set_voltage_advanced(vreg, vreg->save_uV,
+ vreg->save_uV, 1);
+ } else {
+ rc = pm8921_smps_set_voltage_legacy(vreg, vreg->save_uV,
+ vreg->save_uV);
+ if (rc)
+ goto bail;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ SMPS_LEGACY_ENABLE, SMPS_LEGACY_ENABLE_MASK,
+ &vreg->ctrl_reg);
+ }
+
+ /*
+ * Choose HPM if previously set to HPM or if pin control is enabled in
+ * on/off mode.
+ */
+ val = SMPS_CLK_CTRL_PFM;
+ if (vreg->mode == REGULATOR_MODE_NORMAL
+ || (vreg->is_enabled_pc
+ && vreg->pdata.pin_fn == PM8921_VREG_PIN_FN_ENABLE))
+ val = SMPS_CLK_CTRL_PWM;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->clk_ctrl_addr, val,
+ SMPS_CLK_CTRL_MASK, &vreg->clk_ctrl_reg);
+
+ if (!rc)
+ vreg->is_enabled = true;
+bail:
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_ENABLE);
+
+ return rc;
+}
+
+static int pm8921_smps_disable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ mutex_lock(&vreg->pc_lock);
+
+ if (SMPS_IN_ADVANCED_MODE(vreg)) {
+ /* Change SMPS to legacy mode before disabling. */
+ rc = pm8921_smps_set_voltage_legacy(vreg, vreg->save_uV,
+ vreg->save_uV);
+ if (rc)
+ goto bail;
+ }
+
+ /*
+ * Only disable the regulator if it isn't still required for HPM/LPM
+ * pin control.
+ */
+ if (!vreg->is_enabled_pc
+ || vreg->pdata.pin_fn != PM8921_VREG_PIN_FN_MODE) {
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ SMPS_LEGACY_DISABLE, SMPS_LEGACY_ENABLE_MASK,
+ &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+ }
+
+ /* Change to LPM if HPM/LPM pin control is enabled. */
+ if (vreg->is_enabled_pc
+ && vreg->pdata.pin_fn == PM8921_VREG_PIN_FN_MODE)
+ rc = pm8921_vreg_masked_write(vreg, vreg->clk_ctrl_addr,
+ SMPS_CLK_CTRL_PFM, SMPS_CLK_CTRL_MASK,
+ &vreg->clk_ctrl_reg);
+
+ if (!rc)
+ vreg->is_enabled = false;
+
+bail:
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_DISABLE);
+
+ return rc;
+}
+
+static int pm8921_ftsmps_enable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = _pm8921_ftsmps_set_voltage(vreg, vreg->save_uV, vreg->save_uV, 1);
+
+ if (rc)
+ vreg_err(vreg, "set voltage failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_ENABLE);
+
+ return rc;
+}
+
+static int pm8921_ftsmps_disable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ FTSMPS_VCTRL_BAND_OFF, FTSMPS_VCTRL_BAND_MASK, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->pfm_ctrl_addr,
+ FTSMPS_VCTRL_BAND_OFF, FTSMPS_VCTRL_BAND_MASK,
+ &vreg->pfm_ctrl_reg);
+bail:
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_DISABLE);
+
+ return rc;
+}
+
+static int pm8921_vs_enable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ mutex_lock(&vreg->pc_lock);
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, VS_ENABLE,
+ VS_ENABLE_MASK, &vreg->ctrl_reg);
+
+ if (!rc)
+ vreg->is_enabled = true;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_ENABLE);
+
+ return rc;
+}
+
+static int pm8921_vs_disable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ mutex_lock(&vreg->pc_lock);
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, VS_DISABLE,
+ VS_ENABLE_MASK, &vreg->ctrl_reg);
+
+ if (!rc)
+ vreg->is_enabled = false;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_DISABLE);
+
+ return rc;
+}
+
+static int pm8921_vs300_enable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, VS300_CTRL_ENABLE,
+ VS300_CTRL_ENABLE_MASK, &vreg->ctrl_reg);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_ENABLE);
+
+ return rc;
+}
+
+static int pm8921_vs300_disable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, VS300_CTRL_DISABLE,
+ VS300_CTRL_ENABLE_MASK, &vreg->ctrl_reg);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_DISABLE);
+
+ return rc;
+}
+
+static int pm8921_ncp_enable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, NCP_ENABLE,
+ NCP_ENABLE_MASK, &vreg->ctrl_reg);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_ENABLE);
+
+ return rc;
+}
+
+static int pm8921_ncp_disable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, NCP_DISABLE,
+ NCP_ENABLE_MASK, &vreg->ctrl_reg);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_DISABLE);
+
+ return rc;
+}
+
+static int pm8921_ldo_pin_control_enable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc = 0;
+ int bank;
+ u8 val = 0;
+ u8 mask;
+
+ mutex_lock(&vreg->pc_lock);
+
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_D1)
+ val |= LDO_TEST_PIN_CTRL_EN0;
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_A0)
+ val |= LDO_TEST_PIN_CTRL_EN1;
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_A1)
+ val |= LDO_TEST_PIN_CTRL_EN2;
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_A2)
+ val |= LDO_TEST_PIN_CTRL_EN3;
+
+ bank = (vreg->pdata.pin_fn == PM8921_VREG_PIN_FN_ENABLE ? 5 : 6);
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ val | REGULATOR_BANK_SEL(bank) | REGULATOR_BANK_WRITE,
+ LDO_TEST_PIN_CTRL_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[bank]);
+ if (rc)
+ goto bail;
+
+ /* Unset pin control bits in unused bank. */
+ bank = (bank == 5 ? 6 : 5);
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ REGULATOR_BANK_SEL(bank) | REGULATOR_BANK_WRITE,
+ LDO_TEST_PIN_CTRL_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[bank]);
+ if (rc)
+ goto bail;
+
+ val = LDO_TEST_LPM_SEL_CTRL | REGULATOR_BANK_WRITE
+ | REGULATOR_BANK_SEL(0);
+ mask = LDO_TEST_LPM_MASK | REGULATOR_BANK_MASK;
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr, val, mask,
+ &vreg->test_reg[0]);
+ if (rc)
+ goto bail;
+
+ if (vreg->pdata.pin_fn == PM8921_VREG_PIN_FN_ENABLE) {
+ /* Pin control ON/OFF */
+ val = LDO_CTRL_PM_HPM;
+ /* Leave physically enabled if already enabled. */
+ val |= (vreg->is_enabled ? LDO_ENABLE : LDO_DISABLE);
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, val,
+ LDO_ENABLE_MASK | LDO_CTRL_PM_MASK, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+ } else {
+ /* Pin control LPM/HPM */
+ val = LDO_ENABLE;
+ /* Leave in HPM if already enabled in HPM. */
+ val |= (vreg->is_enabled && vreg->mode == REGULATOR_MODE_NORMAL
+ ? LDO_CTRL_PM_HPM : LDO_CTRL_PM_LPM);
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, val,
+ LDO_ENABLE_MASK | LDO_CTRL_PM_MASK, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+ }
+
+bail:
+ if (!rc)
+ vreg->is_enabled_pc = true;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_PIN_CTRL);
+
+ return rc;
+}
+
+static int pm8921_ldo_pin_control_disable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ mutex_lock(&vreg->pc_lock);
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ REGULATOR_BANK_SEL(5) | REGULATOR_BANK_WRITE,
+ LDO_TEST_PIN_CTRL_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[5]);
+ if (rc)
+ goto bail;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ REGULATOR_BANK_SEL(6) | REGULATOR_BANK_WRITE,
+ LDO_TEST_PIN_CTRL_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[6]);
+
+ /*
+ * Physically disable the regulator if it was enabled in HPM/LPM pin
+ * control mode previously and it logically should not be enabled.
+ */
+ if ((vreg->ctrl_reg & LDO_ENABLE_MASK) == LDO_ENABLE
+ && !vreg->is_enabled) {
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ LDO_DISABLE, LDO_ENABLE_MASK, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+ }
+
+ /* Change to LPM if LPM was enabled. */
+ if (vreg->is_enabled && vreg->mode == REGULATOR_MODE_IDLE) {
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ LDO_CTRL_PM_LPM, LDO_CTRL_PM_MASK, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ LDO_TEST_LPM_SEL_CTRL | REGULATOR_BANK_WRITE
+ | REGULATOR_BANK_SEL(0),
+ LDO_TEST_LPM_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[0]);
+ if (rc)
+ goto bail;
+ }
+
+bail:
+ if (!rc)
+ vreg->is_enabled_pc = false;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_PIN_CTRL);
+
+ return rc;
+}
+
+static int pm8921_smps_pin_control_enable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc = 0;
+ u8 val = 0;
+
+ mutex_lock(&vreg->pc_lock);
+
+ if (vreg->pdata.pin_fn == PM8921_VREG_PIN_FN_ENABLE) {
+ /* Pin control ON/OFF */
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_D1)
+ val |= SMPS_PIN_CTRL_EN0;
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_A0)
+ val |= SMPS_PIN_CTRL_EN1;
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_A1)
+ val |= SMPS_PIN_CTRL_EN2;
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_A2)
+ val |= SMPS_PIN_CTRL_EN3;
+ } else {
+ /* Pin control LPM/HPM */
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_D1)
+ val |= SMPS_PIN_CTRL_LPM_EN0;
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_A0)
+ val |= SMPS_PIN_CTRL_LPM_EN1;
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_A1)
+ val |= SMPS_PIN_CTRL_LPM_EN2;
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_A2)
+ val |= SMPS_PIN_CTRL_LPM_EN3;
+ }
+
+ rc = pm8921_smps_set_voltage_legacy(vreg, vreg->save_uV, vreg->save_uV);
+ if (rc)
+ goto bail;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->sleep_ctrl_addr, val,
+ SMPS_PIN_CTRL_MASK | SMPS_PIN_CTRL_LPM_MASK,
+ &vreg->sleep_ctrl_reg);
+ if (rc)
+ goto bail;
+
+ /*
+ * Physically enable the regulator if using HPM/LPM pin control mode or
+ * if the regulator should be logically left on.
+ */
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ ((vreg->pdata.pin_fn == PM8921_VREG_PIN_FN_MODE
+ || vreg->is_enabled) ?
+ SMPS_LEGACY_ENABLE : SMPS_LEGACY_DISABLE),
+ SMPS_LEGACY_ENABLE_MASK, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ /*
+ * Set regulator to HPM if using on/off pin control or if the regulator
+ * is already enabled in HPM. Otherwise, set it to LPM.
+ */
+ rc = pm8921_vreg_masked_write(vreg, vreg->clk_ctrl_addr,
+ (vreg->pdata.pin_fn == PM8921_VREG_PIN_FN_ENABLE
+ || (vreg->is_enabled
+ && vreg->mode == REGULATOR_MODE_NORMAL)
+ ? SMPS_CLK_CTRL_PWM : SMPS_CLK_CTRL_PFM),
+ SMPS_CLK_CTRL_MASK, &vreg->clk_ctrl_reg);
+
+bail:
+ if (!rc)
+ vreg->is_enabled_pc = true;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_PIN_CTRL);
+
+ return rc;
+}
+
+static int pm8921_smps_pin_control_disable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ mutex_lock(&vreg->pc_lock);
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->sleep_ctrl_addr, 0,
+ SMPS_PIN_CTRL_MASK | SMPS_PIN_CTRL_LPM_MASK,
+ &vreg->sleep_ctrl_reg);
+ if (rc)
+ goto bail;
+
+ /*
+ * Physically disable the regulator if it was enabled in HPM/LPM pin
+ * control mode previously and it logically should not be enabled.
+ */
+ if ((vreg->ctrl_reg & SMPS_LEGACY_ENABLE_MASK) == SMPS_LEGACY_ENABLE
+ && vreg->is_enabled == false) {
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ SMPS_LEGACY_DISABLE, SMPS_LEGACY_ENABLE_MASK,
+ &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+ }
+
+ /* Change to LPM if LPM was enabled. */
+ if (vreg->is_enabled && vreg->mode == REGULATOR_MODE_IDLE) {
+ rc = pm8921_vreg_masked_write(vreg, vreg->clk_ctrl_addr,
+ SMPS_CLK_CTRL_PFM, SMPS_CLK_CTRL_MASK,
+ &vreg->clk_ctrl_reg);
+ if (rc)
+ goto bail;
+ }
+
+ rc = pm8921_smps_set_voltage_advanced(vreg, vreg->save_uV,
+ vreg->save_uV, 0);
+
+bail:
+ if (!rc)
+ vreg->is_enabled_pc = false;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_PIN_CTRL);
+
+ return rc;
+}
+
+static int pm8921_vs_pin_control_enable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+ u8 val = 0;
+
+ mutex_lock(&vreg->pc_lock);
+
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_D1)
+ val |= VS_PIN_CTRL_EN0;
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_A0)
+ val |= VS_PIN_CTRL_EN1;
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_A1)
+ val |= VS_PIN_CTRL_EN2;
+ if (vreg->pdata.pin_ctrl & PM8921_VREG_PIN_CTRL_A2)
+ val |= VS_PIN_CTRL_EN3;
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, val,
+ VS_PIN_CTRL_MASK | VS_ENABLE_MASK, &vreg->ctrl_reg);
+
+ if (!rc)
+ vreg->is_enabled_pc = true;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_PIN_CTRL);
+
+ return rc;
+}
+
+static int pm8921_vs_pin_control_disable(struct regulator_dev *rdev)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ mutex_lock(&vreg->pc_lock);
+
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr, 0,
+ VS_PIN_CTRL_MASK, &vreg->ctrl_reg);
+
+ if (!rc)
+ vreg->is_enabled_pc = false;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+ else
+ pm8921_vreg_show_state(rdev, PM8921_REGULATOR_ACTION_PIN_CTRL);
+
+ return rc;
+}
+
+static const char const *pm8921_print_actions[] = {
+ [PM8921_REGULATOR_ACTION_INIT] = "initial ",
+ [PM8921_REGULATOR_ACTION_ENABLE] = "enable ",
+ [PM8921_REGULATOR_ACTION_DISABLE] = "disable ",
+ [PM8921_REGULATOR_ACTION_VOLTAGE] = "set voltage",
+ [PM8921_REGULATOR_ACTION_MODE] = "set mode ",
+ [PM8921_REGULATOR_ACTION_PIN_CTRL] = "pin control",
+};
+
+static void pm8921_vreg_show_state(struct regulator_dev *rdev,
+ enum pm8921_regulator_action action)
+{
+ struct pm8921_vreg *vreg = rdev_get_drvdata(rdev);
+ int uV, pc;
+ unsigned int mode;
+ const char *pc_en0 = "", *pc_en1 = "", *pc_en2 = "", *pc_en3 = "";
+ const char *pc_total = "";
+ const char *action_label = pm8921_print_actions[action];
+ const char *enable_label;
+
+ mutex_lock(&vreg->pc_lock);
+
+ /*
+ * Do not print unless REQUEST is specified and SSBI writes have taken
+ * place, or DUPLICATE is specified.
+ */
+ if (!((pm8921_vreg_debug_mask & PM8921_VREG_DEBUG_DUPLICATE)
+ || ((pm8921_vreg_debug_mask & PM8921_VREG_DEBUG_REQUEST)
+ && (vreg->write_count != vreg->prev_write_count)))) {
+ mutex_unlock(&vreg->pc_lock);
+ return;
+ }
+
+ vreg->prev_write_count = vreg->write_count;
+
+ pc = vreg->pdata.pin_ctrl;
+ if (vreg->is_enabled_pc) {
+ if (pc & PM8921_VREG_PIN_CTRL_D1)
+ pc_en0 = " D1";
+ if (pc & PM8921_VREG_PIN_CTRL_A0)
+ pc_en1 = " A0";
+ if (pc & PM8921_VREG_PIN_CTRL_A1)
+ pc_en2 = " A1";
+ if (pc & PM8921_VREG_PIN_CTRL_A2)
+ pc_en3 = " A2";
+ if (pc == PM8921_VREG_PIN_CTRL_NONE)
+ pc_total = " none";
+ } else {
+ pc_total = " none";
+ }
+
+ mutex_unlock(&vreg->pc_lock);
+
+ enable_label = pm8921_vreg_is_enabled(rdev) ? "on " : "off";
+
+ switch (vreg->type) {
+ case REGULATOR_TYPE_PLDO:
+ uV = pm8921_pldo_get_voltage(rdev);
+ mode = pm8921_ldo_get_mode(rdev);
+ pr_info("%s %-9s: %s, v=%7d uV, mode=%s, pc=%s%s%s%s%s\n",
+ action_label, vreg->name, enable_label, uV,
+ (mode == REGULATOR_MODE_NORMAL ? "HPM" : "LPM"),
+ pc_en0, pc_en1, pc_en2, pc_en3, pc_total);
+ break;
+ case REGULATOR_TYPE_NLDO:
+ uV = pm8921_nldo_get_voltage(rdev);
+ mode = pm8921_ldo_get_mode(rdev);
+ pr_info("%s %-9s: %s, v=%7d uV, mode=%s, pc=%s%s%s%s%s\n",
+ action_label, vreg->name, enable_label, uV,
+ (mode == REGULATOR_MODE_NORMAL ? "HPM" : "LPM"),
+ pc_en0, pc_en1, pc_en2, pc_en3, pc_total);
+ break;
+ case REGULATOR_TYPE_NLDO1200:
+ uV = pm8921_nldo1200_get_voltage(rdev);
+ mode = pm8921_nldo1200_get_mode(rdev);
+ pr_info("%s %-9s: %s, v=%7d uV, mode=%s\n",
+ action_label, vreg->name, enable_label, uV,
+ (mode == REGULATOR_MODE_NORMAL ? "HPM" : "LPM"));
+ break;
+ case REGULATOR_TYPE_SMPS:
+ uV = pm8921_smps_get_voltage(rdev);
+ mode = pm8921_smps_get_mode(rdev);
+ pr_info("%s %-9s: %s, v=%7d uV, mode=%s, pc=%s%s%s%s%s\n",
+ action_label, vreg->name, enable_label, uV,
+ (mode == REGULATOR_MODE_NORMAL ? "HPM" : "LPM"),
+ pc_en0, pc_en1, pc_en2, pc_en3, pc_total);
+ break;
+ case REGULATOR_TYPE_FTSMPS:
+ uV = pm8921_ftsmps_get_voltage(rdev);
+ mode = pm8921_ftsmps_get_mode(rdev);
+ pr_info("%s %-9s: %s, v=%7d uV, mode=%s\n",
+ action_label, vreg->name, enable_label, uV,
+ (mode == REGULATOR_MODE_NORMAL ? "HPM" : "LPM"));
+ break;
+ case REGULATOR_TYPE_VS:
+ pr_info("%s %-9s: %s, pc=%s%s%s%s%s\n",
+ action_label, vreg->name, enable_label,
+ pc_en0, pc_en1, pc_en2, pc_en3, pc_total);
+ break;
+ case REGULATOR_TYPE_VS300:
+ pr_info("%s %-9s: %s\n",
+ action_label, vreg->name, enable_label);
+ break;
+ case REGULATOR_TYPE_NCP:
+ uV = pm8921_ncp_get_voltage(rdev);
+ pr_info("%s %-9s: %s, v=%7d uV\n",
+ action_label, vreg->name, enable_label, uV);
+ break;
+ default:
+ break;
+ }
+}
+
+
+/* Real regulator operations. */
+static struct regulator_ops pm8921_pldo_ops = {
+ .enable = pm8921_ldo_enable,
+ .disable = pm8921_ldo_disable,
+ .is_enabled = pm8921_vreg_is_enabled,
+ .set_voltage = pm8921_pldo_set_voltage,
+ .get_voltage = pm8921_pldo_get_voltage,
+ .list_voltage = pm8921_pldo_list_voltage,
+ .set_mode = pm8921_ldo_set_mode,
+ .get_mode = pm8921_ldo_get_mode,
+ .get_optimum_mode = pm8921_vreg_get_optimum_mode,
+};
+
+static struct regulator_ops pm8921_nldo_ops = {
+ .enable = pm8921_ldo_enable,
+ .disable = pm8921_ldo_disable,
+ .is_enabled = pm8921_vreg_is_enabled,
+ .set_voltage = pm8921_nldo_set_voltage,
+ .get_voltage = pm8921_nldo_get_voltage,
+ .list_voltage = pm8921_nldo_list_voltage,
+ .set_mode = pm8921_ldo_set_mode,
+ .get_mode = pm8921_ldo_get_mode,
+ .get_optimum_mode = pm8921_vreg_get_optimum_mode,
+};
+
+static struct regulator_ops pm8921_nldo1200_ops = {
+ .enable = pm8921_nldo1200_enable,
+ .disable = pm8921_nldo1200_disable,
+ .is_enabled = pm8921_vreg_is_enabled,
+ .set_voltage = pm8921_nldo1200_set_voltage,
+ .get_voltage = pm8921_nldo1200_get_voltage,
+ .list_voltage = pm8921_nldo1200_list_voltage,
+ .set_mode = pm8921_nldo1200_set_mode,
+ .get_mode = pm8921_nldo1200_get_mode,
+ .get_optimum_mode = pm8921_vreg_get_optimum_mode,
+};
+
+static struct regulator_ops pm8921_smps_ops = {
+ .enable = pm8921_smps_enable,
+ .disable = pm8921_smps_disable,
+ .is_enabled = pm8921_vreg_is_enabled,
+ .set_voltage = pm8921_smps_set_voltage,
+ .get_voltage = pm8921_smps_get_voltage,
+ .list_voltage = pm8921_smps_list_voltage,
+ .set_mode = pm8921_smps_set_mode,
+ .get_mode = pm8921_smps_get_mode,
+ .get_optimum_mode = pm8921_vreg_get_optimum_mode,
+};
+
+static struct regulator_ops pm8921_ftsmps_ops = {
+ .enable = pm8921_ftsmps_enable,
+ .disable = pm8921_ftsmps_disable,
+ .is_enabled = pm8921_vreg_is_enabled,
+ .set_voltage = pm8921_ftsmps_set_voltage,
+ .get_voltage = pm8921_ftsmps_get_voltage,
+ .list_voltage = pm8921_ftsmps_list_voltage,
+ .set_mode = pm8921_ftsmps_set_mode,
+ .get_mode = pm8921_ftsmps_get_mode,
+ .get_optimum_mode = pm8921_vreg_get_optimum_mode,
+};
+
+static struct regulator_ops pm8921_vs_ops = {
+ .enable = pm8921_vs_enable,
+ .disable = pm8921_vs_disable,
+ .is_enabled = pm8921_vreg_is_enabled,
+};
+
+static struct regulator_ops pm8921_vs300_ops = {
+ .enable = pm8921_vs300_enable,
+ .disable = pm8921_vs300_disable,
+ .is_enabled = pm8921_vreg_is_enabled,
+};
+
+static struct regulator_ops pm8921_ncp_ops = {
+ .enable = pm8921_ncp_enable,
+ .disable = pm8921_ncp_disable,
+ .is_enabled = pm8921_vreg_is_enabled,
+ .set_voltage = pm8921_ncp_set_voltage,
+ .get_voltage = pm8921_ncp_get_voltage,
+ .list_voltage = pm8921_ncp_list_voltage,
+};
+
+/* Pin control regulator operations. */
+static struct regulator_ops pm8921_ldo_pc_ops = {
+ .enable = pm8921_ldo_pin_control_enable,
+ .disable = pm8921_ldo_pin_control_disable,
+ .is_enabled = pm8921_vreg_pin_control_is_enabled,
+};
+
+static struct regulator_ops pm8921_smps_pc_ops = {
+ .enable = pm8921_smps_pin_control_enable,
+ .disable = pm8921_smps_pin_control_disable,
+ .is_enabled = pm8921_vreg_pin_control_is_enabled,
+};
+
+static struct regulator_ops pm8921_vs_pc_ops = {
+ .enable = pm8921_vs_pin_control_enable,
+ .disable = pm8921_vs_pin_control_disable,
+ .is_enabled = pm8921_vreg_pin_control_is_enabled,
+};
+
+#define VREG_DESC(_id, _name, _ops, _n_voltages) \
+ [PM8921_VREG_ID_##_id] = { \
+ .id = PM8921_VREG_ID_##_id, \
+ .name = _name, \
+ .n_voltages = _n_voltages, \
+ .ops = _ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .owner = THIS_MODULE, \
+ }
+
+static struct regulator_desc pm8921_vreg_description[] = {
+ VREG_DESC(L1, "8921_l1", &pm8921_nldo_ops, NLDO_SET_POINTS),
+ VREG_DESC(L2, "8921_l2", &pm8921_nldo_ops, NLDO_SET_POINTS),
+ VREG_DESC(L3, "8921_l3", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L4, "8921_l4", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L5, "8921_l5", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L6, "8921_l6", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L7, "8921_l7", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L8, "8921_l8", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L9, "8921_l9", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L10, "8921_l10", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L11, "8921_l11", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L12, "8921_l12", &pm8921_nldo_ops, NLDO_SET_POINTS),
+ VREG_DESC(L14, "8921_l14", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L15, "8921_l15", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L16, "8921_l16", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L17, "8921_l17", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L18, "8921_l18", &pm8921_nldo_ops, NLDO_SET_POINTS),
+ VREG_DESC(L21, "8921_l21", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L22, "8921_l22", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L23, "8921_l23", &pm8921_pldo_ops, PLDO_SET_POINTS),
+ VREG_DESC(L24, "8921_l24", &pm8921_nldo1200_ops, NLDO1200_SET_POINTS),
+ VREG_DESC(L25, "8921_l25", &pm8921_nldo1200_ops, NLDO1200_SET_POINTS),
+ VREG_DESC(L26, "8921_l26", &pm8921_nldo1200_ops, NLDO1200_SET_POINTS),
+ VREG_DESC(L27, "8921_l27", &pm8921_nldo1200_ops, NLDO1200_SET_POINTS),
+ VREG_DESC(L28, "8921_l28", &pm8921_nldo1200_ops, NLDO1200_SET_POINTS),
+ VREG_DESC(L29, "8921_l29", &pm8921_pldo_ops, PLDO_SET_POINTS),
+
+ VREG_DESC(S1, "8921_s1", &pm8921_smps_ops, SMPS_ADVANCED_SET_POINTS),
+ VREG_DESC(S2, "8921_s2", &pm8921_smps_ops, SMPS_ADVANCED_SET_POINTS),
+ VREG_DESC(S3, "8921_s3", &pm8921_smps_ops, SMPS_ADVANCED_SET_POINTS),
+ VREG_DESC(S4, "8921_s4", &pm8921_smps_ops, SMPS_ADVANCED_SET_POINTS),
+ VREG_DESC(S5, "8921_s5", &pm8921_ftsmps_ops, FTSMPS_SET_POINTS),
+ VREG_DESC(S6, "8921_s6", &pm8921_ftsmps_ops, FTSMPS_SET_POINTS),
+ VREG_DESC(S7, "8921_s7", &pm8921_smps_ops, SMPS_ADVANCED_SET_POINTS),
+ VREG_DESC(S8, "8921_s8", &pm8921_smps_ops, SMPS_ADVANCED_SET_POINTS),
+
+ VREG_DESC(LVS1, "8921_lvs1", &pm8921_vs_ops, 0),
+ VREG_DESC(LVS2, "8921_lvs2", &pm8921_vs300_ops, 0),
+ VREG_DESC(LVS3, "8921_lvs3", &pm8921_vs_ops, 0),
+ VREG_DESC(LVS4, "8921_lvs4", &pm8921_vs_ops, 0),
+ VREG_DESC(LVS5, "8921_lvs5", &pm8921_vs_ops, 0),
+ VREG_DESC(LVS6, "8921_lvs6", &pm8921_vs_ops, 0),
+ VREG_DESC(LVS7, "8921_lvs7", &pm8921_vs_ops, 0),
+
+ VREG_DESC(USB_OTG, "8921_usb_otg", &pm8921_vs300_ops, 0),
+ VREG_DESC(HDMI_MVS, "8921_hdmi_mvs", &pm8921_vs300_ops, 0),
+ VREG_DESC(NCP, "8921_ncp", &pm8921_ncp_ops, NCP_SET_POINTS),
+
+ VREG_DESC(L1_PC, "8921_l1_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L2_PC, "8921_l2_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L3_PC, "8921_l3_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L4_PC, "8921_l4_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L5_PC, "8921_l5_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L6_PC, "8921_l6_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L7_PC, "8921_l7_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L8_PC, "8921_l8_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L9_PC, "8921_l9_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L10_PC, "8921_l10_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L11_PC, "8921_l11_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L12_PC, "8921_l12_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L14_PC, "8921_l14_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L15_PC, "8921_l15_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L16_PC, "8921_l16_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L17_PC, "8921_l17_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L18_PC, "8921_l18_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L21_PC, "8921_l21_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L22_PC, "8921_l22_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L23_PC, "8921_l23_pc", &pm8921_ldo_pc_ops, 0),
+ VREG_DESC(L29_PC, "8921_l29_pc", &pm8921_ldo_pc_ops, 0),
+
+ VREG_DESC(S1_PC, "8921_s1_pc", &pm8921_smps_pc_ops, 0),
+ VREG_DESC(S2_PC, "8921_s2_pc", &pm8921_smps_pc_ops, 0),
+ VREG_DESC(S3_PC, "8921_s3_pc", &pm8921_smps_pc_ops, 0),
+ VREG_DESC(S4_PC, "8921_s4_pc", &pm8921_smps_pc_ops, 0),
+ VREG_DESC(S7_PC, "8921_s7_pc", &pm8921_smps_pc_ops, 0),
+ VREG_DESC(S8_PC, "8921_s8_pc", &pm8921_smps_pc_ops, 0),
+
+ VREG_DESC(LVS1_PC, "8921_lvs1_pc", &pm8921_vs_pc_ops, 0),
+ VREG_DESC(LVS3_PC, "8921_lvs3_pc", &pm8921_vs_pc_ops, 0),
+ VREG_DESC(LVS4_PC, "8921_lvs4_pc", &pm8921_vs_pc_ops, 0),
+ VREG_DESC(LVS5_PC, "8921_lvs5_pc", &pm8921_vs_pc_ops, 0),
+ VREG_DESC(LVS6_PC, "8921_lvs6_pc", &pm8921_vs_pc_ops, 0),
+ VREG_DESC(LVS7_PC, "8921_lvs7_pc", &pm8921_vs_pc_ops, 0),
+};
+
+static int pm8921_init_ldo(struct pm8921_vreg *vreg, bool is_real)
+{
+ int rc = 0;
+ int i;
+ u8 bank;
+
+ /* Save the current control register state. */
+ rc = pm8xxx_readb(vreg->dev->parent, vreg->ctrl_addr, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ /* Save the current test register state. */
+ for (i = 0; i < LDO_TEST_BANKS; i++) {
+ bank = REGULATOR_BANK_SEL(i);
+ rc = pm8xxx_writeb(vreg->dev->parent, vreg->test_addr, bank);
+ if (rc)
+ goto bail;
+
+ rc = pm8xxx_readb(vreg->dev->parent, vreg->test_addr,
+ &vreg->test_reg[i]);
+ if (rc)
+ goto bail;
+ vreg->test_reg[i] |= REGULATOR_BANK_WRITE;
+ }
+
+ if (is_real) {
+ /* Set pull down enable based on platform data. */
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ (vreg->pdata.pull_down_enable ? LDO_PULL_DOWN_ENABLE : 0),
+ LDO_PULL_DOWN_ENABLE_MASK, &vreg->ctrl_reg);
+
+ vreg->is_enabled = !!_pm8921_vreg_is_enabled(vreg);
+
+ vreg->mode = ((vreg->ctrl_reg & LDO_CTRL_PM_MASK)
+ == LDO_CTRL_PM_LPM ?
+ REGULATOR_MODE_IDLE : REGULATOR_MODE_NORMAL);
+ }
+bail:
+ if (rc)
+ vreg_err(vreg, "pm8xxx_readb/writeb failed, rc=%d\n", rc);
+
+ return rc;
+}
+
+static int pm8921_init_nldo1200(struct pm8921_vreg *vreg)
+{
+ int rc = 0;
+ int i;
+ u8 bank;
+
+ /* Save the current control register state. */
+ rc = pm8xxx_readb(vreg->dev->parent, vreg->ctrl_addr, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ /* Save the current test register state. */
+ for (i = 0; i < LDO_TEST_BANKS; i++) {
+ bank = REGULATOR_BANK_SEL(i);
+ rc = pm8xxx_writeb(vreg->dev->parent, vreg->test_addr, bank);
+ if (rc)
+ goto bail;
+
+ rc = pm8xxx_readb(vreg->dev->parent, vreg->test_addr,
+ &vreg->test_reg[i]);
+ if (rc)
+ goto bail;
+ vreg->test_reg[i] |= REGULATOR_BANK_WRITE;
+ }
+
+ vreg->save_uV = _pm8921_nldo1200_get_voltage(vreg);
+
+ /* Set pull down enable based on platform data. */
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ (vreg->pdata.pull_down_enable ? NLDO1200_PULL_DOWN_ENABLE : 0)
+ | REGULATOR_BANK_SEL(1) | REGULATOR_BANK_WRITE,
+ NLDO1200_PULL_DOWN_ENABLE_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[1]);
+
+bail:
+ if (rc)
+ vreg_err(vreg, "pm8xxx_readb/writeb failed, rc=%d\n", rc);
+
+ return rc;
+}
+
+static int pm8921_init_smps(struct pm8921_vreg *vreg, bool is_real)
+{
+ int rc = 0;
+ int i;
+ u8 bank;
+
+ /* Save the current control register state. */
+ rc = pm8xxx_readb(vreg->dev->parent, vreg->ctrl_addr, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ /* Save the current test2 register state. */
+ for (i = 0; i < SMPS_TEST_BANKS; i++) {
+ bank = REGULATOR_BANK_SEL(i);
+ rc = pm8xxx_writeb(vreg->dev->parent, vreg->test_addr, bank);
+ if (rc)
+ goto bail;
+
+ rc = pm8xxx_readb(vreg->dev->parent, vreg->test_addr,
+ &vreg->test_reg[i]);
+ if (rc)
+ goto bail;
+ vreg->test_reg[i] |= REGULATOR_BANK_WRITE;
+ }
+
+ /* Save the current clock control register state. */
+ rc = pm8xxx_readb(vreg->dev->parent, vreg->clk_ctrl_addr,
+ &vreg->clk_ctrl_reg);
+ if (rc)
+ goto bail;
+
+ /* Save the current sleep control register state. */
+ rc = pm8xxx_readb(vreg->dev->parent, vreg->sleep_ctrl_addr,
+ &vreg->sleep_ctrl_reg);
+ if (rc)
+ goto bail;
+
+ vreg->save_uV = _pm8921_smps_get_voltage(vreg);
+
+ if (is_real) {
+ /* Set advanced mode pull down enable based on platform data. */
+ rc = pm8921_vreg_masked_write(vreg, vreg->test_addr,
+ (vreg->pdata.pull_down_enable
+ ? SMPS_ADVANCED_PULL_DOWN_ENABLE : 0)
+ | REGULATOR_BANK_SEL(6) | REGULATOR_BANK_WRITE,
+ REGULATOR_BANK_MASK | SMPS_ADVANCED_PULL_DOWN_ENABLE,
+ &vreg->test_reg[6]);
+ if (rc)
+ goto bail;
+
+ vreg->is_enabled = !!_pm8921_vreg_is_enabled(vreg);
+
+ vreg->mode = ((vreg->clk_ctrl_reg & SMPS_CLK_CTRL_MASK)
+ == SMPS_CLK_CTRL_PFM ?
+ REGULATOR_MODE_IDLE : REGULATOR_MODE_NORMAL);
+ }
+
+ if (!SMPS_IN_ADVANCED_MODE(vreg) && is_real) {
+ /* Set legacy mode pull down enable based on platform data. */
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ (vreg->pdata.pull_down_enable
+ ? SMPS_LEGACY_PULL_DOWN_ENABLE : 0),
+ SMPS_LEGACY_PULL_DOWN_ENABLE, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+ }
+
+bail:
+ if (rc)
+ vreg_err(vreg, "pm8xxx_readb/writeb failed, rc=%d\n", rc);
+
+ return rc;
+}
+
+static int pm8921_init_ftsmps(struct pm8921_vreg *vreg)
+{
+ int rc, i;
+ u8 bank;
+
+ /* Save the current control register state. */
+ rc = pm8xxx_readb(vreg->dev->parent, vreg->ctrl_addr, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ /* Store current regulator register values. */
+ rc = pm8xxx_readb(vreg->dev->parent, vreg->pfm_ctrl_addr,
+ &vreg->pfm_ctrl_reg);
+ if (rc)
+ goto bail;
+
+ rc = pm8xxx_readb(vreg->dev->parent, vreg->pwr_cnfg_addr,
+ &vreg->pwr_cnfg_reg);
+ if (rc)
+ goto bail;
+
+ /* Save the current fts_cnfg1 register state (uses 'test' member). */
+ for (i = 0; i < SMPS_TEST_BANKS; i++) {
+ bank = REGULATOR_BANK_SEL(i);
+ rc = pm8xxx_writeb(vreg->dev->parent, vreg->test_addr, bank);
+ if (rc)
+ goto bail;
+
+ rc = pm8xxx_readb(vreg->dev->parent, vreg->test_addr,
+ &vreg->test_reg[i]);
+ if (rc)
+ goto bail;
+ vreg->test_reg[i] |= REGULATOR_BANK_WRITE;
+ }
+
+ vreg->save_uV = _pm8921_ftsmps_get_voltage(vreg);
+
+ /* Set pull down enable based on platform data. */
+ rc = pm8921_vreg_masked_write(vreg, vreg->pwr_cnfg_addr,
+ (vreg->pdata.pull_down_enable ? FTSMPS_PULL_DOWN_ENABLE : 0),
+ FTSMPS_PULL_DOWN_ENABLE_MASK, &vreg->pwr_cnfg_reg);
+
+bail:
+ if (rc)
+ vreg_err(vreg, "pm8xxx_readb/writeb failed, rc=%d\n", rc);
+
+ return rc;
+}
+
+static int pm8921_init_vs(struct pm8921_vreg *vreg, bool is_real)
+{
+ int rc = 0;
+
+ /* Save the current control register state. */
+ rc = pm8xxx_readb(vreg->dev->parent, vreg->ctrl_addr, &vreg->ctrl_reg);
+ if (rc) {
+ vreg_err(vreg, "pm8xxx_readb failed, rc=%d\n", rc);
+ return rc;
+ }
+
+ if (is_real) {
+ /* Set pull down enable based on platform data. */
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ (vreg->pdata.pull_down_enable ? VS_PULL_DOWN_ENABLE : 0),
+ VS_PULL_DOWN_ENABLE_MASK, &vreg->ctrl_reg);
+
+ if (rc)
+ vreg_err(vreg,
+ "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+
+ vreg->is_enabled = !!_pm8921_vreg_is_enabled(vreg);
+ }
+
+ return rc;
+}
+
+static int pm8921_init_vs300(struct pm8921_vreg *vreg)
+{
+ int rc;
+
+ /* Save the current control register state. */
+ rc = pm8xxx_readb(vreg->dev->parent, vreg->ctrl_addr, &vreg->ctrl_reg);
+ if (rc) {
+ vreg_err(vreg, "pm8xxx_readb failed, rc=%d\n", rc);
+ return rc;
+ }
+
+ /* Set pull down enable based on platform data. */
+ rc = pm8921_vreg_masked_write(vreg, vreg->ctrl_addr,
+ (vreg->pdata.pull_down_enable ? VS300_PULL_DOWN_ENABLE : 0),
+ VS300_PULL_DOWN_ENABLE_MASK, &vreg->ctrl_reg);
+
+ if (rc)
+ vreg_err(vreg, "pm8921_vreg_masked_write failed, rc=%d\n", rc);
+
+ return rc;
+}
+
+static int pm8921_init_ncp(struct pm8921_vreg *vreg)
+{
+ int rc;
+
+ /* Save the current control register state. */
+ rc = pm8xxx_readb(vreg->dev->parent, vreg->ctrl_addr, &vreg->ctrl_reg);
+ if (rc) {
+ vreg_err(vreg, "pm8xxx_readb failed, rc=%d\n", rc);
+ return rc;
+ }
+
+ return rc;
+}
+
+int pc_id_to_real_id(int id)
+{
+ int real_id;
+
+ if (id >= PM8921_VREG_ID_L1_PC && id <= PM8921_VREG_ID_L23_PC)
+ real_id = id - PM8921_VREG_ID_L1_PC;
+ else if (id >= PM8921_VREG_ID_L29_PC && id <= PM8921_VREG_ID_S4_PC)
+ real_id = id - PM8921_VREG_ID_L29_PC + PM8921_VREG_ID_L29;
+ else if (id >= PM8921_VREG_ID_S7_PC && id <= PM8921_VREG_ID_LVS1_PC)
+ real_id = id - PM8921_VREG_ID_S7_PC + PM8921_VREG_ID_S7;
+ else
+ real_id = id - PM8921_VREG_ID_LVS3_PC + PM8921_VREG_ID_LVS3;
+
+ return real_id;
+}
+
+static int __devinit pm8921_vreg_probe(struct platform_device *pdev)
+{
+ const struct pm8921_regulator_platform_data *pdata;
+ enum pm8921_vreg_pin_function pin_fn;
+ struct regulator_desc *rdesc;
+ struct pm8921_vreg *vreg;
+ const char *reg_name = "";
+ unsigned pin_ctrl;
+ int rc = 0, id = pdev->id;
+
+ if (pdev == NULL)
+ return -EINVAL;
+
+ if (pdev->id >= 0 && pdev->id < PM8921_VREG_ID_MAX) {
+ pdata = pdev->dev.platform_data;
+ rdesc = &pm8921_vreg_description[pdev->id];
+ if (!IS_REAL_REGULATOR(pdev->id))
+ id = pc_id_to_real_id(pdev->id);
+ vreg = &pm8921_vreg[id];
+ reg_name = pm8921_vreg_description[pdev->id].name;
+ if (!pdata) {
+ pr_err("%s requires platform data\n", reg_name);
+ return -EINVAL;
+ }
+
+ mutex_lock(&vreg->pc_lock);
+
+ if (IS_REAL_REGULATOR(pdev->id)) {
+ /* Do not modify pin control and pin function values. */
+ pin_ctrl = vreg->pdata.pin_ctrl;
+ pin_fn = vreg->pdata.pin_fn;
+ memcpy(&(vreg->pdata), pdata,
+ sizeof(struct pm8921_regulator_platform_data));
+ vreg->pdata.pin_ctrl = pin_ctrl;
+ vreg->pdata.pin_fn = pin_fn;
+ vreg->dev = &pdev->dev;
+ vreg->name = reg_name;
+ } else {
+ /* Pin control regulator */
+ if ((pdata->pin_ctrl &
+ (PM8921_VREG_PIN_CTRL_D1 | PM8921_VREG_PIN_CTRL_A0
+ | PM8921_VREG_PIN_CTRL_A1 | PM8921_VREG_PIN_CTRL_A2))
+ == PM8921_VREG_PIN_CTRL_NONE) {
+ pr_err("%s: no pin control input specified\n",
+ reg_name);
+ mutex_unlock(&vreg->pc_lock);
+ return -EINVAL;
+ }
+ vreg->pdata.pin_ctrl = pdata->pin_ctrl;
+ vreg->pdata.pin_fn = pdata->pin_fn;
+ vreg->dev_pc = &pdev->dev;
+ if (!vreg->dev)
+ vreg->dev = &pdev->dev;
+ if (!vreg->name)
+ vreg->name = reg_name;
+ }
+
+ /* Initialize register values. */
+ switch (vreg->type) {
+ case REGULATOR_TYPE_PLDO:
+ case REGULATOR_TYPE_NLDO:
+ rc = pm8921_init_ldo(vreg, IS_REAL_REGULATOR(pdev->id));
+ break;
+ case REGULATOR_TYPE_NLDO1200:
+ rc = pm8921_init_nldo1200(vreg);
+ break;
+ case REGULATOR_TYPE_SMPS:
+ rc = pm8921_init_smps(vreg,
+ IS_REAL_REGULATOR(pdev->id));
+ break;
+ case REGULATOR_TYPE_FTSMPS:
+ rc = pm8921_init_ftsmps(vreg);
+ break;
+ case REGULATOR_TYPE_VS:
+ rc = pm8921_init_vs(vreg, IS_REAL_REGULATOR(pdev->id));
+ break;
+ case REGULATOR_TYPE_VS300:
+ rc = pm8921_init_vs300(vreg);
+ break;
+ case REGULATOR_TYPE_NCP:
+ rc = pm8921_init_ncp(vreg);
+ break;
+ }
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ goto bail;
+
+ if (IS_REAL_REGULATOR(pdev->id)) {
+ vreg->rdev = regulator_register(rdesc, &pdev->dev,
+ &(pdata->init_data), vreg);
+ if (IS_ERR(vreg->rdev)) {
+ rc = PTR_ERR(vreg->rdev);
+ vreg->rdev = NULL;
+ pr_err("regulator_register failed: %s, rc=%d\n",
+ reg_name, rc);
+ }
+ } else {
+ vreg->rdev_pc = regulator_register(rdesc, &pdev->dev,
+ &(pdata->init_data), vreg);
+ if (IS_ERR(vreg->rdev_pc)) {
+ rc = PTR_ERR(vreg->rdev_pc);
+ vreg->rdev_pc = NULL;
+ pr_err("regulator_register failed: %s, rc=%d\n",
+ reg_name, rc);
+ }
+ }
+ if ((pm8921_vreg_debug_mask & PM8921_VREG_DEBUG_INIT) && !rc
+ && vreg->rdev)
+ pm8921_vreg_show_state(vreg->rdev,
+ PM8921_REGULATOR_ACTION_INIT);
+ } else {
+ rc = -ENODEV;
+ }
+
+bail:
+ if (rc)
+ pr_err("error for %s, rc=%d\n", reg_name, rc);
+
+ return rc;
+}
+
+static int __devexit pm8921_vreg_remove(struct platform_device *pdev)
+{
+ if (IS_REAL_REGULATOR(pdev->id))
+ regulator_unregister(pm8921_vreg[pdev->id].rdev);
+ else
+ regulator_unregister(
+ pm8921_vreg[pc_id_to_real_id(pdev->id)].rdev_pc);
+
+ return 0;
+}
+
+static struct platform_driver pm8921_vreg_driver = {
+ .probe = pm8921_vreg_probe,
+ .remove = __devexit_p(pm8921_vreg_remove),
+ .driver = {
+ .name = PM8921_REGULATOR_DEV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pm8921_vreg_init(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pm8921_vreg); i++) {
+ mutex_init(&pm8921_vreg[i].pc_lock);
+ pm8921_vreg[i].write_count = 0;
+ pm8921_vreg[i].prev_write_count = -1;
+ }
+
+ return platform_driver_register(&pm8921_vreg_driver);
+}
+postcore_initcall(pm8921_vreg_init);
+
+static void __exit pm8921_vreg_exit(void)
+{
+ int i;
+
+ platform_driver_unregister(&pm8921_vreg_driver);
+
+ for (i = 0; i < ARRAY_SIZE(pm8921_vreg); i++)
+ mutex_destroy(&pm8921_vreg[i].pc_lock);
+}
+module_exit(pm8921_vreg_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PMIC8921 regulator driver");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:" PM8921_REGULATOR_DEV_NAME);
diff --git a/drivers/regulator/pmic8058-regulator.c b/drivers/regulator/pmic8058-regulator.c
new file mode 100644
index 0000000..98ba163
--- /dev/null
+++ b/drivers/regulator/pmic8058-regulator.c
@@ -0,0 +1,1769 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/bitops.h>
+#include <linux/mfd/pmic8058.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/pmic8058-regulator.h>
+
+/* Regulator types */
+#define REGULATOR_TYPE_LDO 0
+#define REGULATOR_TYPE_SMPS 1
+#define REGULATOR_TYPE_LVS 2
+#define REGULATOR_TYPE_NCP 3
+
+/* Common masks */
+#define REGULATOR_EN_MASK 0x80
+
+#define REGULATOR_BANK_MASK 0xF0
+#define REGULATOR_BANK_SEL(n) ((n) << 4)
+#define REGULATOR_BANK_WRITE 0x80
+
+#define LDO_TEST_BANKS 7
+#define SMPS_TEST_BANKS 8
+#define REGULATOR_TEST_BANKS_MAX SMPS_TEST_BANKS
+
+/* LDO programming */
+
+/* CTRL register */
+#define LDO_ENABLE_MASK 0x80
+#define LDO_ENABLE 0x80
+#define LDO_PULL_DOWN_ENABLE_MASK 0x40
+#define LDO_PULL_DOWN_ENABLE 0x40
+
+#define LDO_CTRL_PM_MASK 0x20
+#define LDO_CTRL_PM_HPM 0x00
+#define LDO_CTRL_PM_LPM 0x20
+
+#define LDO_CTRL_VPROG_MASK 0x1F
+
+/* TEST register bank 0 */
+#define LDO_TEST_LPM_MASK 0x40
+#define LDO_TEST_LPM_SEL_CTRL 0x00
+#define LDO_TEST_LPM_SEL_TCXO 0x40
+
+/* TEST register bank 2 */
+#define LDO_TEST_VPROG_UPDATE_MASK 0x08
+#define LDO_TEST_RANGE_SEL_MASK 0x04
+#define LDO_TEST_FINE_STEP_MASK 0x02
+#define LDO_TEST_FINE_STEP_SHIFT 1
+
+/* TEST register bank 4 */
+#define LDO_TEST_RANGE_EXT_MASK 0x01
+
+/* TEST register bank 5 */
+#define LDO_TEST_PIN_CTRL_MASK 0x0F
+#define LDO_TEST_PIN_CTRL_EN3 0x08
+#define LDO_TEST_PIN_CTRL_EN2 0x04
+#define LDO_TEST_PIN_CTRL_EN1 0x02
+#define LDO_TEST_PIN_CTRL_EN0 0x01
+
+/* TEST register bank 6 */
+#define LDO_TEST_PIN_CTRL_LPM_MASK 0x0F
+
+/* Allowable voltage ranges */
+#define PLDO_LOW_UV_MIN 750000
+#define PLDO_LOW_UV_MAX 1537500
+#define PLDO_LOW_FINE_STEP_UV 12500
+
+#define PLDO_NORM_UV_MIN 1500000
+#define PLDO_NORM_UV_MAX 3075000
+#define PLDO_NORM_FINE_STEP_UV 25000
+
+#define PLDO_HIGH_UV_MIN 1750000
+#define PLDO_HIGH_UV_MAX 4900000
+#define PLDO_HIGH_FINE_STEP_UV 50000
+
+#define NLDO_UV_MIN 750000
+#define NLDO_UV_MAX 1537500
+#define NLDO_FINE_STEP_UV 12500
+
+/* SMPS masks and values */
+
+/* CTRL register */
+
+/* Legacy mode */
+#define SMPS_LEGACY_ENABLE 0x80
+#define SMPS_LEGACY_PULL_DOWN_ENABLE 0x40
+#define SMPS_LEGACY_VREF_SEL_MASK 0x20
+#define SMPS_LEGACY_VPROG_MASK 0x1F
+
+/* Advanced mode */
+#define SMPS_ADVANCED_BAND_MASK 0xC0
+#define SMPS_ADVANCED_BAND_OFF 0x00
+#define SMPS_ADVANCED_BAND_1 0x40
+#define SMPS_ADVANCED_BAND_2 0x80
+#define SMPS_ADVANCED_BAND_3 0xC0
+#define SMPS_ADVANCED_VPROG_MASK 0x3F
+
+/* Legacy mode voltage ranges */
+#define SMPS_MODE1_UV_MIN 1500000
+#define SMPS_MODE1_UV_MAX 3050000
+#define SMPS_MODE1_UV_STEP 50000
+
+#define SMPS_MODE2_UV_MIN 750000
+#define SMPS_MODE2_UV_MAX 1525000
+#define SMPS_MODE2_UV_STEP 25000
+
+#define SMPS_MODE3_UV_MIN 375000
+#define SMPS_MODE3_UV_MAX 1150000
+#define SMPS_MODE3_UV_STEP 25000
+
+/* Advanced mode voltage ranges */
+#define SMPS_BAND3_UV_MIN 1500000
+#define SMPS_BAND3_UV_MAX 3075000
+#define SMPS_BAND3_UV_STEP 25000
+
+#define SMPS_BAND2_UV_MIN 750000
+#define SMPS_BAND2_UV_MAX 1537500
+#define SMPS_BAND2_UV_STEP 12500
+
+#define SMPS_BAND1_UV_MIN 375000
+#define SMPS_BAND1_UV_MAX 1162500
+#define SMPS_BAND1_UV_STEP 12500
+
+#define SMPS_UV_MIN SMPS_MODE3_UV_MIN
+#define SMPS_UV_MAX SMPS_MODE1_UV_MAX
+
+/* Test2 register bank 1 */
+#define SMPS_LEGACY_VLOW_SEL_MASK 0x01
+
+/* Test2 register bank 6 */
+#define SMPS_ADVANCED_PULL_DOWN_ENABLE 0x08
+
+/* Test2 register bank 7 */
+#define SMPS_ADVANCED_MODE_MASK 0x02
+#define SMPS_ADVANCED_MODE 0x02
+#define SMPS_LEGACY_MODE 0x00
+
+#define SMPS_IN_ADVANCED_MODE(vreg) \
+ ((vreg->test_reg[7] & SMPS_ADVANCED_MODE_MASK) == SMPS_ADVANCED_MODE)
+
+/* BUCK_SLEEP_CNTRL register */
+#define SMPS_PIN_CTRL_MASK 0xF0
+#define SMPS_PIN_CTRL_A1 0x80
+#define SMPS_PIN_CTRL_A0 0x40
+#define SMPS_PIN_CTRL_D1 0x20
+#define SMPS_PIN_CTRL_D0 0x10
+
+#define SMPS_PIN_CTRL_LPM_MASK 0x0F
+#define SMPS_PIN_CTRL_LPM_A1 0x08
+#define SMPS_PIN_CTRL_LPM_A0 0x04
+#define SMPS_PIN_CTRL_LPM_D1 0x02
+#define SMPS_PIN_CTRL_LPM_D0 0x01
+
+/* BUCK_CLOCK_CNTRL register */
+#define SMPS_CLK_DIVIDE2 0x40
+
+#define SMPS_CLK_CTRL_MASK 0x30
+#define SMPS_CLK_CTRL_FOLLOW_TCXO 0x00
+#define SMPS_CLK_CTRL_PWM 0x10
+#define SMPS_CLK_CTRL_PFM 0x20
+
+/* LVS masks and values */
+
+/* CTRL register */
+#define LVS_ENABLE_MASK 0x80
+#define LVS_ENABLE 0x80
+#define LVS_PULL_DOWN_ENABLE_MASK 0x40
+#define LVS_PULL_DOWN_ENABLE 0x00
+#define LVS_PULL_DOWN_DISABLE 0x40
+
+#define LVS_PIN_CTRL_MASK 0x0F
+#define LVS_PIN_CTRL_EN0 0x08
+#define LVS_PIN_CTRL_EN1 0x04
+#define LVS_PIN_CTRL_EN2 0x02
+#define LVS_PIN_CTRL_EN3 0x01
+
+/* NCP masks and values */
+
+/* CTRL register */
+#define NCP_VPROG_MASK 0x1F
+
+#define NCP_UV_MIN 1500000
+#define NCP_UV_MAX 3050000
+#define NCP_UV_STEP 50000
+
+#define GLOBAL_ENABLE_MAX (2)
+struct pm8058_enable {
+ u16 addr;
+ u8 reg;
+};
+
+struct pm8058_vreg {
+ struct pm8058_vreg_pdata *pdata;
+ struct regulator_dev *rdev;
+ struct pm8058_enable *global_enable[GLOBAL_ENABLE_MAX];
+ int hpm_min_load;
+ int save_uV;
+ unsigned pc_vote;
+ unsigned optimum;
+ unsigned mode_initialized;
+ u16 ctrl_addr;
+ u16 test_addr;
+ u16 clk_ctrl_addr;
+ u16 sleep_ctrl_addr;
+ u8 type;
+ u8 ctrl_reg;
+ u8 test_reg[REGULATOR_TEST_BANKS_MAX];
+ u8 clk_ctrl_reg;
+ u8 sleep_ctrl_reg;
+ u8 is_nmos;
+ u8 global_enable_mask[GLOBAL_ENABLE_MAX];
+};
+
+#define LDO_M2(_id, _ctrl_addr, _test_addr, _is_nmos, _hpm_min_load, \
+ _en0, _en0_mask, _en1, _en1_mask) \
+ [PM8058_VREG_ID_##_id] = { \
+ .ctrl_addr = _ctrl_addr, \
+ .test_addr = _test_addr, \
+ .type = REGULATOR_TYPE_LDO, \
+ .hpm_min_load = PM8058_VREG_##_hpm_min_load##_HPM_MIN_LOAD, \
+ .is_nmos = _is_nmos, \
+ .global_enable = { \
+ [0] = _en0, \
+ [1] = _en1, \
+ }, \
+ .global_enable_mask = { \
+ [0] = _en0_mask, \
+ [1] = _en1_mask, \
+ }, \
+ }
+
+#define LDO(_id, _ctrl_addr, _test_addr, _is_nmos, _hpm_min_load, \
+ _en0, _en0_mask) \
+ LDO_M2(_id, _ctrl_addr, _test_addr, _is_nmos, _hpm_min_load, \
+ _en0, _en0_mask, NULL, 0)
+
+#define SMPS(_id, _ctrl_addr, _test_addr, _clk_ctrl_addr, _sleep_ctrl_addr, \
+ _hpm_min_load, _en0, _en0_mask) \
+ [PM8058_VREG_ID_##_id] = { \
+ .ctrl_addr = _ctrl_addr, \
+ .test_addr = _test_addr, \
+ .clk_ctrl_addr = _clk_ctrl_addr, \
+ .sleep_ctrl_addr = _sleep_ctrl_addr, \
+ .type = REGULATOR_TYPE_SMPS, \
+ .hpm_min_load = PM8058_VREG_##_hpm_min_load##_HPM_MIN_LOAD, \
+ .global_enable = { \
+ [0] = _en0, \
+ [1] = NULL, \
+ }, \
+ .global_enable_mask = { \
+ [0] = _en0_mask, \
+ [1] = 0, \
+ }, \
+ }
+
+#define LVS(_id, _ctrl_addr, _en0, _en0_mask) \
+ [PM8058_VREG_ID_##_id] = { \
+ .ctrl_addr = _ctrl_addr, \
+ .type = REGULATOR_TYPE_LVS, \
+ .global_enable = { \
+ [0] = _en0, \
+ [1] = NULL, \
+ }, \
+ .global_enable_mask = { \
+ [0] = _en0_mask, \
+ [1] = 0, \
+ }, \
+ }
+
+#define NCP(_id, _ctrl_addr, _test1) \
+ [PM8058_VREG_ID_##_id] = { \
+ .ctrl_addr = _ctrl_addr, \
+ .type = REGULATOR_TYPE_NCP, \
+ .test_addr = _test1, \
+ .global_enable = { \
+ [0] = NULL, \
+ [1] = NULL, \
+ }, \
+ .global_enable_mask = { \
+ [0] = 0, \
+ [1] = 0, \
+ }, \
+ }
+
+#define MASTER_ENABLE_COUNT 6
+
+#define EN_MSM 0
+#define EN_PH 1
+#define EN_RF 2
+#define EN_GRP_5_4 3
+#define EN_GRP_3_2 4
+#define EN_GRP_1_0 5
+
+/* Master regulator control registers */
+static struct pm8058_enable m_en[MASTER_ENABLE_COUNT] = {
+ [EN_MSM] = {
+ .addr = 0x018, /* VREG_EN_MSM */
+ },
+ [EN_PH] = {
+ .addr = 0x019, /* VREG_EN_PH */
+ },
+ [EN_RF] = {
+ .addr = 0x01A, /* VREG_EN_RF */
+ },
+ [EN_GRP_5_4] = {
+ .addr = 0x1C8, /* VREG_EN_MSM_GRP_5-4 */
+ },
+ [EN_GRP_3_2] = {
+ .addr = 0x1C9, /* VREG_EN_MSM_GRP_3-2 */
+ },
+ [EN_GRP_1_0] = {
+ .addr = 0x1CA, /* VREG_EN_MSM_GRP_1-0 */
+ },
+};
+
+
+static struct pm8058_vreg pm8058_vreg[] = {
+ /* id ctrl test n/p hpm_min m_en m_en_mask */
+ LDO(L0, 0x009, 0x065, 1, LDO_150, &m_en[EN_GRP_5_4], BIT(3)),
+ LDO(L1, 0x00A, 0x066, 1, LDO_300, &m_en[EN_GRP_5_4], BIT(6) | BIT(2)),
+ LDO(L2, 0x00B, 0x067, 0, LDO_300, &m_en[EN_GRP_3_2], BIT(2)),
+ LDO(L3, 0x00C, 0x068, 0, LDO_150, &m_en[EN_GRP_1_0], BIT(1)),
+ LDO(L4, 0x00D, 0x069, 0, LDO_50, &m_en[EN_MSM], 0),
+ LDO(L5, 0x00E, 0x06A, 0, LDO_300, &m_en[EN_GRP_1_0], BIT(7)),
+ LDO(L6, 0x00F, 0x06B, 0, LDO_50, &m_en[EN_GRP_1_0], BIT(2)),
+ LDO(L7, 0x010, 0x06C, 0, LDO_50, &m_en[EN_GRP_3_2], BIT(3)),
+ LDO(L8, 0x011, 0x06D, 0, LDO_300, &m_en[EN_PH], BIT(7)),
+ LDO(L9, 0x012, 0x06E, 0, LDO_300, &m_en[EN_GRP_1_0], BIT(3)),
+ LDO(L10, 0x013, 0x06F, 0, LDO_300, &m_en[EN_GRP_3_2], BIT(4)),
+ LDO(L11, 0x014, 0x070, 0, LDO_150, &m_en[EN_PH], BIT(4)),
+ LDO(L12, 0x015, 0x071, 0, LDO_150, &m_en[EN_PH], BIT(3)),
+ LDO(L13, 0x016, 0x072, 0, LDO_300, &m_en[EN_GRP_3_2], BIT(1)),
+ LDO(L14, 0x017, 0x073, 0, LDO_300, &m_en[EN_GRP_1_0], BIT(5)),
+ LDO(L15, 0x089, 0x0E5, 0, LDO_300, &m_en[EN_GRP_1_0], BIT(4)),
+ LDO(L16, 0x08A, 0x0E6, 0, LDO_300, &m_en[EN_GRP_3_2], BIT(0)),
+ LDO(L17, 0x08B, 0x0E7, 0, LDO_150, &m_en[EN_RF], BIT(7)),
+ LDO(L18, 0x11D, 0x125, 0, LDO_150, &m_en[EN_RF], BIT(6)),
+ LDO(L19, 0x11E, 0x126, 0, LDO_150, &m_en[EN_RF], BIT(5)),
+ LDO(L20, 0x11F, 0x127, 0, LDO_150, &m_en[EN_RF], BIT(4)),
+ LDO_M2(L21, 0x120, 0x128, 1, LDO_150, &m_en[EN_GRP_5_4], BIT(1),
+ &m_en[EN_GRP_1_0], BIT(6)),
+ LDO(L22, 0x121, 0x129, 1, LDO_300, &m_en[EN_GRP_3_2], BIT(7)),
+ LDO(L23, 0x122, 0x12A, 1, LDO_300, &m_en[EN_GRP_5_4], BIT(0)),
+ LDO(L24, 0x123, 0x12B, 1, LDO_150, &m_en[EN_RF], BIT(3)),
+ LDO(L25, 0x124, 0x12C, 1, LDO_150, &m_en[EN_RF], BIT(2)),
+
+ /* id ctrl test2 clk sleep hpm_min m_en m_en_mask */
+ SMPS(S0, 0x004, 0x084, 0x1D1, 0x1D8, SMPS, &m_en[EN_MSM], BIT(7)),
+ SMPS(S1, 0x005, 0x085, 0x1D2, 0x1DB, SMPS, &m_en[EN_MSM], BIT(6)),
+ SMPS(S2, 0x110, 0x119, 0x1D3, 0x1DE, SMPS, &m_en[EN_GRP_5_4], BIT(5)),
+ SMPS(S3, 0x111, 0x11A, 0x1D4, 0x1E1, SMPS, &m_en[EN_GRP_5_4],
+ BIT(7) | BIT(4)),
+ SMPS(S4, 0x112, 0x11B, 0x1D5, 0x1E4, SMPS, &m_en[EN_GRP_3_2], BIT(5)),
+
+ /* id ctrl m_en m_en_mask */
+ LVS(LVS0, 0x12D, &m_en[EN_RF], BIT(1)),
+ LVS(LVS1, 0x12F, &m_en[EN_GRP_1_0], BIT(0)),
+
+ /* id ctrl test1 */
+ NCP(NCP, 0x090, 0x0EC),
+};
+
+static int pm8058_smps_set_voltage_advanced(struct pm8058_vreg *vreg,
+ struct pm8058_chip *chip, int uV,
+ int force_on);
+static int pm8058_smps_set_voltage_legacy(struct pm8058_vreg *vreg,
+ struct pm8058_chip *chip, int uV);
+static int _pm8058_vreg_is_enabled(struct pm8058_vreg *vreg);
+
+static unsigned int pm8058_vreg_get_mode(struct regulator_dev *dev);
+
+static void print_write_error(struct pm8058_vreg *vreg, int rc,
+ const char *func);
+
+static int pm8058_vreg_write(struct pm8058_chip *chip,
+ u16 addr, u8 val, u8 mask, u8 *reg_save)
+{
+ int rc = 0;
+ u8 reg;
+
+ reg = (*reg_save & ~mask) | (val & mask);
+ if (reg != *reg_save)
+ rc = pm8058_write(chip, addr, ®, 1);
+ if (rc)
+ pr_err("%s: pm8058_write failed, rc=%d\n", __func__, rc);
+ else
+ *reg_save = reg;
+ return rc;
+}
+
+static int pm8058_vreg_is_global_enabled(struct pm8058_vreg *vreg)
+{
+ int ret = 0, i;
+
+ for (i = 0;
+ (i < GLOBAL_ENABLE_MAX) && !ret && vreg->global_enable[i]; i++)
+ ret = vreg->global_enable[i]->reg &
+ vreg->global_enable_mask[i];
+
+ return ret;
+}
+
+
+static int pm8058_vreg_set_global_enable(struct pm8058_vreg *vreg,
+ struct pm8058_chip *chip, int on)
+{
+ int rc = 0, i;
+
+ for (i = 0;
+ (i < GLOBAL_ENABLE_MAX) && !rc && vreg->global_enable[i]; i++)
+ rc = pm8058_vreg_write(chip, vreg->global_enable[i]->addr,
+ (on ? vreg->global_enable_mask[i] : 0),
+ vreg->global_enable_mask[i],
+ &vreg->global_enable[i]->reg);
+
+ return rc;
+}
+
+static int pm8058_vreg_using_pin_ctrl(struct pm8058_vreg *vreg)
+{
+ int ret = 0;
+
+ switch (vreg->type) {
+ case REGULATOR_TYPE_LDO:
+ ret = ((vreg->test_reg[5] & LDO_TEST_PIN_CTRL_MASK) << 4)
+ | (vreg->test_reg[6] & LDO_TEST_PIN_CTRL_LPM_MASK);
+ break;
+ case REGULATOR_TYPE_SMPS:
+ ret = vreg->sleep_ctrl_reg
+ & (SMPS_PIN_CTRL_MASK | SMPS_PIN_CTRL_LPM_MASK);
+ break;
+ case REGULATOR_TYPE_LVS:
+ ret = vreg->ctrl_reg & LVS_PIN_CTRL_MASK;
+ break;
+ }
+
+ return ret;
+}
+
+static int pm8058_vreg_set_pin_ctrl(struct pm8058_vreg *vreg,
+ struct pm8058_chip *chip, int on)
+{
+ int rc = 0, bank;
+ u8 val = 0, mask;
+ unsigned pc = vreg->pdata->pin_ctrl;
+ unsigned pf = vreg->pdata->pin_fn;
+
+ switch (vreg->type) {
+ case REGULATOR_TYPE_LDO:
+ if (on) {
+ if (pc & PM8058_VREG_PIN_CTRL_D0)
+ val |= LDO_TEST_PIN_CTRL_EN0;
+ if (pc & PM8058_VREG_PIN_CTRL_D1)
+ val |= LDO_TEST_PIN_CTRL_EN1;
+ if (pc & PM8058_VREG_PIN_CTRL_A0)
+ val |= LDO_TEST_PIN_CTRL_EN2;
+ if (pc & PM8058_VREG_PIN_CTRL_A1)
+ val |= LDO_TEST_PIN_CTRL_EN3;
+
+ bank = (pf == PM8058_VREG_PIN_FN_ENABLE ? 5 : 6);
+ rc = pm8058_vreg_write(chip, vreg->test_addr,
+ val | REGULATOR_BANK_SEL(bank)
+ | REGULATOR_BANK_WRITE,
+ LDO_TEST_PIN_CTRL_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[bank]);
+ if (rc)
+ goto bail;
+
+ val = LDO_TEST_LPM_SEL_CTRL | REGULATOR_BANK_WRITE
+ | REGULATOR_BANK_SEL(0);
+ mask = LDO_TEST_LPM_MASK | REGULATOR_BANK_MASK;
+ rc = pm8058_vreg_write(chip, vreg->test_addr, val, mask,
+ &vreg->test_reg[0]);
+ if (rc)
+ goto bail;
+
+ if (pf == PM8058_VREG_PIN_FN_ENABLE) {
+ /* Pin control ON/OFF */
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr,
+ LDO_CTRL_PM_HPM,
+ LDO_ENABLE_MASK | LDO_CTRL_PM_MASK,
+ &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+ rc = pm8058_vreg_set_global_enable(vreg, chip,
+ 0);
+ if (rc)
+ goto bail;
+ } else {
+ /* Pin control LPM/HPM */
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr,
+ LDO_ENABLE | LDO_CTRL_PM_LPM,
+ LDO_ENABLE_MASK | LDO_CTRL_PM_MASK,
+ &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+ }
+ } else {
+ /* Pin control off */
+ rc = pm8058_vreg_write(chip, vreg->test_addr,
+ REGULATOR_BANK_SEL(5) | REGULATOR_BANK_WRITE,
+ LDO_TEST_PIN_CTRL_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[5]);
+ if (rc)
+ goto bail;
+
+ rc = pm8058_vreg_write(chip, vreg->test_addr,
+ REGULATOR_BANK_SEL(6) | REGULATOR_BANK_WRITE,
+ LDO_TEST_PIN_CTRL_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[6]);
+ if (rc)
+ goto bail;
+ }
+ break;
+
+ case REGULATOR_TYPE_SMPS:
+ if (on) {
+ if (pf == PM8058_VREG_PIN_FN_ENABLE) {
+ /* Pin control ON/OFF */
+ if (pc & PM8058_VREG_PIN_CTRL_D0)
+ val |= SMPS_PIN_CTRL_D0;
+ if (pc & PM8058_VREG_PIN_CTRL_D1)
+ val |= SMPS_PIN_CTRL_D1;
+ if (pc & PM8058_VREG_PIN_CTRL_A0)
+ val |= SMPS_PIN_CTRL_A0;
+ if (pc & PM8058_VREG_PIN_CTRL_A1)
+ val |= SMPS_PIN_CTRL_A1;
+ } else {
+ /* Pin control LPM/HPM */
+ if (pc & PM8058_VREG_PIN_CTRL_D0)
+ val |= SMPS_PIN_CTRL_LPM_D0;
+ if (pc & PM8058_VREG_PIN_CTRL_D1)
+ val |= SMPS_PIN_CTRL_LPM_D1;
+ if (pc & PM8058_VREG_PIN_CTRL_A0)
+ val |= SMPS_PIN_CTRL_LPM_A0;
+ if (pc & PM8058_VREG_PIN_CTRL_A1)
+ val |= SMPS_PIN_CTRL_LPM_A1;
+ }
+ rc = pm8058_vreg_set_global_enable(vreg, chip, 0);
+ if (rc)
+ goto bail;
+
+ rc = pm8058_smps_set_voltage_legacy(vreg, chip,
+ vreg->save_uV);
+ if (rc)
+ goto bail;
+
+ rc = pm8058_vreg_write(chip, vreg->sleep_ctrl_addr, val,
+ SMPS_PIN_CTRL_MASK | SMPS_PIN_CTRL_LPM_MASK,
+ &vreg->sleep_ctrl_reg);
+ if (rc)
+ goto bail;
+
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr,
+ (pf == PM8058_VREG_PIN_FN_ENABLE
+ ? 0 : SMPS_LEGACY_ENABLE),
+ SMPS_LEGACY_ENABLE, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ rc = pm8058_vreg_write(chip, vreg->clk_ctrl_addr,
+ (pf == PM8058_VREG_PIN_FN_ENABLE
+ ? SMPS_CLK_CTRL_PWM : SMPS_CLK_CTRL_PFM),
+ SMPS_CLK_CTRL_MASK, &vreg->clk_ctrl_reg);
+ if (rc)
+ goto bail;
+ } else {
+ /* Pin control off */
+ if (!SMPS_IN_ADVANCED_MODE(vreg)) {
+ if (_pm8058_vreg_is_enabled(vreg))
+ val = SMPS_LEGACY_ENABLE;
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr,
+ val, SMPS_LEGACY_ENABLE,
+ &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+ }
+
+ rc = pm8058_vreg_write(chip, vreg->sleep_ctrl_addr, 0,
+ SMPS_PIN_CTRL_MASK | SMPS_PIN_CTRL_LPM_MASK,
+ &vreg->sleep_ctrl_reg);
+ if (rc)
+ goto bail;
+
+ rc = pm8058_smps_set_voltage_advanced(vreg, chip,
+ vreg->save_uV, 0);
+ if (rc)
+ goto bail;
+ }
+ break;
+
+ case REGULATOR_TYPE_LVS:
+ if (on) {
+ if (pc & PM8058_VREG_PIN_CTRL_D0)
+ val |= LVS_PIN_CTRL_EN0;
+ if (pc & PM8058_VREG_PIN_CTRL_D1)
+ val |= LVS_PIN_CTRL_EN1;
+ if (pc & PM8058_VREG_PIN_CTRL_A0)
+ val |= LVS_PIN_CTRL_EN2;
+ if (pc & PM8058_VREG_PIN_CTRL_A1)
+ val |= LVS_PIN_CTRL_EN3;
+
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr, val,
+ LVS_PIN_CTRL_MASK | LVS_ENABLE_MASK,
+ &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ rc = pm8058_vreg_set_global_enable(vreg, chip, 0);
+ if (rc)
+ goto bail;
+ } else {
+ /* Pin control off */
+ if (_pm8058_vreg_is_enabled(vreg))
+ val = LVS_ENABLE;
+
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr, val,
+ LVS_ENABLE_MASK | LVS_PIN_CTRL_MASK,
+ &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ }
+ break;
+ }
+
+bail:
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+static int pm8058_vreg_enable(struct regulator_dev *dev)
+{
+ struct pm8058_vreg *vreg = rdev_get_drvdata(dev);
+ struct pm8058_chip *chip = dev_get_drvdata(dev->dev.parent);
+ int mode;
+ int rc = 0;
+
+ mode = pm8058_vreg_get_mode(dev);
+
+ if (mode == REGULATOR_MODE_IDLE) {
+ /* Turn on pin control. */
+ rc = pm8058_vreg_set_pin_ctrl(vreg, chip, 1);
+ if (rc)
+ goto bail;
+ return rc;
+ }
+ if (vreg->type == REGULATOR_TYPE_SMPS && SMPS_IN_ADVANCED_MODE(vreg))
+ rc = pm8058_smps_set_voltage_advanced(vreg, chip,
+ vreg->save_uV, 1);
+ else
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr, REGULATOR_EN_MASK,
+ REGULATOR_EN_MASK, &vreg->ctrl_reg);
+bail:
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+static int _pm8058_vreg_is_enabled(struct pm8058_vreg *vreg)
+{
+ /*
+ * All regulator types except advanced mode SMPS have enable bit in
+ * bit 7 of the control register. Global enable and pin control also
+ * do not work for advanced mode SMPS.
+ */
+ if (!(vreg->type == REGULATOR_TYPE_SMPS && SMPS_IN_ADVANCED_MODE(vreg))
+ && ((vreg->ctrl_reg & REGULATOR_EN_MASK)
+ || pm8058_vreg_is_global_enabled(vreg)
+ || pm8058_vreg_using_pin_ctrl(vreg)))
+ return 1;
+ else if (vreg->type == REGULATOR_TYPE_SMPS
+ && SMPS_IN_ADVANCED_MODE(vreg)
+ && ((vreg->ctrl_reg & SMPS_ADVANCED_BAND_MASK)
+ != SMPS_ADVANCED_BAND_OFF))
+ return 1;
+
+ return 0;
+}
+
+static int pm8058_vreg_is_enabled(struct regulator_dev *dev)
+{
+ struct pm8058_vreg *vreg = rdev_get_drvdata(dev);
+
+ return _pm8058_vreg_is_enabled(vreg);
+}
+
+static int pm8058_vreg_disable(struct regulator_dev *dev)
+{
+ struct pm8058_vreg *vreg = rdev_get_drvdata(dev);
+ struct pm8058_chip *chip = dev_get_drvdata(dev->dev.parent);
+ int rc = 0;
+
+ /* Disable in global control register. */
+ rc = pm8058_vreg_set_global_enable(vreg, chip, 0);
+ if (rc)
+ goto bail;
+
+ /* Turn off pin control. */
+ rc = pm8058_vreg_set_pin_ctrl(vreg, chip, 0);
+ if (rc)
+ goto bail;
+
+ /* Disable in local control register. */
+ if (vreg->type == REGULATOR_TYPE_SMPS && SMPS_IN_ADVANCED_MODE(vreg))
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr,
+ SMPS_ADVANCED_BAND_OFF, SMPS_ADVANCED_BAND_MASK,
+ &vreg->ctrl_reg);
+ else
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr, 0,
+ REGULATOR_EN_MASK, &vreg->ctrl_reg);
+
+bail:
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+static int pm8058_pldo_set_voltage(struct pm8058_chip *chip,
+ struct pm8058_vreg *vreg, int uV)
+{
+ int vmin, rc = 0;
+ unsigned vprog, fine_step;
+ u8 range_ext, range_sel, fine_step_reg;
+
+ if (uV < PLDO_LOW_UV_MIN || uV > PLDO_HIGH_UV_MAX)
+ return -EINVAL;
+
+ if (uV < PLDO_LOW_UV_MAX + PLDO_LOW_FINE_STEP_UV) {
+ vmin = PLDO_LOW_UV_MIN;
+ fine_step = PLDO_LOW_FINE_STEP_UV;
+ range_ext = 0;
+ range_sel = LDO_TEST_RANGE_SEL_MASK;
+ } else if (uV < PLDO_NORM_UV_MAX + PLDO_NORM_FINE_STEP_UV) {
+ vmin = PLDO_NORM_UV_MIN;
+ fine_step = PLDO_NORM_FINE_STEP_UV;
+ range_ext = 0;
+ range_sel = 0;
+ } else {
+ vmin = PLDO_HIGH_UV_MIN;
+ fine_step = PLDO_HIGH_FINE_STEP_UV;
+ range_ext = LDO_TEST_RANGE_EXT_MASK;
+ range_sel = 0;
+ }
+
+ vprog = (uV - vmin) / fine_step;
+ fine_step_reg = (vprog & 1) << LDO_TEST_FINE_STEP_SHIFT;
+ vprog >>= 1;
+
+ /*
+ * Disable program voltage update if range extension, range select,
+ * or fine step have changed and the regulator is enabled.
+ */
+ if (_pm8058_vreg_is_enabled(vreg) &&
+ (((range_ext ^ vreg->test_reg[4]) & LDO_TEST_RANGE_EXT_MASK)
+ || ((range_sel ^ vreg->test_reg[2]) & LDO_TEST_RANGE_SEL_MASK)
+ || ((fine_step_reg ^ vreg->test_reg[2])
+ & LDO_TEST_FINE_STEP_MASK))) {
+ rc = pm8058_vreg_write(chip, vreg->test_addr,
+ REGULATOR_BANK_SEL(2) | REGULATOR_BANK_WRITE,
+ REGULATOR_BANK_MASK | LDO_TEST_VPROG_UPDATE_MASK,
+ &vreg->test_reg[2]);
+ if (rc)
+ goto bail;
+ }
+
+ /* Write new voltage. */
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr, vprog,
+ LDO_CTRL_VPROG_MASK, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ /* Write range extension. */
+ rc = pm8058_vreg_write(chip, vreg->test_addr,
+ range_ext | REGULATOR_BANK_SEL(4)
+ | REGULATOR_BANK_WRITE,
+ LDO_TEST_RANGE_EXT_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[4]);
+ if (rc)
+ goto bail;
+
+ /* Write fine step, range select and program voltage update. */
+ rc = pm8058_vreg_write(chip, vreg->test_addr,
+ fine_step_reg | range_sel | REGULATOR_BANK_SEL(2)
+ | REGULATOR_BANK_WRITE | LDO_TEST_VPROG_UPDATE_MASK,
+ LDO_TEST_FINE_STEP_MASK | LDO_TEST_RANGE_SEL_MASK
+ | REGULATOR_BANK_MASK | LDO_TEST_VPROG_UPDATE_MASK,
+ &vreg->test_reg[2]);
+bail:
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+static int pm8058_nldo_set_voltage(struct pm8058_chip *chip,
+ struct pm8058_vreg *vreg, int uV)
+{
+ unsigned vprog, fine_step_reg;
+ int rc;
+
+ if (uV < NLDO_UV_MIN || uV > NLDO_UV_MAX)
+ return -EINVAL;
+
+ vprog = (uV - NLDO_UV_MIN) / NLDO_FINE_STEP_UV;
+ fine_step_reg = (vprog & 1) << LDO_TEST_FINE_STEP_SHIFT;
+ vprog >>= 1;
+
+ /* Write new voltage. */
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr, vprog,
+ LDO_CTRL_VPROG_MASK, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ /* Write fine step. */
+ rc = pm8058_vreg_write(chip, vreg->test_addr,
+ fine_step_reg | REGULATOR_BANK_SEL(2)
+ | REGULATOR_BANK_WRITE | LDO_TEST_VPROG_UPDATE_MASK,
+ LDO_TEST_FINE_STEP_MASK | REGULATOR_BANK_MASK
+ | LDO_TEST_VPROG_UPDATE_MASK,
+ &vreg->test_reg[2]);
+bail:
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+static int pm8058_ldo_set_voltage(struct regulator_dev *dev,
+ int min_uV, int max_uV, unsigned *selector)
+{
+ struct pm8058_vreg *vreg = rdev_get_drvdata(dev);
+ struct pm8058_chip *chip = dev_get_drvdata(dev->dev.parent);
+
+ if (vreg->is_nmos)
+ return pm8058_nldo_set_voltage(chip, vreg, min_uV);
+ else
+ return pm8058_pldo_set_voltage(chip, vreg, min_uV);
+}
+
+static int pm8058_pldo_get_voltage(struct pm8058_vreg *vreg)
+{
+ int vmin, fine_step;
+ u8 range_ext, range_sel, vprog, fine_step_reg;
+
+ fine_step_reg = vreg->test_reg[2] & LDO_TEST_FINE_STEP_MASK;
+ range_sel = vreg->test_reg[2] & LDO_TEST_RANGE_SEL_MASK;
+ range_ext = vreg->test_reg[4] & LDO_TEST_RANGE_EXT_MASK;
+ vprog = vreg->ctrl_reg & LDO_CTRL_VPROG_MASK;
+
+ vprog = (vprog << 1) | (fine_step_reg >> LDO_TEST_FINE_STEP_SHIFT);
+
+ if (range_sel) {
+ /* low range mode */
+ fine_step = PLDO_LOW_FINE_STEP_UV;
+ vmin = PLDO_LOW_UV_MIN;
+ } else if (!range_ext) {
+ /* normal mode */
+ fine_step = PLDO_NORM_FINE_STEP_UV;
+ vmin = PLDO_NORM_UV_MIN;
+ } else {
+ /* high range mode */
+ fine_step = PLDO_HIGH_FINE_STEP_UV;
+ vmin = PLDO_HIGH_UV_MIN;
+ }
+
+ return fine_step * vprog + vmin;
+}
+
+static int pm8058_nldo_get_voltage(struct pm8058_vreg *vreg)
+{
+ u8 vprog, fine_step_reg;
+
+ fine_step_reg = vreg->test_reg[2] & LDO_TEST_FINE_STEP_MASK;
+ vprog = vreg->ctrl_reg & LDO_CTRL_VPROG_MASK;
+
+ vprog = (vprog << 1) | (fine_step_reg >> LDO_TEST_FINE_STEP_SHIFT);
+
+ return NLDO_FINE_STEP_UV * vprog + NLDO_UV_MIN;
+}
+
+static int pm8058_ldo_get_voltage(struct regulator_dev *dev)
+{
+ struct pm8058_vreg *vreg = rdev_get_drvdata(dev);
+
+ if (vreg->is_nmos)
+ return pm8058_nldo_get_voltage(vreg);
+ else
+ return pm8058_pldo_get_voltage(vreg);
+}
+
+static int pm8058_smps_get_voltage_advanced(struct pm8058_vreg *vreg)
+{
+ u8 vprog, band;
+ int uV = 0;
+
+ vprog = vreg->ctrl_reg & SMPS_ADVANCED_VPROG_MASK;
+ band = vreg->ctrl_reg & SMPS_ADVANCED_BAND_MASK;
+
+ if (band == SMPS_ADVANCED_BAND_1)
+ uV = vprog * SMPS_BAND1_UV_STEP + SMPS_BAND1_UV_MIN;
+ else if (band == SMPS_ADVANCED_BAND_2)
+ uV = vprog * SMPS_BAND2_UV_STEP + SMPS_BAND2_UV_MIN;
+ else if (band == SMPS_ADVANCED_BAND_3)
+ uV = vprog * SMPS_BAND3_UV_STEP + SMPS_BAND3_UV_MIN;
+ else
+ uV = vreg->save_uV;
+
+ return uV;
+}
+
+static int pm8058_smps_get_voltage_legacy(struct pm8058_vreg *vreg)
+{
+ u8 vlow, vref, vprog;
+ int uV;
+
+ vlow = vreg->test_reg[1] & SMPS_LEGACY_VLOW_SEL_MASK;
+ vref = vreg->ctrl_reg & SMPS_LEGACY_VREF_SEL_MASK;
+ vprog = vreg->ctrl_reg & SMPS_LEGACY_VPROG_MASK;
+
+ if (vlow && vref) {
+ /* mode 3 */
+ uV = vprog * SMPS_MODE3_UV_STEP + SMPS_MODE3_UV_MIN;
+ } else if (vref) {
+ /* mode 2 */
+ uV = vprog * SMPS_MODE2_UV_STEP + SMPS_MODE2_UV_MIN;
+ } else {
+ /* mode 1 */
+ uV = vprog * SMPS_MODE1_UV_STEP + SMPS_MODE1_UV_MIN;
+ }
+
+ return uV;
+}
+
+static int _pm8058_smps_get_voltage(struct pm8058_vreg *vreg)
+{
+ if (SMPS_IN_ADVANCED_MODE(vreg))
+ return pm8058_smps_get_voltage_advanced(vreg);
+
+ return pm8058_smps_get_voltage_legacy(vreg);
+}
+
+static int pm8058_smps_get_voltage(struct regulator_dev *dev)
+{
+ struct pm8058_vreg *vreg = rdev_get_drvdata(dev);
+
+ return _pm8058_smps_get_voltage(vreg);
+}
+
+static int pm8058_smps_set_voltage_advanced(struct pm8058_vreg *vreg,
+ struct pm8058_chip *chip, int uV,
+ int force_on)
+{
+ u8 vprog, band;
+ int rc, new_uV;
+
+ if (uV < SMPS_BAND1_UV_MAX + SMPS_BAND1_UV_STEP) {
+ vprog = ((uV - SMPS_BAND1_UV_MIN) / SMPS_BAND1_UV_STEP);
+ band = SMPS_ADVANCED_BAND_1;
+ new_uV = SMPS_BAND1_UV_MIN + vprog * SMPS_BAND1_UV_STEP;
+ } else if (uV < SMPS_BAND2_UV_MAX + SMPS_BAND2_UV_STEP) {
+ vprog = ((uV - SMPS_BAND2_UV_MIN) / SMPS_BAND2_UV_STEP);
+ band = SMPS_ADVANCED_BAND_2;
+ new_uV = SMPS_BAND2_UV_MIN + vprog * SMPS_BAND2_UV_STEP;
+ } else {
+ vprog = ((uV - SMPS_BAND3_UV_MIN) / SMPS_BAND3_UV_STEP);
+ band = SMPS_ADVANCED_BAND_3;
+ new_uV = SMPS_BAND3_UV_MIN + vprog * SMPS_BAND3_UV_STEP;
+ }
+
+ /* Do not set band if regulator currently disabled. */
+ if (!_pm8058_vreg_is_enabled(vreg) && !force_on)
+ band = SMPS_ADVANCED_BAND_OFF;
+
+ /* Set advanced mode bit to 1. */
+ rc = pm8058_vreg_write(chip, vreg->test_addr, SMPS_ADVANCED_MODE
+ | REGULATOR_BANK_WRITE | REGULATOR_BANK_SEL(7),
+ SMPS_ADVANCED_MODE_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[7]);
+ if (rc)
+ goto bail;
+
+ /* Set voltage and voltage band. */
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr, band | vprog,
+ SMPS_ADVANCED_BAND_MASK | SMPS_ADVANCED_VPROG_MASK,
+ &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ vreg->save_uV = new_uV;
+
+bail:
+ return rc;
+}
+
+static int pm8058_smps_set_voltage_legacy(struct pm8058_vreg *vreg,
+ struct pm8058_chip *chip, int uV)
+{
+ u8 vlow, vref, vprog, pd, en;
+ int rc;
+
+ if (uV < SMPS_MODE3_UV_MAX + SMPS_MODE3_UV_STEP) {
+ vprog = ((uV - SMPS_MODE3_UV_MIN) / SMPS_MODE3_UV_STEP);
+ vref = SMPS_LEGACY_VREF_SEL_MASK;
+ vlow = SMPS_LEGACY_VLOW_SEL_MASK;
+ } else if (uV < SMPS_MODE2_UV_MAX + SMPS_MODE2_UV_STEP) {
+ vprog = ((uV - SMPS_MODE2_UV_MIN) / SMPS_MODE2_UV_STEP);
+ vref = SMPS_LEGACY_VREF_SEL_MASK;
+ vlow = 0;
+ } else {
+ vprog = ((uV - SMPS_MODE1_UV_MIN) / SMPS_MODE1_UV_STEP);
+ vref = 0;
+ vlow = 0;
+ }
+
+ /* set vlow bit for ultra low voltage mode */
+ rc = pm8058_vreg_write(chip, vreg->test_addr,
+ vlow | REGULATOR_BANK_WRITE | REGULATOR_BANK_SEL(1),
+ REGULATOR_BANK_MASK | SMPS_LEGACY_VLOW_SEL_MASK,
+ &vreg->test_reg[1]);
+ if (rc)
+ goto bail;
+
+ /* Set advanced mode bit to 0. */
+ rc = pm8058_vreg_write(chip, vreg->test_addr, SMPS_LEGACY_MODE
+ | REGULATOR_BANK_WRITE | REGULATOR_BANK_SEL(7),
+ SMPS_ADVANCED_MODE_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[7]);
+ if (rc)
+ goto bail;
+
+ en = (_pm8058_vreg_is_enabled(vreg) ? SMPS_LEGACY_ENABLE : 0);
+ pd = (vreg->pdata->pull_down_enable ? SMPS_LEGACY_PULL_DOWN_ENABLE : 0);
+
+ /* Set voltage (and the rest of the control register). */
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr, en | pd | vref | vprog,
+ SMPS_LEGACY_ENABLE | SMPS_LEGACY_PULL_DOWN_ENABLE
+ | SMPS_LEGACY_VREF_SEL_MASK | SMPS_LEGACY_VPROG_MASK,
+ &vreg->ctrl_reg);
+
+ vreg->save_uV = pm8058_smps_get_voltage_legacy(vreg);
+
+bail:
+ return rc;
+}
+
+static int pm8058_smps_set_voltage(struct regulator_dev *dev,
+ int min_uV, int max_uV, unsigned *selector)
+{
+ struct pm8058_vreg *vreg = rdev_get_drvdata(dev);
+ struct pm8058_chip *chip = dev_get_drvdata(dev->dev.parent);
+ int rc = 0;
+
+ if (min_uV < SMPS_UV_MIN || min_uV > SMPS_UV_MAX)
+ return -EINVAL;
+
+ if (SMPS_IN_ADVANCED_MODE(vreg))
+ rc = pm8058_smps_set_voltage_advanced(vreg, chip, min_uV, 0);
+ else
+ rc = pm8058_smps_set_voltage_legacy(vreg, chip, min_uV);
+
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+static int pm8058_ncp_set_voltage(struct regulator_dev *dev,
+ int min_uV, int max_uV, unsigned *selector)
+{
+ struct pm8058_vreg *vreg = rdev_get_drvdata(dev);
+ struct pm8058_chip *chip = dev_get_drvdata(dev->dev.parent);
+ int rc;
+ u8 val;
+
+ if (min_uV < NCP_UV_MIN || min_uV > NCP_UV_MAX)
+ return -EINVAL;
+
+ val = (min_uV - NCP_UV_MIN) / NCP_UV_STEP;
+
+ /* voltage setting */
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr, val, NCP_VPROG_MASK,
+ &vreg->ctrl_reg);
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+static int pm8058_ncp_get_voltage(struct regulator_dev *dev)
+{
+ struct pm8058_vreg *vreg = rdev_get_drvdata(dev);
+ u8 vprog = vreg->ctrl_reg & NCP_VPROG_MASK;
+ return NCP_UV_MIN + vprog * NCP_UV_STEP;
+}
+
+static int pm8058_ldo_set_mode(struct pm8058_vreg *vreg,
+ struct pm8058_chip *chip, unsigned int mode)
+{
+ int rc = 0;
+ u8 mask, val;
+
+ switch (mode) {
+ case REGULATOR_MODE_FAST:
+ /* HPM */
+ val = (_pm8058_vreg_is_enabled(vreg) ? LDO_ENABLE : 0)
+ | LDO_CTRL_PM_HPM;
+ mask = LDO_ENABLE_MASK | LDO_CTRL_PM_MASK;
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr, val, mask,
+ &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ if (pm8058_vreg_using_pin_ctrl(vreg))
+ rc = pm8058_vreg_set_pin_ctrl(vreg, chip, 0);
+ if (rc)
+ goto bail;
+ break;
+
+ case REGULATOR_MODE_STANDBY:
+ /* LPM */
+ val = (_pm8058_vreg_is_enabled(vreg) ? LDO_ENABLE : 0)
+ | LDO_CTRL_PM_LPM;
+ mask = LDO_ENABLE_MASK | LDO_CTRL_PM_MASK;
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr, val, mask,
+ &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ val = LDO_TEST_LPM_SEL_CTRL | REGULATOR_BANK_WRITE
+ | REGULATOR_BANK_SEL(0);
+ mask = LDO_TEST_LPM_MASK | REGULATOR_BANK_MASK;
+ rc = pm8058_vreg_write(chip, vreg->test_addr, val, mask,
+ &vreg->test_reg[0]);
+ if (rc)
+ goto bail;
+
+ if (pm8058_vreg_using_pin_ctrl(vreg))
+ rc = pm8058_vreg_set_pin_ctrl(vreg, chip, 0);
+ if (rc)
+ goto bail;
+ break;
+
+ case REGULATOR_MODE_IDLE:
+ /* Pin Control */
+ if (_pm8058_vreg_is_enabled(vreg))
+ rc = pm8058_vreg_set_pin_ctrl(vreg, chip, 1);
+ if (rc)
+ goto bail;
+ break;
+
+ default:
+ pr_err("%s: invalid mode: %u\n", __func__, mode);
+ return -EINVAL;
+ }
+
+bail:
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+static int pm8058_smps_set_mode(struct pm8058_vreg *vreg,
+ struct pm8058_chip *chip, unsigned int mode)
+{
+ int rc = 0;
+ u8 mask, val;
+
+ switch (mode) {
+ case REGULATOR_MODE_FAST:
+ /* HPM */
+ val = SMPS_CLK_CTRL_PWM;
+ mask = SMPS_CLK_CTRL_MASK;
+ rc = pm8058_vreg_write(chip, vreg->clk_ctrl_addr, val, mask,
+ &vreg->clk_ctrl_reg);
+ if (rc)
+ goto bail;
+
+ if (pm8058_vreg_using_pin_ctrl(vreg))
+ rc = pm8058_vreg_set_pin_ctrl(vreg, chip, 0);
+ if (rc)
+ goto bail;
+ break;
+
+ case REGULATOR_MODE_STANDBY:
+ /* LPM */
+ val = SMPS_CLK_CTRL_PFM;
+ mask = SMPS_CLK_CTRL_MASK;
+ rc = pm8058_vreg_write(chip, vreg->clk_ctrl_addr, val, mask,
+ &vreg->clk_ctrl_reg);
+ if (rc)
+ goto bail;
+
+ if (pm8058_vreg_using_pin_ctrl(vreg))
+ rc = pm8058_vreg_set_pin_ctrl(vreg, chip, 0);
+ if (rc)
+ goto bail;
+ break;
+
+ case REGULATOR_MODE_IDLE:
+ /* Pin Control */
+ if (_pm8058_vreg_is_enabled(vreg))
+ rc = pm8058_vreg_set_pin_ctrl(vreg, chip, 1);
+ if (rc)
+ goto bail;
+ break;
+
+ default:
+ pr_err("%s: invalid mode: %u\n", __func__, mode);
+ return -EINVAL;
+ }
+
+bail:
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+static int pm8058_lvs_set_mode(struct pm8058_vreg *vreg,
+ struct pm8058_chip *chip, unsigned int mode)
+{
+ int rc = 0;
+
+ if (mode == REGULATOR_MODE_IDLE) {
+ /* Use pin control. */
+ if (_pm8058_vreg_is_enabled(vreg))
+ rc = pm8058_vreg_set_pin_ctrl(vreg, chip, 1);
+ } else {
+ /* Turn off pin control. */
+ rc = pm8058_vreg_set_pin_ctrl(vreg, chip, 0);
+ }
+
+ return rc;
+}
+
+/*
+ * Optimum mode programming:
+ * REGULATOR_MODE_FAST: Go to HPM (highest priority)
+ * REGULATOR_MODE_STANDBY: Go to pin ctrl mode if there are any pin ctrl
+ * votes, else go to LPM
+ *
+ * Pin ctrl mode voting via regulator set_mode:
+ * REGULATOR_MODE_IDLE: Go to pin ctrl mode if the optimum mode is LPM, else
+ * go to HPM
+ * REGULATOR_MODE_NORMAL: Go to LPM if it is the optimum mode, else go to HPM
+ */
+static int pm8058_vreg_set_mode(struct regulator_dev *dev, unsigned int mode)
+{
+ struct pm8058_vreg *vreg = rdev_get_drvdata(dev);
+ struct pm8058_chip *chip = dev_get_drvdata(dev->dev.parent);
+ unsigned prev_optimum = vreg->optimum;
+ unsigned prev_pc_vote = vreg->pc_vote;
+ unsigned prev_mode_initialized = vreg->mode_initialized;
+ int new_mode = REGULATOR_MODE_FAST;
+ int rc = 0;
+
+ /* Determine new mode to go into. */
+ switch (mode) {
+ case REGULATOR_MODE_FAST:
+ new_mode = REGULATOR_MODE_FAST;
+ vreg->optimum = mode;
+ vreg->mode_initialized = 1;
+ break;
+
+ case REGULATOR_MODE_STANDBY:
+ if (vreg->pc_vote)
+ new_mode = REGULATOR_MODE_IDLE;
+ else
+ new_mode = REGULATOR_MODE_STANDBY;
+ vreg->optimum = mode;
+ vreg->mode_initialized = 1;
+ break;
+
+ case REGULATOR_MODE_IDLE:
+ if (vreg->pc_vote++)
+ goto done; /* already taken care of */
+
+ if (vreg->mode_initialized
+ && vreg->optimum == REGULATOR_MODE_FAST)
+ new_mode = REGULATOR_MODE_FAST;
+ else
+ new_mode = REGULATOR_MODE_IDLE;
+ break;
+
+ case REGULATOR_MODE_NORMAL:
+ if (vreg->pc_vote && --(vreg->pc_vote))
+ goto done; /* already taken care of */
+
+ if (vreg->optimum == REGULATOR_MODE_STANDBY)
+ new_mode = REGULATOR_MODE_STANDBY;
+ else
+ new_mode = REGULATOR_MODE_FAST;
+ break;
+
+ default:
+ pr_err("%s: unknown mode, mode=%u\n", __func__, mode);
+ return -EINVAL;
+ }
+
+ switch (vreg->type) {
+ case REGULATOR_TYPE_LDO:
+ rc = pm8058_ldo_set_mode(vreg, chip, new_mode);
+ break;
+ case REGULATOR_TYPE_SMPS:
+ rc = pm8058_smps_set_mode(vreg, chip, new_mode);
+ break;
+ case REGULATOR_TYPE_LVS:
+ rc = pm8058_lvs_set_mode(vreg, chip, new_mode);
+ break;
+ }
+
+ if (rc) {
+ print_write_error(vreg, rc, __func__);
+ vreg->mode_initialized = prev_mode_initialized;
+ vreg->optimum = prev_optimum;
+ vreg->pc_vote = prev_pc_vote;
+ return rc;
+ }
+
+done:
+ return 0;
+}
+
+static unsigned int pm8058_vreg_get_mode(struct regulator_dev *dev)
+{
+ struct pm8058_vreg *vreg = rdev_get_drvdata(dev);
+
+ if (!vreg->mode_initialized && vreg->pc_vote)
+ return REGULATOR_MODE_IDLE;
+
+ /* Check physical pin control state. */
+ switch (vreg->type) {
+ case REGULATOR_TYPE_LDO:
+ if (!(vreg->ctrl_reg & LDO_ENABLE_MASK)
+ && !pm8058_vreg_is_global_enabled(vreg)
+ && (vreg->test_reg[5] & LDO_TEST_PIN_CTRL_MASK))
+ return REGULATOR_MODE_IDLE;
+ else if (((vreg->ctrl_reg & LDO_ENABLE_MASK)
+ || pm8058_vreg_is_global_enabled(vreg))
+ && (vreg->ctrl_reg & LDO_CTRL_PM_MASK)
+ && (vreg->test_reg[6] & LDO_TEST_PIN_CTRL_LPM_MASK))
+ return REGULATOR_MODE_IDLE;
+ break;
+ case REGULATOR_TYPE_SMPS:
+ if (!SMPS_IN_ADVANCED_MODE(vreg)
+ && !(vreg->ctrl_reg & REGULATOR_EN_MASK)
+ && !pm8058_vreg_is_global_enabled(vreg)
+ && (vreg->sleep_ctrl_reg & SMPS_PIN_CTRL_MASK))
+ return REGULATOR_MODE_IDLE;
+ else if (!SMPS_IN_ADVANCED_MODE(vreg)
+ && ((vreg->ctrl_reg & REGULATOR_EN_MASK)
+ || pm8058_vreg_is_global_enabled(vreg))
+ && ((vreg->clk_ctrl_reg & SMPS_CLK_CTRL_MASK)
+ == SMPS_CLK_CTRL_PFM)
+ && (vreg->sleep_ctrl_reg & SMPS_PIN_CTRL_LPM_MASK))
+ return REGULATOR_MODE_IDLE;
+ break;
+ case REGULATOR_TYPE_LVS:
+ if (!(vreg->ctrl_reg & LVS_ENABLE_MASK)
+ && !pm8058_vreg_is_global_enabled(vreg)
+ && (vreg->ctrl_reg & LVS_PIN_CTRL_MASK))
+ return REGULATOR_MODE_IDLE;
+ }
+
+ if (vreg->optimum == REGULATOR_MODE_FAST)
+ return REGULATOR_MODE_FAST;
+ else if (vreg->pc_vote)
+ return REGULATOR_MODE_IDLE;
+ else if (vreg->optimum == REGULATOR_MODE_STANDBY)
+ return REGULATOR_MODE_STANDBY;
+ return REGULATOR_MODE_FAST;
+}
+
+unsigned int pm8058_vreg_get_optimum_mode(struct regulator_dev *dev,
+ int input_uV, int output_uV, int load_uA)
+{
+ struct pm8058_vreg *vreg = rdev_get_drvdata(dev);
+
+ if (load_uA <= 0) {
+ /*
+ * pm8058_vreg_get_optimum_mode is being called before consumers
+ * have specified their load currents via
+ * regulator_set_optimum_mode. Return whatever the existing mode
+ * is.
+ */
+ return pm8058_vreg_get_mode(dev);
+ }
+
+ if (load_uA >= vreg->hpm_min_load)
+ return REGULATOR_MODE_FAST;
+ return REGULATOR_MODE_STANDBY;
+}
+
+static struct regulator_ops pm8058_ldo_ops = {
+ .enable = pm8058_vreg_enable,
+ .disable = pm8058_vreg_disable,
+ .is_enabled = pm8058_vreg_is_enabled,
+ .set_voltage = pm8058_ldo_set_voltage,
+ .get_voltage = pm8058_ldo_get_voltage,
+ .set_mode = pm8058_vreg_set_mode,
+ .get_mode = pm8058_vreg_get_mode,
+ .get_optimum_mode = pm8058_vreg_get_optimum_mode,
+};
+
+static struct regulator_ops pm8058_smps_ops = {
+ .enable = pm8058_vreg_enable,
+ .disable = pm8058_vreg_disable,
+ .is_enabled = pm8058_vreg_is_enabled,
+ .set_voltage = pm8058_smps_set_voltage,
+ .get_voltage = pm8058_smps_get_voltage,
+ .set_mode = pm8058_vreg_set_mode,
+ .get_mode = pm8058_vreg_get_mode,
+ .get_optimum_mode = pm8058_vreg_get_optimum_mode,
+};
+
+static struct regulator_ops pm8058_lvs_ops = {
+ .enable = pm8058_vreg_enable,
+ .disable = pm8058_vreg_disable,
+ .is_enabled = pm8058_vreg_is_enabled,
+ .set_mode = pm8058_vreg_set_mode,
+ .get_mode = pm8058_vreg_get_mode,
+};
+
+static struct regulator_ops pm8058_ncp_ops = {
+ .enable = pm8058_vreg_enable,
+ .disable = pm8058_vreg_disable,
+ .is_enabled = pm8058_vreg_is_enabled,
+ .set_voltage = pm8058_ncp_set_voltage,
+ .get_voltage = pm8058_ncp_get_voltage,
+};
+
+#define VREG_DESCRIP(_id, _name, _ops) \
+ [_id] = { \
+ .id = _id, \
+ .name = _name, \
+ .ops = _ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .owner = THIS_MODULE, \
+ }
+
+static struct regulator_desc pm8058_vreg_descrip[] = {
+ VREG_DESCRIP(PM8058_VREG_ID_L0, "8058_l0", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L1, "8058_l1", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L2, "8058_l2", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L3, "8058_l3", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L4, "8058_l4", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L5, "8058_l5", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L6, "8058_l6", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L7, "8058_l7", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L8, "8058_l8", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L9, "8058_l9", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L10, "8058_l10", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L11, "8058_l11", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L12, "8058_l12", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L13, "8058_l13", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L14, "8058_l14", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L15, "8058_l15", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L16, "8058_l16", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L17, "8058_l17", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L18, "8058_l18", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L19, "8058_l19", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L20, "8058_l20", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L21, "8058_l21", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L22, "8058_l22", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L23, "8058_l23", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L24, "8058_l24", &pm8058_ldo_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_L25, "8058_l25", &pm8058_ldo_ops),
+
+ VREG_DESCRIP(PM8058_VREG_ID_S0, "8058_s0", &pm8058_smps_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_S1, "8058_s1", &pm8058_smps_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_S2, "8058_s2", &pm8058_smps_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_S3, "8058_s3", &pm8058_smps_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_S4, "8058_s4", &pm8058_smps_ops),
+
+ VREG_DESCRIP(PM8058_VREG_ID_LVS0, "8058_lvs0", &pm8058_lvs_ops),
+ VREG_DESCRIP(PM8058_VREG_ID_LVS1, "8058_lvs1", &pm8058_lvs_ops),
+
+ VREG_DESCRIP(PM8058_VREG_ID_NCP, "8058_ncp", &pm8058_ncp_ops),
+};
+
+static int pm8058_master_enable_init(struct pm8058_chip *chip)
+{
+ int rc = 0, i;
+
+ for (i = 0; i < MASTER_ENABLE_COUNT; i++) {
+ rc = pm8058_read(chip, m_en[i].addr, &(m_en[i].reg), 1);
+ if (rc)
+ goto bail;
+ }
+
+bail:
+ if (rc)
+ pr_err("%s: pm8058_read failed, rc=%d\n", __func__, rc);
+
+ return rc;
+}
+
+static int pm8058_init_ldo(struct pm8058_chip *chip, struct pm8058_vreg *vreg)
+{
+ int rc = 0, i;
+ u8 bank;
+
+ /* Save the current test register state. */
+ for (i = 0; i < LDO_TEST_BANKS; i++) {
+ bank = REGULATOR_BANK_SEL(i);
+ rc = pm8058_write(chip, vreg->test_addr, &bank, 1);
+ if (rc)
+ goto bail;
+
+ rc = pm8058_read(chip, vreg->test_addr, &vreg->test_reg[i], 1);
+ if (rc)
+ goto bail;
+ vreg->test_reg[i] |= REGULATOR_BANK_WRITE;
+ }
+
+ if ((vreg->ctrl_reg & LDO_CTRL_PM_MASK) == LDO_CTRL_PM_LPM)
+ vreg->optimum = REGULATOR_MODE_STANDBY;
+ else
+ vreg->optimum = REGULATOR_MODE_FAST;
+
+ /* Set pull down enable based on platform data. */
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr,
+ (vreg->pdata->pull_down_enable ? LDO_PULL_DOWN_ENABLE : 0),
+ LDO_PULL_DOWN_ENABLE_MASK, &vreg->ctrl_reg);
+bail:
+ return rc;
+}
+
+static int pm8058_init_smps(struct pm8058_chip *chip, struct pm8058_vreg *vreg)
+{
+ int rc = 0, i;
+ u8 bank;
+
+ /* Save the current test2 register state. */
+ for (i = 0; i < SMPS_TEST_BANKS; i++) {
+ bank = REGULATOR_BANK_SEL(i);
+ rc = pm8058_write(chip, vreg->test_addr, &bank, 1);
+ if (rc)
+ goto bail;
+
+ rc = pm8058_read(chip, vreg->test_addr, &vreg->test_reg[i],
+ 1);
+ if (rc)
+ goto bail;
+ vreg->test_reg[i] |= REGULATOR_BANK_WRITE;
+ }
+
+ /* Save the current clock control register state. */
+ rc = pm8058_read(chip, vreg->clk_ctrl_addr, &vreg->clk_ctrl_reg, 1);
+ if (rc)
+ goto bail;
+
+ /* Save the current sleep control register state. */
+ rc = pm8058_read(chip, vreg->sleep_ctrl_addr, &vreg->sleep_ctrl_reg, 1);
+ if (rc)
+ goto bail;
+
+ vreg->save_uV = 1; /* This is not a no-op. */
+ vreg->save_uV = _pm8058_smps_get_voltage(vreg);
+
+ if ((vreg->clk_ctrl_reg & SMPS_CLK_CTRL_MASK) == SMPS_CLK_CTRL_PFM)
+ vreg->optimum = REGULATOR_MODE_STANDBY;
+ else
+ vreg->optimum = REGULATOR_MODE_FAST;
+
+ /* Set advanced mode pull down enable based on platform data. */
+ rc = pm8058_vreg_write(chip, vreg->test_addr,
+ (vreg->pdata->pull_down_enable
+ ? SMPS_ADVANCED_PULL_DOWN_ENABLE : 0)
+ | REGULATOR_BANK_SEL(6) | REGULATOR_BANK_WRITE,
+ REGULATOR_BANK_MASK | SMPS_ADVANCED_PULL_DOWN_ENABLE,
+ &vreg->test_reg[6]);
+ if (rc)
+ goto bail;
+
+ if (!SMPS_IN_ADVANCED_MODE(vreg)) {
+ /* Set legacy mode pull down enable based on platform data. */
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr,
+ (vreg->pdata->pull_down_enable
+ ? SMPS_LEGACY_PULL_DOWN_ENABLE : 0),
+ SMPS_LEGACY_PULL_DOWN_ENABLE, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+ }
+
+bail:
+ return rc;
+}
+
+static int pm8058_init_lvs(struct pm8058_chip *chip, struct pm8058_vreg *vreg)
+{
+ int rc = 0;
+
+ vreg->optimum = REGULATOR_MODE_FAST;
+
+ /* Set pull down enable based on platform data. */
+ rc = pm8058_vreg_write(chip, vreg->ctrl_addr,
+ (vreg->pdata->pull_down_enable
+ ? LVS_PULL_DOWN_ENABLE : LVS_PULL_DOWN_DISABLE),
+ LVS_PULL_DOWN_ENABLE_MASK, &vreg->ctrl_reg);
+ return rc;
+}
+
+static int pm8058_init_ncp(struct pm8058_chip *chip, struct pm8058_vreg *vreg)
+{
+ int rc = 0;
+
+ /* Save the current test1 register state. */
+ rc = pm8058_read(chip, vreg->test_addr, &vreg->test_reg[0], 1);
+ if (rc)
+ goto bail;
+
+ vreg->optimum = REGULATOR_MODE_FAST;
+
+bail:
+ return rc;
+}
+
+static int pm8058_init_regulator(struct pm8058_chip *chip,
+ struct pm8058_vreg *vreg)
+{
+ static int master_enable_inited;
+ int rc = 0;
+
+ vreg->mode_initialized = 0;
+
+ if (!master_enable_inited) {
+ rc = pm8058_master_enable_init(chip);
+ if (!rc)
+ master_enable_inited = 1;
+ }
+
+ /* save the current control register state */
+ rc = pm8058_read(chip, vreg->ctrl_addr, &vreg->ctrl_reg, 1);
+ if (rc)
+ goto bail;
+
+ switch (vreg->type) {
+ case REGULATOR_TYPE_LDO:
+ rc = pm8058_init_ldo(chip, vreg);
+ break;
+ case REGULATOR_TYPE_SMPS:
+ rc = pm8058_init_smps(chip, vreg);
+ break;
+ case REGULATOR_TYPE_LVS:
+ rc = pm8058_init_lvs(chip, vreg);
+ break;
+ case REGULATOR_TYPE_NCP:
+ rc = pm8058_init_ncp(chip, vreg);
+ break;
+ }
+
+bail:
+ if (rc)
+ pr_err("%s: pm8058_read/write failed; initial register states "
+ "unknown, rc=%d\n", __func__, rc);
+ return rc;
+}
+
+static int __devinit pm8058_vreg_probe(struct platform_device *pdev)
+{
+ struct regulator_desc *rdesc;
+ struct pm8058_chip *chip;
+ struct pm8058_vreg *vreg;
+ const char *reg_name = NULL;
+ int rc = 0;
+
+ if (pdev == NULL)
+ return -EINVAL;
+
+ if (pdev->id >= 0 && pdev->id < PM8058_VREG_MAX) {
+ chip = platform_get_drvdata(pdev);
+ rdesc = &pm8058_vreg_descrip[pdev->id];
+ vreg = &pm8058_vreg[pdev->id];
+ vreg->pdata = pdev->dev.platform_data;
+ reg_name = pm8058_vreg_descrip[pdev->id].name;
+
+ rc = pm8058_init_regulator(chip, vreg);
+ if (rc)
+ goto bail;
+
+ /* Disallow idle and normal modes if pin control isn't set. */
+ if (vreg->pdata->pin_ctrl == 0)
+ vreg->pdata->init_data.constraints.valid_modes_mask
+ &= ~(REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE);
+
+ vreg->rdev = regulator_register(rdesc, &pdev->dev,
+ &vreg->pdata->init_data, vreg);
+ if (IS_ERR(vreg->rdev)) {
+ rc = PTR_ERR(vreg->rdev);
+ pr_err("%s: regulator_register failed for %s, rc=%d\n",
+ __func__, reg_name, rc);
+ }
+ } else {
+ rc = -ENODEV;
+ }
+
+bail:
+ if (rc)
+ pr_err("%s: error for %s, rc=%d\n", __func__, reg_name, rc);
+
+ return rc;
+}
+
+static int __devexit pm8058_vreg_remove(struct platform_device *pdev)
+{
+ regulator_unregister(pm8058_vreg[pdev->id].rdev);
+ return 0;
+}
+
+static struct platform_driver pm8058_vreg_driver = {
+ .probe = pm8058_vreg_probe,
+ .remove = __devexit_p(pm8058_vreg_remove),
+ .driver = {
+ .name = "pm8058-regulator",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pm8058_vreg_init(void)
+{
+ return platform_driver_register(&pm8058_vreg_driver);
+}
+
+static void __exit pm8058_vreg_exit(void)
+{
+ platform_driver_unregister(&pm8058_vreg_driver);
+}
+
+static void print_write_error(struct pm8058_vreg *vreg, int rc,
+ const char *func)
+{
+ const char *reg_name = NULL;
+ ptrdiff_t id = vreg - pm8058_vreg;
+
+ if (id >= 0 && id < PM8058_VREG_MAX)
+ reg_name = pm8058_vreg_descrip[id].name;
+ pr_err("%s: pm8058_vreg_write failed for %s, rc=%d\n",
+ func, reg_name, rc);
+}
+
+subsys_initcall(pm8058_vreg_init);
+module_exit(pm8058_vreg_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PMIC8058 regulator driver");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:pm8058-regulator");
diff --git a/drivers/regulator/pmic8901-regulator.c b/drivers/regulator/pmic8901-regulator.c
new file mode 100644
index 0000000..5b4b907
--- /dev/null
+++ b/drivers/regulator/pmic8901-regulator.c
@@ -0,0 +1,1097 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mfd/pmic8901.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/pmic8901-regulator.h>
+#include <mach/mpp.h>
+
+/* Regulator types */
+#define REGULATOR_TYPE_LDO 0
+#define REGULATOR_TYPE_SMPS 1
+#define REGULATOR_TYPE_VS 2
+#define REGULATOR_TYPE_MPP 3
+
+/* Bank select/write macros */
+#define REGULATOR_BANK_SEL(n) ((n) << 4)
+#define REGULATOR_BANK_WRITE 0x80
+#define LDO_TEST_BANKS 7
+#define REGULATOR_BANK_MASK 0xF0
+
+/* Pin mask resource register programming */
+#define VREG_PMR_STATE_MASK 0x60
+#define VREG_PMR_STATE_HPM 0x60
+#define VREG_PMR_STATE_LPM 0x40
+#define VREG_PMR_STATE_OFF 0x20
+#define VREG_PMR_STATE_PIN_CTRL 0x20
+
+#define VREG_PMR_MODE_ACTION_MASK 0x10
+#define VREG_PMR_MODE_ACTION_SLEEP 0x10
+#define VREG_PMR_MODE_ACTION_OFF 0x00
+
+#define VREG_PMR_MODE_PIN_MASK 0x08
+#define VREG_PMR_MODE_PIN_MASKED 0x08
+
+#define VREG_PMR_CTRL_PIN2_MASK 0x04
+#define VREG_PMR_CTRL_PIN2_MASKED 0x04
+
+#define VREG_PMR_CTRL_PIN1_MASK 0x02
+#define VREG_PMR_CTRL_PIN1_MASKED 0x02
+
+#define VREG_PMR_CTRL_PIN0_MASK 0x01
+#define VREG_PMR_CTRL_PIN0_MASKED 0x01
+
+#define VREG_PMR_PIN_CTRL_ALL_MASK 0x1F
+#define VREG_PMR_PIN_CTRL_ALL_MASKED 0x1F
+
+#define REGULATOR_IS_EN(pmr_reg) \
+ ((pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_HPM || \
+ (pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_LPM)
+
+/* FTSMPS programming */
+
+/* CTRL register */
+#define SMPS_VCTRL_BAND_MASK 0xC0
+#define SMPS_VCTRL_BAND_OFF 0x00
+#define SMPS_VCTRL_BAND_1 0x40
+#define SMPS_VCTRL_BAND_2 0x80
+#define SMPS_VCTRL_BAND_3 0xC0
+#define SMPS_VCTRL_VPROG_MASK 0x3F
+
+#define SMPS_BAND_1_UV_MIN 350000
+#define SMPS_BAND_1_UV_MAX 650000
+#define SMPS_BAND_1_UV_STEP 6250
+
+#define SMPS_BAND_2_UV_MIN 700000
+#define SMPS_BAND_2_UV_MAX 1400000
+#define SMPS_BAND_2_UV_STEP 12500
+
+#define SMPS_BAND_3_UV_SETPOINT_MIN 1500000
+#define SMPS_BAND_3_UV_MIN 1400000
+#define SMPS_BAND_3_UV_MAX 3300000
+#define SMPS_BAND_3_UV_STEP 50000
+
+#define SMPS_UV_MIN SMPS_BAND_1_UV_MIN
+#define SMPS_UV_MAX SMPS_BAND_3_UV_MAX
+
+/* PWR_CNFG register */
+#define SMPS_PULL_DOWN_ENABLE_MASK 0x40
+#define SMPS_PULL_DOWN_ENABLE 0x40
+
+/* LDO programming */
+
+/* CTRL register */
+#define LDO_LOCAL_ENABLE_MASK 0x80
+#define LDO_LOCAL_ENABLE 0x80
+
+#define LDO_PULL_DOWN_ENABLE_MASK 0x40
+#define LDO_PULL_DOWN_ENABLE 0x40
+
+#define LDO_CTRL_VPROG_MASK 0x1F
+
+/* TEST register bank 2 */
+#define LDO_TEST_VPROG_UPDATE_MASK 0x08
+#define LDO_TEST_RANGE_SEL_MASK 0x04
+#define LDO_TEST_FINE_STEP_MASK 0x02
+#define LDO_TEST_FINE_STEP_SHIFT 1
+
+/* TEST register bank 4 */
+#define LDO_TEST_RANGE_EXT_MASK 0x01
+
+/* Allowable voltage ranges */
+#define PLDO_LOW_UV_MIN 750000
+#define PLDO_LOW_UV_MAX 1537500
+#define PLDO_LOW_FINE_STEP_UV 12500
+
+#define PLDO_NORM_UV_MIN 1500000
+#define PLDO_NORM_UV_MAX 3075000
+#define PLDO_NORM_FINE_STEP_UV 25000
+
+#define PLDO_HIGH_UV_MIN 1750000
+#define PLDO_HIGH_UV_MAX 4900000
+#define PLDO_HIGH_FINE_STEP_UV 50000
+
+#define NLDO_UV_MIN 750000
+#define NLDO_UV_MAX 1537500
+#define NLDO_FINE_STEP_UV 12500
+
+/* VS programming */
+
+/* CTRL register */
+#define VS_CTRL_ENABLE_MASK 0xC0
+#define VS_CTRL_DISABLE 0x00
+#define VS_CTRL_ENABLE 0x40
+#define VS_CTRL_USE_PMR 0xC0
+
+#define VS_PULL_DOWN_ENABLE_MASK 0x20
+#define VS_PULL_DOWN_ENABLE 0x20
+
+struct pm8901_vreg {
+ struct pm8901_vreg_pdata *pdata;
+ struct regulator_dev *rdev;
+ struct pm8901_chip *chip;
+ int hpm_min_load;
+ unsigned pc_vote;
+ unsigned optimum;
+ unsigned mode_initialized;
+ u16 ctrl_addr;
+ u16 pmr_addr;
+ u16 test_addr;
+ u16 pfm_ctrl_addr;
+ u16 pwr_cnfg_addr;
+ u8 type;
+ u8 ctrl_reg;
+ u8 pmr_reg;
+ u8 test_reg[LDO_TEST_BANKS];
+ u8 pfm_ctrl_reg;
+ u8 pwr_cnfg_reg;
+ u8 is_nmos;
+ u8 mpp_id;
+ u8 state;
+};
+
+/*
+ * These are used to compensate for the PMIC 8901 v1 FTS regulators which
+ * output ~10% higher than the programmed set point.
+ */
+#define IS_PMIC_8901_V1(rev) ((rev) == PM_8901_REV_1p0 || \
+ (rev) == PM_8901_REV_1p1)
+
+#define PMIC_8901_V1_SCALE(uV) ((((uV) - 62100) * 23) / 25)
+
+#define PMIC_8901_V1_SCALE_INV(uV) (((uV) * 25) / 23 + 62100)
+
+/*
+ * Band 1 of PMIC 8901 SMPS regulators only supports set points with the 3 LSB's
+ * equal to 0. This is accomplished in the macro by truncating the bits.
+ */
+#define PM8901_SMPS_BAND_1_COMPENSATE(vprog) ((vprog) & 0xF8)
+
+#define LDO(_id, _ctrl_addr, _pmr_addr, _test_addr, _is_nmos) \
+ [_id] = { \
+ .ctrl_addr = _ctrl_addr, \
+ .pmr_addr = _pmr_addr, \
+ .test_addr = _test_addr, \
+ .type = REGULATOR_TYPE_LDO, \
+ .is_nmos = _is_nmos, \
+ .hpm_min_load = PM8901_VREG_LDO_300_HPM_MIN_LOAD, \
+ }
+
+#define SMPS(_id, _ctrl_addr, _pmr_addr, _pfm_ctrl_addr, _pwr_cnfg_addr) \
+ [_id] = { \
+ .ctrl_addr = _ctrl_addr, \
+ .pmr_addr = _pmr_addr, \
+ .pfm_ctrl_addr = _pfm_ctrl_addr, \
+ .pwr_cnfg_addr = _pwr_cnfg_addr, \
+ .type = REGULATOR_TYPE_SMPS, \
+ .hpm_min_load = PM8901_VREG_FTSMPS_HPM_MIN_LOAD, \
+ }
+
+#define VS(_id, _ctrl_addr, _pmr_addr) \
+ [_id] = { \
+ .ctrl_addr = _ctrl_addr, \
+ .pmr_addr = _pmr_addr, \
+ .type = REGULATOR_TYPE_VS, \
+ }
+
+#define MPP(_id, _mpp_id) \
+ [_id] = { \
+ .mpp_id = _mpp_id, \
+ .type = REGULATOR_TYPE_MPP, \
+ }
+
+static struct pm8901_vreg pm8901_vreg[] = {
+ /* id ctrl pmr tst n/p */
+ LDO(PM8901_VREG_ID_L0, 0x02F, 0x0AB, 0x030, 1),
+ LDO(PM8901_VREG_ID_L1, 0x031, 0x0AC, 0x032, 0),
+ LDO(PM8901_VREG_ID_L2, 0x033, 0x0AD, 0x034, 0),
+ LDO(PM8901_VREG_ID_L3, 0x035, 0x0AE, 0x036, 0),
+ LDO(PM8901_VREG_ID_L4, 0x037, 0x0AF, 0x038, 0),
+ LDO(PM8901_VREG_ID_L5, 0x039, 0x0B0, 0x03A, 0),
+ LDO(PM8901_VREG_ID_L6, 0x03B, 0x0B1, 0x03C, 0),
+
+ /* id ctrl pmr pfm pwr */
+ SMPS(PM8901_VREG_ID_S0, 0x05B, 0x0A6, 0x05C, 0x0E3),
+ SMPS(PM8901_VREG_ID_S1, 0x06A, 0x0A7, 0x06B, 0x0EC),
+ SMPS(PM8901_VREG_ID_S2, 0x079, 0x0A8, 0x07A, 0x0F1),
+ SMPS(PM8901_VREG_ID_S3, 0x088, 0x0A9, 0x089, 0x0F6),
+ SMPS(PM8901_VREG_ID_S4, 0x097, 0x0AA, 0x098, 0x0FB),
+
+ /* id MPP ID */
+ MPP(PM8901_VREG_ID_MPP0, 0),
+
+ /* id ctrl pmr */
+ VS(PM8901_VREG_ID_LVS0, 0x046, 0x0B2),
+ VS(PM8901_VREG_ID_LVS1, 0x048, 0x0B3),
+ VS(PM8901_VREG_ID_LVS2, 0x04A, 0x0B4),
+ VS(PM8901_VREG_ID_LVS3, 0x04C, 0x0B5),
+ VS(PM8901_VREG_ID_MVS0, 0x052, 0x0B6),
+ VS(PM8901_VREG_ID_USB_OTG, 0x055, 0x0B7),
+ VS(PM8901_VREG_ID_HDMI_MVS, 0x058, 0x0B8),
+};
+
+static void print_write_error(struct pm8901_vreg *vreg, int rc,
+ const char *func);
+
+static int pm8901_vreg_write(struct pm8901_chip *chip,
+ u16 addr, u8 val, u8 mask, u8 *reg_save)
+{
+ int rc = 0;
+ u8 reg;
+
+ reg = (*reg_save & ~mask) | (val & mask);
+ if (reg != *reg_save)
+ rc = pm8901_write(chip, addr, ®, 1);
+ if (!rc)
+ *reg_save = reg;
+ return rc;
+}
+
+/* Set pin control bits based on new mode. */
+static int pm8901_vreg_select_pin_ctrl(struct pm8901_vreg *vreg, u8 *pmr_reg)
+{
+ *pmr_reg |= VREG_PMR_PIN_CTRL_ALL_MASKED;
+
+ if ((*pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_PIN_CTRL) {
+ if (vreg->pdata->pin_fn == PM8901_VREG_PIN_FN_MODE)
+ *pmr_reg = (*pmr_reg & ~VREG_PMR_STATE_MASK)
+ | VREG_PMR_STATE_LPM;
+ if (vreg->pdata->pin_ctrl & PM8901_VREG_PIN_CTRL_A0)
+ *pmr_reg &= ~VREG_PMR_CTRL_PIN0_MASKED;
+ if (vreg->pdata->pin_ctrl & PM8901_VREG_PIN_CTRL_A1)
+ *pmr_reg &= ~VREG_PMR_CTRL_PIN1_MASKED;
+ if (vreg->pdata->pin_ctrl & PM8901_VREG_PIN_CTRL_D0)
+ *pmr_reg &= ~VREG_PMR_CTRL_PIN2_MASKED;
+ }
+
+ return 0;
+}
+
+static int pm8901_vreg_enable(struct regulator_dev *dev)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+ struct pm8901_chip *chip = vreg->chip;
+ u8 val = VREG_PMR_STATE_HPM;
+ int rc;
+
+ if (!vreg->mode_initialized && vreg->pc_vote)
+ val = VREG_PMR_STATE_PIN_CTRL;
+ else if (vreg->optimum == REGULATOR_MODE_FAST)
+ val = VREG_PMR_STATE_HPM;
+ else if (vreg->pc_vote)
+ val = VREG_PMR_STATE_PIN_CTRL;
+ else if (vreg->optimum == REGULATOR_MODE_STANDBY)
+ val = VREG_PMR_STATE_LPM;
+
+ pm8901_vreg_select_pin_ctrl(vreg, &val);
+
+ rc = pm8901_vreg_write(chip, vreg->pmr_addr,
+ val,
+ VREG_PMR_STATE_MASK | VREG_PMR_PIN_CTRL_ALL_MASK,
+ &vreg->pmr_reg);
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+static int pm8901_vreg_disable(struct regulator_dev *dev)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+ struct pm8901_chip *chip = vreg->chip;
+ int rc;
+
+ rc = pm8901_vreg_write(chip, vreg->pmr_addr,
+ VREG_PMR_STATE_OFF | VREG_PMR_PIN_CTRL_ALL_MASKED,
+ VREG_PMR_STATE_MASK | VREG_PMR_PIN_CTRL_ALL_MASK,
+ &vreg->pmr_reg);
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+/*
+ * Cases that count as enabled:
+ *
+ * 1. PMR register has mode == HPM or LPM.
+ * 2. Any pin control bits are unmasked.
+ * 3. The regulator is an LDO and its local enable bit is set.
+ */
+static int _pm8901_vreg_is_enabled(struct pm8901_vreg *vreg)
+{
+ if ((vreg->type == REGULATOR_TYPE_LDO)
+ && (vreg->ctrl_reg & LDO_LOCAL_ENABLE_MASK))
+ return 1;
+ else if (vreg->type == REGULATOR_TYPE_VS) {
+ if ((vreg->ctrl_reg & VS_CTRL_ENABLE_MASK) == VS_CTRL_ENABLE)
+ return 1;
+ else if ((vreg->ctrl_reg & VS_CTRL_ENABLE_MASK)
+ == VS_CTRL_DISABLE)
+ return 0;
+ }
+
+ return REGULATOR_IS_EN(vreg->pmr_reg)
+ || ((vreg->pmr_reg & VREG_PMR_PIN_CTRL_ALL_MASK)
+ != VREG_PMR_PIN_CTRL_ALL_MASKED);
+}
+
+static int pm8901_vreg_is_enabled(struct regulator_dev *dev)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+
+ return _pm8901_vreg_is_enabled(vreg);
+}
+
+static int pm8901_ldo_disable(struct regulator_dev *dev)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+ struct pm8901_chip *chip = vreg->chip;
+ int rc;
+
+ /* Disassert local enable bit in CTRL register. */
+ rc = pm8901_vreg_write(chip, vreg->ctrl_addr, 0, LDO_LOCAL_ENABLE_MASK,
+ &vreg->ctrl_reg);
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ /* Disassert enable bit in PMR register. */
+ rc = pm8901_vreg_disable(dev);
+
+ return rc;
+}
+
+static int pm8901_pldo_set_voltage(struct pm8901_chip *chip,
+ struct pm8901_vreg *vreg, int uV)
+{
+ int vmin, rc = 0;
+ unsigned vprog, fine_step;
+ u8 range_ext, range_sel, fine_step_reg;
+
+ if (uV < PLDO_LOW_UV_MIN || uV > PLDO_HIGH_UV_MAX)
+ return -EINVAL;
+
+ if (uV < PLDO_LOW_UV_MAX + PLDO_LOW_FINE_STEP_UV) {
+ vmin = PLDO_LOW_UV_MIN;
+ fine_step = PLDO_LOW_FINE_STEP_UV;
+ range_ext = 0;
+ range_sel = LDO_TEST_RANGE_SEL_MASK;
+ } else if (uV < PLDO_NORM_UV_MAX + PLDO_NORM_FINE_STEP_UV) {
+ vmin = PLDO_NORM_UV_MIN;
+ fine_step = PLDO_NORM_FINE_STEP_UV;
+ range_ext = 0;
+ range_sel = 0;
+ } else {
+ vmin = PLDO_HIGH_UV_MIN;
+ fine_step = PLDO_HIGH_FINE_STEP_UV;
+ range_ext = LDO_TEST_RANGE_EXT_MASK;
+ range_sel = 0;
+ }
+
+ vprog = (uV - vmin) / fine_step;
+ fine_step_reg = (vprog & 1) << LDO_TEST_FINE_STEP_SHIFT;
+ vprog >>= 1;
+
+ /*
+ * Disable program voltage update if range extension, range select,
+ * or fine step have changed and the regulator is enabled.
+ */
+ if (_pm8901_vreg_is_enabled(vreg) &&
+ (((range_ext ^ vreg->test_reg[4]) & LDO_TEST_RANGE_EXT_MASK)
+ || ((range_sel ^ vreg->test_reg[2]) & LDO_TEST_RANGE_SEL_MASK)
+ || ((fine_step_reg ^ vreg->test_reg[2])
+ & LDO_TEST_FINE_STEP_MASK))) {
+ rc = pm8901_vreg_write(chip, vreg->test_addr,
+ REGULATOR_BANK_SEL(2) | REGULATOR_BANK_WRITE,
+ REGULATOR_BANK_MASK | LDO_TEST_VPROG_UPDATE_MASK,
+ &vreg->test_reg[2]);
+ if (rc)
+ goto bail;
+ }
+
+ /* Write new voltage. */
+ rc = pm8901_vreg_write(chip, vreg->ctrl_addr, vprog,
+ LDO_CTRL_VPROG_MASK, &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ /* Write range extension. */
+ rc = pm8901_vreg_write(chip, vreg->test_addr,
+ range_ext | REGULATOR_BANK_SEL(4)
+ | REGULATOR_BANK_WRITE,
+ LDO_TEST_RANGE_EXT_MASK | REGULATOR_BANK_MASK,
+ &vreg->test_reg[4]);
+ if (rc)
+ goto bail;
+
+ /* Write fine step, range select and program voltage update. */
+ rc = pm8901_vreg_write(chip, vreg->test_addr,
+ fine_step_reg | range_sel | REGULATOR_BANK_SEL(2)
+ | REGULATOR_BANK_WRITE | LDO_TEST_VPROG_UPDATE_MASK,
+ LDO_TEST_FINE_STEP_MASK | LDO_TEST_RANGE_SEL_MASK
+ | REGULATOR_BANK_MASK | LDO_TEST_VPROG_UPDATE_MASK,
+ &vreg->test_reg[2]);
+bail:
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+static int pm8901_nldo_set_voltage(struct pm8901_chip *chip,
+ struct pm8901_vreg *vreg, int uV)
+{
+ unsigned vprog, fine_step_reg;
+ int rc;
+
+ if (uV < NLDO_UV_MIN || uV > NLDO_UV_MAX)
+ return -EINVAL;
+
+ vprog = (uV - NLDO_UV_MIN) / NLDO_FINE_STEP_UV;
+ fine_step_reg = (vprog & 1) << LDO_TEST_FINE_STEP_SHIFT;
+ vprog >>= 1;
+
+ /* Write new voltage. */
+ rc = pm8901_vreg_write(chip, vreg->ctrl_addr, vprog,
+ LDO_CTRL_VPROG_MASK, &vreg->ctrl_reg);
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ /* Write fine step. */
+ rc = pm8901_vreg_write(chip, vreg->test_addr,
+ fine_step_reg | REGULATOR_BANK_SEL(2)
+ | REGULATOR_BANK_WRITE | LDO_TEST_VPROG_UPDATE_MASK,
+ LDO_TEST_FINE_STEP_MASK | REGULATOR_BANK_MASK
+ | LDO_TEST_VPROG_UPDATE_MASK,
+ &vreg->test_reg[2]);
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+static int pm8901_ldo_set_voltage(struct regulator_dev *dev,
+ int min_uV, int max_uV, unsigned *selector)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+ struct pm8901_chip *chip = vreg->chip;
+
+ if (vreg->is_nmos)
+ return pm8901_nldo_set_voltage(chip, vreg, min_uV);
+ else
+ return pm8901_pldo_set_voltage(chip, vreg, min_uV);
+}
+
+static int pm8901_pldo_get_voltage(struct pm8901_vreg *vreg)
+{
+ int vmin, fine_step;
+ u8 range_ext, range_sel, vprog, fine_step_reg;
+
+ fine_step_reg = vreg->test_reg[2] & LDO_TEST_FINE_STEP_MASK;
+ range_sel = vreg->test_reg[2] & LDO_TEST_RANGE_SEL_MASK;
+ range_ext = vreg->test_reg[4] & LDO_TEST_RANGE_EXT_MASK;
+ vprog = vreg->ctrl_reg & LDO_CTRL_VPROG_MASK;
+
+ vprog = (vprog << 1) | (fine_step_reg >> LDO_TEST_FINE_STEP_SHIFT);
+
+ if (range_sel) {
+ /* low range mode */
+ fine_step = PLDO_LOW_FINE_STEP_UV;
+ vmin = PLDO_LOW_UV_MIN;
+ } else if (!range_ext) {
+ /* normal mode */
+ fine_step = PLDO_NORM_FINE_STEP_UV;
+ vmin = PLDO_NORM_UV_MIN;
+ } else {
+ /* high range mode */
+ fine_step = PLDO_HIGH_FINE_STEP_UV;
+ vmin = PLDO_HIGH_UV_MIN;
+ }
+
+ return fine_step * vprog + vmin;
+}
+
+static int pm8901_nldo_get_voltage(struct pm8901_vreg *vreg)
+{
+ u8 vprog, fine_step_reg;
+
+ fine_step_reg = vreg->test_reg[2] & LDO_TEST_FINE_STEP_MASK;
+ vprog = vreg->ctrl_reg & LDO_CTRL_VPROG_MASK;
+
+ vprog = (vprog << 1) | (fine_step_reg >> LDO_TEST_FINE_STEP_SHIFT);
+
+ return NLDO_FINE_STEP_UV * vprog + NLDO_UV_MIN;
+}
+
+static int pm8901_ldo_get_voltage(struct regulator_dev *dev)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+
+ if (vreg->is_nmos)
+ return pm8901_nldo_get_voltage(vreg);
+ else
+ return pm8901_pldo_get_voltage(vreg);
+}
+
+/*
+ * Optimum mode programming:
+ * REGULATOR_MODE_FAST: Go to HPM (highest priority)
+ * REGULATOR_MODE_STANDBY: Go to pin ctrl mode if there are any pin ctrl
+ * votes, else go to LPM
+ *
+ * Pin ctrl mode voting via regulator set_mode:
+ * REGULATOR_MODE_IDLE: Go to pin ctrl mode if the optimum mode is LPM, else
+ * go to HPM
+ * REGULATOR_MODE_NORMAL: Go to LPM if it is the optimum mode, else go to HPM
+ */
+static int pm8901_vreg_set_mode(struct regulator_dev *dev, unsigned int mode)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+ struct pm8901_chip *chip = vreg->chip;
+ unsigned optimum = vreg->optimum;
+ unsigned pc_vote = vreg->pc_vote;
+ unsigned mode_initialized = vreg->mode_initialized;
+ u8 val = 0;
+ int rc = 0;
+
+ /* Determine new mode to go into. */
+ switch (mode) {
+ case REGULATOR_MODE_FAST:
+ val = VREG_PMR_STATE_HPM;
+ optimum = mode;
+ mode_initialized = 1;
+ break;
+
+ case REGULATOR_MODE_STANDBY:
+ if (pc_vote)
+ val = VREG_PMR_STATE_PIN_CTRL;
+ else
+ val = VREG_PMR_STATE_LPM;
+ optimum = mode;
+ mode_initialized = 1;
+ break;
+
+ case REGULATOR_MODE_IDLE:
+ if (pc_vote++)
+ goto done; /* already taken care of */
+
+ if (mode_initialized && optimum == REGULATOR_MODE_FAST)
+ val = VREG_PMR_STATE_HPM;
+ else
+ val = VREG_PMR_STATE_PIN_CTRL;
+ break;
+
+ case REGULATOR_MODE_NORMAL:
+ if (pc_vote && --pc_vote)
+ goto done; /* already taken care of */
+
+ if (optimum == REGULATOR_MODE_STANDBY)
+ val = VREG_PMR_STATE_LPM;
+ else
+ val = VREG_PMR_STATE_HPM;
+ break;
+
+ default:
+ pr_err("%s: unknown mode, mode=%u\n", __func__, mode);
+ return -EINVAL;
+ }
+
+ /* Set pin control bits based on new mode. */
+ pm8901_vreg_select_pin_ctrl(vreg, &val);
+
+ /* Only apply mode setting to hardware if currently enabled. */
+ if (pm8901_vreg_is_enabled(dev))
+ rc = pm8901_vreg_write(chip, vreg->pmr_addr, val,
+ VREG_PMR_STATE_MASK | VREG_PMR_PIN_CTRL_ALL_MASK,
+ &vreg->pmr_reg);
+
+ if (rc) {
+ print_write_error(vreg, rc, __func__);
+ return rc;
+ }
+
+done:
+ vreg->mode_initialized = mode_initialized;
+ vreg->optimum = optimum;
+ vreg->pc_vote = pc_vote;
+
+ return 0;
+}
+
+static unsigned int pm8901_vreg_get_mode(struct regulator_dev *dev)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+ int pin_mask = VREG_PMR_CTRL_PIN0_MASK | VREG_PMR_CTRL_PIN1_MASK
+ | VREG_PMR_CTRL_PIN2_MASK;
+
+ if (!vreg->mode_initialized && vreg->pc_vote)
+ return REGULATOR_MODE_IDLE;
+ else if (((vreg->pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_OFF)
+ && ((vreg->pmr_reg & pin_mask) != pin_mask))
+ return REGULATOR_MODE_IDLE;
+ else if (((vreg->pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_LPM)
+ && ((vreg->pmr_reg & pin_mask) != pin_mask))
+ return REGULATOR_MODE_IDLE;
+ else if (vreg->optimum == REGULATOR_MODE_FAST)
+ return REGULATOR_MODE_FAST;
+ else if (vreg->pc_vote)
+ return REGULATOR_MODE_IDLE;
+ else if (vreg->optimum == REGULATOR_MODE_STANDBY)
+ return REGULATOR_MODE_STANDBY;
+ return REGULATOR_MODE_FAST;
+}
+
+unsigned int pm8901_vreg_get_optimum_mode(struct regulator_dev *dev,
+ int input_uV, int output_uV, int load_uA)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+
+ if (load_uA <= 0) {
+ /*
+ * pm8901_vreg_get_optimum_mode is being called before consumers
+ * have specified their load currents via
+ * regulator_set_optimum_mode. Return whatever the existing mode
+ * is.
+ */
+ return pm8901_vreg_get_mode(dev);
+ }
+
+ if (load_uA >= vreg->hpm_min_load)
+ return REGULATOR_MODE_FAST;
+ return REGULATOR_MODE_STANDBY;
+}
+
+static int pm8901_smps_set_voltage(struct regulator_dev *dev,
+ int min_uV, int max_uV, unsigned *selector)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+ struct pm8901_chip *chip = vreg->chip;
+ int rc;
+ u8 val, band;
+
+ if (IS_PMIC_8901_V1(pm8901_rev(chip)))
+ min_uV = PMIC_8901_V1_SCALE(min_uV);
+
+ if (min_uV < SMPS_BAND_1_UV_MIN || min_uV > SMPS_BAND_3_UV_MAX)
+ return -EINVAL;
+
+ /* Round down for set points in the gaps between bands. */
+ if (min_uV > SMPS_BAND_1_UV_MAX && min_uV < SMPS_BAND_2_UV_MIN)
+ min_uV = SMPS_BAND_1_UV_MAX;
+ else if (min_uV > SMPS_BAND_2_UV_MAX
+ && min_uV < SMPS_BAND_3_UV_SETPOINT_MIN)
+ min_uV = SMPS_BAND_2_UV_MAX;
+
+ if (min_uV < SMPS_BAND_2_UV_MIN) {
+ val = ((min_uV - SMPS_BAND_1_UV_MIN) / SMPS_BAND_1_UV_STEP);
+ val = PM8901_SMPS_BAND_1_COMPENSATE(val);
+ band = SMPS_VCTRL_BAND_1;
+ } else if (min_uV < SMPS_BAND_3_UV_SETPOINT_MIN) {
+ val = ((min_uV - SMPS_BAND_2_UV_MIN) / SMPS_BAND_2_UV_STEP);
+ band = SMPS_VCTRL_BAND_2;
+ } else {
+ val = ((min_uV - SMPS_BAND_3_UV_MIN) / SMPS_BAND_3_UV_STEP);
+ band = SMPS_VCTRL_BAND_3;
+ }
+
+ rc = pm8901_vreg_write(chip, vreg->ctrl_addr, band | val,
+ SMPS_VCTRL_BAND_MASK | SMPS_VCTRL_VPROG_MASK,
+ &vreg->ctrl_reg);
+ if (rc)
+ goto bail;
+
+ rc = pm8901_vreg_write(chip, vreg->pfm_ctrl_addr, band | val,
+ SMPS_VCTRL_BAND_MASK | SMPS_VCTRL_VPROG_MASK,
+ &vreg->pfm_ctrl_reg);
+bail:
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+static int pm8901_smps_get_voltage(struct regulator_dev *dev)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+ struct pm8901_chip *chip = vreg->chip;
+ u8 vprog, band;
+ int ret = 0;
+
+ if ((vreg->pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_LPM) {
+ vprog = vreg->pfm_ctrl_reg & SMPS_VCTRL_VPROG_MASK;
+ band = vreg->pfm_ctrl_reg & SMPS_VCTRL_BAND_MASK;
+ } else {
+ vprog = vreg->ctrl_reg & SMPS_VCTRL_VPROG_MASK;
+ band = vreg->ctrl_reg & SMPS_VCTRL_BAND_MASK;
+ }
+
+ if (band == SMPS_VCTRL_BAND_1)
+ ret = vprog * SMPS_BAND_1_UV_STEP + SMPS_BAND_1_UV_MIN;
+ else if (band == SMPS_VCTRL_BAND_2)
+ ret = vprog * SMPS_BAND_2_UV_STEP + SMPS_BAND_2_UV_MIN;
+ else
+ ret = vprog * SMPS_BAND_3_UV_STEP + SMPS_BAND_3_UV_MIN;
+
+ if (IS_PMIC_8901_V1(pm8901_rev(chip)))
+ ret = PMIC_8901_V1_SCALE_INV(ret);
+
+ return ret;
+}
+
+static int pm8901_vs_enable(struct regulator_dev *dev)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+ struct pm8901_chip *chip = vreg->chip;
+ int rc;
+
+ /* Assert enable bit in PMR register. */
+ rc = pm8901_vreg_enable(dev);
+
+ /* Make sure that switch is controlled via PMR register */
+ rc = pm8901_vreg_write(chip, vreg->ctrl_addr, VS_CTRL_USE_PMR,
+ VS_CTRL_ENABLE_MASK, &vreg->ctrl_reg);
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+static int pm8901_vs_disable(struct regulator_dev *dev)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+ struct pm8901_chip *chip = vreg->chip;
+ int rc;
+
+ /* Disassert enable bit in PMR register. */
+ rc = pm8901_vreg_disable(dev);
+
+ /* Make sure that switch is controlled via PMR register */
+ rc = pm8901_vreg_write(chip, vreg->ctrl_addr, VS_CTRL_USE_PMR,
+ VS_CTRL_ENABLE_MASK, &vreg->ctrl_reg);
+ if (rc)
+ print_write_error(vreg, rc, __func__);
+
+ return rc;
+}
+
+static int pm8901_mpp_enable(struct regulator_dev *dev)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+ int out_val;
+ int rc;
+
+ out_val = (vreg->pdata->active_high
+ ? PM_MPP_DOUT_CTL_HIGH : PM_MPP_DOUT_CTL_LOW);
+
+ rc = pm8901_mpp_config(vreg->mpp_id, PM_MPP_TYPE_D_OUTPUT,
+ PM8901_MPP_DIG_LEVEL_VPH, out_val);
+
+ if (rc)
+ pr_err("%s: pm8901_mpp_config failed, rc=%d\n", __func__, rc);
+ else
+ vreg->state = 1;
+
+ return rc;
+}
+
+static int pm8901_mpp_disable(struct regulator_dev *dev)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+ int out_val;
+ int rc;
+
+ out_val = (vreg->pdata->active_high
+ ? PM_MPP_DOUT_CTL_LOW : PM_MPP_DOUT_CTL_HIGH);
+
+ rc = pm8901_mpp_config(vreg->mpp_id, PM_MPP_TYPE_D_OUTPUT,
+ PM8901_MPP_DIG_LEVEL_VPH, out_val);
+
+ if (rc)
+ pr_err("%s: pm8901_mpp_config failed, rc=%d\n", __func__, rc);
+ else
+ vreg->state = 0;
+
+ return rc;
+}
+
+static int pm8901_mpp_is_enabled(struct regulator_dev *dev)
+{
+ struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
+ return vreg->state;
+}
+
+static struct regulator_ops pm8901_ldo_ops = {
+ .enable = pm8901_vreg_enable,
+ .disable = pm8901_ldo_disable,
+ .is_enabled = pm8901_vreg_is_enabled,
+ .set_voltage = pm8901_ldo_set_voltage,
+ .get_voltage = pm8901_ldo_get_voltage,
+ .set_mode = pm8901_vreg_set_mode,
+ .get_mode = pm8901_vreg_get_mode,
+ .get_optimum_mode = pm8901_vreg_get_optimum_mode,
+};
+
+static struct regulator_ops pm8901_smps_ops = {
+ .enable = pm8901_vreg_enable,
+ .disable = pm8901_vreg_disable,
+ .is_enabled = pm8901_vreg_is_enabled,
+ .set_voltage = pm8901_smps_set_voltage,
+ .get_voltage = pm8901_smps_get_voltage,
+ .set_mode = pm8901_vreg_set_mode,
+ .get_mode = pm8901_vreg_get_mode,
+ .get_optimum_mode = pm8901_vreg_get_optimum_mode,
+};
+
+static struct regulator_ops pm8901_vs_ops = {
+ .enable = pm8901_vs_enable,
+ .disable = pm8901_vs_disable,
+ .is_enabled = pm8901_vreg_is_enabled,
+ .set_mode = pm8901_vreg_set_mode,
+ .get_mode = pm8901_vreg_get_mode,
+};
+
+static struct regulator_ops pm8901_mpp_ops = {
+ .enable = pm8901_mpp_enable,
+ .disable = pm8901_mpp_disable,
+ .is_enabled = pm8901_mpp_is_enabled,
+};
+
+#define VREG_DESCRIP(_id, _name, _ops) \
+ [_id] = { \
+ .name = _name, \
+ .id = _id, \
+ .ops = _ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .owner = THIS_MODULE, \
+ }
+
+static struct regulator_desc pm8901_vreg_descrip[] = {
+ VREG_DESCRIP(PM8901_VREG_ID_L0, "8901_l0", &pm8901_ldo_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_L1, "8901_l1", &pm8901_ldo_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_L2, "8901_l2", &pm8901_ldo_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_L3, "8901_l3", &pm8901_ldo_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_L4, "8901_l4", &pm8901_ldo_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_L5, "8901_l5", &pm8901_ldo_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_L6, "8901_l6", &pm8901_ldo_ops),
+
+ VREG_DESCRIP(PM8901_VREG_ID_S0, "8901_s0", &pm8901_smps_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_S1, "8901_s1", &pm8901_smps_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_S2, "8901_s2", &pm8901_smps_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_S3, "8901_s3", &pm8901_smps_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_S4, "8901_s4", &pm8901_smps_ops),
+
+ VREG_DESCRIP(PM8901_VREG_ID_MPP0, "8901_mpp0", &pm8901_mpp_ops),
+
+ VREG_DESCRIP(PM8901_VREG_ID_LVS0, "8901_lvs0", &pm8901_vs_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_LVS1, "8901_lvs1", &pm8901_vs_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_LVS2, "8901_lvs2", &pm8901_vs_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_LVS3, "8901_lvs3", &pm8901_vs_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_MVS0, "8901_mvs0", &pm8901_vs_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_USB_OTG, "8901_usb_otg", &pm8901_vs_ops),
+ VREG_DESCRIP(PM8901_VREG_ID_HDMI_MVS, "8901_hdmi_mvs", &pm8901_vs_ops),
+};
+
+static int pm8901_init_ldo(struct pm8901_chip *chip, struct pm8901_vreg *vreg)
+{
+ int rc = 0, i;
+ u8 bank;
+
+ /* Store current regulator register values. */
+ for (i = 0; i < LDO_TEST_BANKS; i++) {
+ bank = REGULATOR_BANK_SEL(i);
+ rc = pm8901_write(chip, vreg->test_addr, &bank, 1);
+ if (rc)
+ goto bail;
+
+ rc = pm8901_read(chip, vreg->test_addr, &vreg->test_reg[i], 1);
+ if (rc)
+ goto bail;
+
+ vreg->test_reg[i] |= REGULATOR_BANK_WRITE;
+ }
+
+ /* Set pull down enable based on platform data. */
+ rc = pm8901_vreg_write(chip, vreg->ctrl_addr,
+ (vreg->pdata->pull_down_enable ? LDO_PULL_DOWN_ENABLE : 0),
+ LDO_PULL_DOWN_ENABLE_MASK, &vreg->ctrl_reg);
+bail:
+ return rc;
+}
+
+static int pm8901_init_smps(struct pm8901_chip *chip, struct pm8901_vreg *vreg)
+{
+ int rc;
+
+ /* Store current regulator register values. */
+ rc = pm8901_read(chip, vreg->pfm_ctrl_addr,
+ &vreg->pfm_ctrl_reg, 1);
+ if (rc)
+ goto bail;
+
+ rc = pm8901_read(chip, vreg->pwr_cnfg_addr,
+ &vreg->pwr_cnfg_reg, 1);
+ if (rc)
+ goto bail;
+
+ /* Set pull down enable based on platform data. */
+ rc = pm8901_vreg_write(chip, vreg->pwr_cnfg_addr,
+ (vreg->pdata->pull_down_enable ? SMPS_PULL_DOWN_ENABLE : 0),
+ SMPS_PULL_DOWN_ENABLE_MASK, &vreg->pwr_cnfg_reg);
+
+bail:
+ return rc;
+}
+
+static int pm8901_init_vs(struct pm8901_chip *chip, struct pm8901_vreg *vreg)
+{
+ int rc = 0;
+
+ /* Set pull down enable based on platform data. */
+ rc = pm8901_vreg_write(chip, vreg->ctrl_addr,
+ (vreg->pdata->pull_down_enable ? VS_PULL_DOWN_ENABLE : 0),
+ VS_PULL_DOWN_ENABLE_MASK, &vreg->ctrl_reg);
+
+ return rc;
+}
+
+static int pm8901_init_regulator(struct pm8901_chip *chip,
+ struct pm8901_vreg *vreg)
+{
+ int rc;
+
+ /* Store current regulator register values. */
+ if (vreg->type != REGULATOR_TYPE_MPP) {
+ rc = pm8901_read(chip, vreg->ctrl_addr, &vreg->ctrl_reg, 1);
+ if (rc)
+ goto bail;
+
+ rc = pm8901_read(chip, vreg->pmr_addr, &vreg->pmr_reg, 1);
+ if (rc)
+ goto bail;
+ }
+
+ /* Set initial mode based on hardware state. */
+ if ((vreg->pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_LPM)
+ vreg->optimum = REGULATOR_MODE_STANDBY;
+ else
+ vreg->optimum = REGULATOR_MODE_FAST;
+
+ vreg->mode_initialized = 0;
+
+ if (vreg->type == REGULATOR_TYPE_LDO)
+ rc = pm8901_init_ldo(chip, vreg);
+ else if (vreg->type == REGULATOR_TYPE_SMPS)
+ rc = pm8901_init_smps(chip, vreg);
+ else if (vreg->type == REGULATOR_TYPE_VS)
+ rc = pm8901_init_vs(chip, vreg);
+bail:
+ if (rc)
+ pr_err("%s: pm8901_read/write failed; initial register states "
+ "unknown, rc=%d\n", __func__, rc);
+
+ return rc;
+}
+
+static int __devinit pm8901_vreg_probe(struct platform_device *pdev)
+{
+ struct regulator_desc *rdesc;
+ struct pm8901_chip *chip;
+ struct pm8901_vreg *vreg;
+ const char *reg_name = NULL;
+ int rc = 0;
+
+ if (pdev == NULL)
+ return -EINVAL;
+
+ if (pdev->id >= 0 && pdev->id < PM8901_VREG_MAX) {
+ chip = dev_get_drvdata(pdev->dev.parent);
+ rdesc = &pm8901_vreg_descrip[pdev->id];
+ vreg = &pm8901_vreg[pdev->id];
+ vreg->pdata = pdev->dev.platform_data;
+ vreg->chip = chip;
+ reg_name = pm8901_vreg_descrip[pdev->id].name;
+
+ rc = pm8901_init_regulator(chip, vreg);
+ if (rc)
+ goto bail;
+
+ /* Disallow idle and normal modes if pin control isn't set. */
+ if (vreg->pdata->pin_ctrl == 0)
+ vreg->pdata->init_data.constraints.valid_modes_mask
+ &= ~(REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE);
+
+ vreg->rdev = regulator_register(rdesc, &pdev->dev,
+ &vreg->pdata->init_data, vreg);
+ if (IS_ERR(vreg->rdev)) {
+ rc = PTR_ERR(vreg->rdev);
+ pr_err("%s: regulator_register failed for %s, rc=%d\n",
+ __func__, reg_name, rc);
+ }
+ } else {
+ rc = -ENODEV;
+ }
+
+bail:
+ if (rc)
+ pr_err("%s: error for %s, rc=%d\n", __func__, reg_name, rc);
+
+ return rc;
+}
+
+static int __devexit pm8901_vreg_remove(struct platform_device *pdev)
+{
+ regulator_unregister(pm8901_vreg[pdev->id].rdev);
+ return 0;
+}
+
+static struct platform_driver pm8901_vreg_driver = {
+ .probe = pm8901_vreg_probe,
+ .remove = __devexit_p(pm8901_vreg_remove),
+ .driver = {
+ .name = "pm8901-regulator",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pm8901_vreg_init(void)
+{
+ return platform_driver_register(&pm8901_vreg_driver);
+}
+
+static void __exit pm8901_vreg_exit(void)
+{
+ platform_driver_unregister(&pm8901_vreg_driver);
+}
+
+static void print_write_error(struct pm8901_vreg *vreg, int rc,
+ const char *func)
+{
+ const char *reg_name = NULL;
+ ptrdiff_t id = vreg - pm8901_vreg;
+
+ if (id >= 0 && id < PM8901_VREG_MAX)
+ reg_name = pm8901_vreg_descrip[id].name;
+ pr_err("%s: pm8901_vreg_write failed for %s, rc=%d\n",
+ func, reg_name, rc);
+}
+
+subsys_initcall(pm8901_vreg_init);
+module_exit(pm8901_vreg_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PMIC8901 regulator driver");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:pm8901-regulator");