Initial Contribution
msm-2.6.38: tag AU_LINUX_ANDROID_GINGERBREAD.02.03.04.00.142
Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index b3692e6..852cff5 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1308,6 +1308,44 @@
Choose M here to compile it as a module. The module will be
called msm_serial_hs.
+config SERIAL_MSM_CLOCK_CONTROL
+ bool "Allow tty clients to make clock requests to msm uarts."
+ depends on SERIAL_MSM=y
+ default y
+ help
+ Provides an interface for tty clients to request the msm uart clock
+ to be turned on or off for power savings.
+
+config SERIAL_MSM_RX_WAKEUP
+ bool "Wakeup the msm uart clock on GPIO activity."
+ depends on SERIAL_MSM_CLOCK_CONTROL
+ default n
+ help
+ Requires SERIAL_MSM_CLOCK_CONTROL. Wake up the uart while the uart
+ clock is off, using a wakeup GPIO.
+
+config SERIAL_MSM_HSL
+ tristate "MSM UART High Speed : Legacy mode Serial Driver"
+ depends on ARM && ARCH_MSM
+ select SERIAL_CORE
+ default n
+ help
+ Select this module to enable MSM high speed UART driver.
+
+config SERIAL_MSM_HSL_CONSOLE
+ bool "MSM High speed serial legacy mode console support"
+ depends on SERIAL_MSM_HSL=y
+ select SERIAL_CORE_CONSOLE
+ default n
+
+config SERIAL_BCM_BT_LPM
+ tristate "Broadcom Bluetooth Low Power Mode"
+ depends on ARM && ARCH_MSM
+ select SERIAL_CORE
+ default n
+ help
+ Select this module for Broadcom Bluetooth low power management.
+
config SERIAL_VT8500
bool "VIA VT8500 on-chip serial port support"
depends on ARM && ARCH_VT8500
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index cb2628f..122c992 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -76,6 +76,8 @@
obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o
obj-$(CONFIG_SERIAL_MSM) += msm_serial.o
obj-$(CONFIG_SERIAL_MSM_HS) += msm_serial_hs.o
+obj-$(CONFIG_SERIAL_MSM_HSL) += msm_serial_hs_lite.o
+obj-$(CONFIG_MSM_SERIAL_DEBUGGER) += msm_serial_debugger.o
obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index e6ba838..e6646ab 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -1,9 +1,9 @@
/*
- * Driver for msm7k serial device and console
+ * drivers/serial/msm_serial.c - driver for msm7k serial device and console
*
* Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
* Author: Robert Love <rlove@google.com>
- * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -25,122 +25,243 @@
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/init.h>
+#include <linux/delay.h>
#include <linux/console.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
+#include <linux/nmi.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
-#include <linux/delay.h>
-
+#include <linux/pm_runtime.h>
+#include <mach/msm_serial_pdata.h>
#include "msm_serial.h"
+
+#ifdef CONFIG_SERIAL_MSM_CLOCK_CONTROL
+enum msm_clk_states_e {
+ MSM_CLK_PORT_OFF, /* uart port not in use */
+ MSM_CLK_OFF, /* clock enabled */
+ MSM_CLK_REQUEST_OFF, /* disable after TX flushed */
+ MSM_CLK_ON, /* clock disabled */
+};
+#endif
+
+#ifdef CONFIG_SERIAL_MSM_RX_WAKEUP
+/* optional low power wakeup, typically on a GPIO RX irq */
+struct msm_wakeup {
+ int irq; /* < 0 indicates low power wakeup disabled */
+ unsigned char ignore; /* bool */
+
+ /* bool: inject char into rx tty on wakeup */
+ unsigned char inject_rx;
+ char rx_to_inject;
+};
+#endif
+
struct msm_port {
struct uart_port uart;
char name[16];
struct clk *clk;
- struct clk *pclk;
unsigned int imr;
- unsigned int *gsbi_base;
- int is_uartdm;
- unsigned int old_snap_state;
+#ifdef CONFIG_SERIAL_MSM_CLOCK_CONTROL
+ enum msm_clk_states_e clk_state;
+ struct hrtimer clk_off_timer;
+ ktime_t clk_off_delay;
+#endif
+#ifdef CONFIG_SERIAL_MSM_RX_WAKEUP
+ struct msm_wakeup wakeup;
+#endif
};
-static inline void wait_for_xmitr(struct uart_port *port, int bits)
+#define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port)
+#define is_console(port) ((port)->cons && \
+ (port)->cons->index == (port)->line)
+
+
+static inline void msm_write(struct uart_port *port, unsigned int val,
+ unsigned int off)
{
- if (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY))
- while ((msm_read(port, UART_ISR) & bits) != bits)
- cpu_relax();
+ __raw_writel(val, port->membase + off);
}
+static inline unsigned int msm_read(struct uart_port *port, unsigned int off)
+{
+ return __raw_readl(port->membase + off);
+}
+
+#ifdef CONFIG_SERIAL_MSM_RX_WAKEUP
+static inline unsigned int use_low_power_wakeup(struct msm_port *msm_port)
+{
+ return (msm_port->wakeup.irq >= 0);
+}
+#endif
+
static void msm_stop_tx(struct uart_port *port)
{
struct msm_port *msm_port = UART_TO_MSM(port);
+ clk_enable(msm_port->clk);
+
msm_port->imr &= ~UART_IMR_TXLEV;
msm_write(port, msm_port->imr, UART_IMR);
+
+ clk_disable(msm_port->clk);
}
static void msm_start_tx(struct uart_port *port)
{
struct msm_port *msm_port = UART_TO_MSM(port);
+ clk_enable(msm_port->clk);
+
msm_port->imr |= UART_IMR_TXLEV;
msm_write(port, msm_port->imr, UART_IMR);
+
+ clk_disable(msm_port->clk);
}
static void msm_stop_rx(struct uart_port *port)
{
struct msm_port *msm_port = UART_TO_MSM(port);
+ clk_enable(msm_port->clk);
+
msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
msm_write(port, msm_port->imr, UART_IMR);
+
+ clk_disable(msm_port->clk);
}
static void msm_enable_ms(struct uart_port *port)
{
struct msm_port *msm_port = UART_TO_MSM(port);
+ clk_enable(msm_port->clk);
+
msm_port->imr |= UART_IMR_DELTA_CTS;
msm_write(port, msm_port->imr, UART_IMR);
+
+ clk_disable(msm_port->clk);
}
-static void handle_rx_dm(struct uart_port *port, unsigned int misr)
-{
- struct tty_struct *tty = port->state->port.tty;
- unsigned int sr;
- int count = 0;
+#ifdef CONFIG_SERIAL_MSM_CLOCK_CONTROL
+/* turn clock off if TX buffer is empty, otherwise reschedule */
+static enum hrtimer_restart msm_serial_clock_off(struct hrtimer *timer) {
+ struct msm_port *msm_port = container_of(timer, struct msm_port,
+ clk_off_timer);
+ struct uart_port *port = &msm_port->uart;
+ struct circ_buf *xmit = &port->state->xmit;
+ unsigned long flags;
+ int ret = HRTIMER_NORESTART;
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ if (msm_port->clk_state == MSM_CLK_REQUEST_OFF) {
+ if (uart_circ_empty(xmit)) {
+ struct msm_port *msm_port = UART_TO_MSM(port);
+ clk_disable(msm_port->clk);
+ msm_port->clk_state = MSM_CLK_OFF;
+#ifdef CONFIG_SERIAL_MSM_RX_WAKEUP
+ if (use_low_power_wakeup(msm_port)) {
+ msm_port->wakeup.ignore = 1;
+ enable_irq(msm_port->wakeup.irq);
+ }
+#endif
+ } else {
+ hrtimer_forward_now(timer, msm_port->clk_off_delay);
+ ret = HRTIMER_RESTART;
+ }
+ }
+
+ spin_unlock_irqrestore(&port->lock, flags);
+
+ return HRTIMER_NORESTART;
+}
+
+/* request to turn off uart clock once pending TX is flushed */
+void msm_serial_clock_request_off(struct uart_port *port) {
+ unsigned long flags;
struct msm_port *msm_port = UART_TO_MSM(port);
- if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
- port->icount.overrun++;
- tty_insert_flip_char(tty, 0, TTY_OVERRUN);
- msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
+ spin_lock_irqsave(&port->lock, flags);
+ if (msm_port->clk_state == MSM_CLK_ON) {
+ msm_port->clk_state = MSM_CLK_REQUEST_OFF;
+ /* turn off TX later. unfortunately not all msm uart's have a
+ * TXDONE available, and TXLEV does not wait until completely
+ * flushed, so a timer is our only option
+ */
+ hrtimer_start(&msm_port->clk_off_timer,
+ msm_port->clk_off_delay, HRTIMER_MODE_REL);
}
-
- if (misr & UART_IMR_RXSTALE) {
- count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
- msm_port->old_snap_state;
- msm_port->old_snap_state = 0;
- } else {
- count = 4 * (msm_read(port, UART_RFWR));
- msm_port->old_snap_state += count;
- }
-
- /* TODO: Precise error reporting */
-
- port->icount.rx += count;
-
- while (count > 0) {
- unsigned int c;
-
- sr = msm_read(port, UART_SR);
- if ((sr & UART_SR_RX_READY) == 0) {
- msm_port->old_snap_state -= count;
- break;
- }
- c = msm_read(port, UARTDM_RF);
- if (sr & UART_SR_RX_BREAK) {
- port->icount.brk++;
- if (uart_handle_break(port))
- continue;
- } else if (sr & UART_SR_PAR_FRAME_ERR)
- port->icount.frame++;
-
- /* TODO: handle sysrq */
- tty_insert_flip_string(tty, (char *) &c,
- (count > 4) ? 4 : count);
- count -= 4;
- }
-
- tty_flip_buffer_push(tty);
- if (misr & (UART_IMR_RXSTALE))
- msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
- msm_write(port, 0xFFFFFF, UARTDM_DMRX);
- msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
+ spin_unlock_irqrestore(&port->lock, flags);
}
+/* request to immediately turn on uart clock.
+ * ignored if there is a pending off request, unless force = 1.
+ */
+void msm_serial_clock_on(struct uart_port *port, int force) {
+ unsigned long flags;
+ struct msm_port *msm_port = UART_TO_MSM(port);
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ switch (msm_port->clk_state) {
+ case MSM_CLK_OFF:
+ clk_enable(msm_port->clk);
+#ifdef CONFIG_SERIAL_MSM_RX_WAKEUP
+ if (use_low_power_wakeup(msm_port))
+ disable_irq(msm_port->wakeup.irq);
+#endif
+ force = 1;
+ case MSM_CLK_REQUEST_OFF:
+ if (force) {
+ hrtimer_try_to_cancel(&msm_port->clk_off_timer);
+ msm_port->clk_state = MSM_CLK_ON;
+ }
+ break;
+ case MSM_CLK_ON: break;
+ case MSM_CLK_PORT_OFF: break;
+ }
+
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+#endif
+
+#ifdef CONFIG_SERIAL_MSM_RX_WAKEUP
+static irqreturn_t msm_rx_irq(int irq, void *dev_id)
+{
+ struct uart_port *port = dev_id;
+ struct msm_port *msm_port = UART_TO_MSM(port);
+ int inject_wakeup = 0;
+
+ spin_lock(&port->lock);
+
+ if (msm_port->clk_state == MSM_CLK_OFF) {
+ /* ignore the first irq - it is a pending irq that occured
+ * before enable_irq() */
+ if (msm_port->wakeup.ignore)
+ msm_port->wakeup.ignore = 0;
+ else
+ inject_wakeup = 1;
+ }
+
+ msm_serial_clock_on(port, 0);
+
+ /* we missed an rx while asleep - it must be a wakeup indicator
+ */
+ if (inject_wakeup) {
+ struct tty_struct *tty = port->state->port.tty;
+ tty_insert_flip_char(tty, WAKE_UP_IND, TTY_NORMAL);
+ tty_flip_buffer_push(tty);
+ }
+
+ spin_unlock(&port->lock);
+ return IRQ_HANDLED;
+}
+#endif
+
static void handle_rx(struct uart_port *port)
{
struct tty_struct *tty = port->state->port.tty;
@@ -189,12 +310,6 @@
tty_flip_buffer_push(tty);
}
-static void reset_dm_count(struct uart_port *port)
-{
- wait_for_xmitr(port, UART_ISR_TX_READY);
- msm_write(port, 1, UARTDM_NCF_TX);
-}
-
static void handle_tx(struct uart_port *port)
{
struct circ_buf *xmit = &port->state->xmit;
@@ -202,18 +317,11 @@
int sent_tx;
if (port->x_char) {
- if (msm_port->is_uartdm)
- reset_dm_count(port);
-
- msm_write(port, port->x_char,
- msm_port->is_uartdm ? UARTDM_TF : UART_TF);
+ msm_write(port, port->x_char, UART_TF);
port->icount.tx++;
port->x_char = 0;
}
- if (msm_port->is_uartdm)
- reset_dm_count(port);
-
while (msm_read(port, UART_SR) & UART_SR_TX_READY) {
if (uart_circ_empty(xmit)) {
/* disable tx interrupts */
@@ -221,17 +329,22 @@
msm_write(port, msm_port->imr, UART_IMR);
break;
}
- msm_write(port, xmit->buf[xmit->tail],
- msm_port->is_uartdm ? UARTDM_TF : UART_TF);
- if (msm_port->is_uartdm)
- reset_dm_count(port);
+ msm_write(port, xmit->buf[xmit->tail], UART_TF);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
sent_tx = 1;
}
+#ifdef CONFIG_SERIAL_MSM_CLOCK_CONTROL
+ if (sent_tx && msm_port->clk_state == MSM_CLK_REQUEST_OFF)
+ /* new TX - restart the timer */
+ if (hrtimer_try_to_cancel(&msm_port->clk_off_timer) == 1)
+ hrtimer_start(&msm_port->clk_off_timer,
+ msm_port->clk_off_delay, HRTIMER_MODE_REL);
+#endif
+
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
}
@@ -250,21 +363,19 @@
unsigned int misr;
spin_lock(&port->lock);
+ clk_enable(msm_port->clk);
misr = msm_read(port, UART_MISR);
msm_write(port, 0, UART_IMR); /* disable interrupt */
- if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
- if (msm_port->is_uartdm)
- handle_rx_dm(port, misr);
- else
- handle_rx(port);
- }
+ if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE))
+ handle_rx(port);
if (misr & UART_IMR_TXLEV)
handle_tx(port);
if (misr & UART_IMR_DELTA_CTS)
handle_delta_cts(port);
msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
+ clk_disable(msm_port->clk);
spin_unlock(&port->lock);
return IRQ_HANDLED;
@@ -272,7 +383,14 @@
static unsigned int msm_tx_empty(struct uart_port *port)
{
- return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
+ unsigned int ret;
+ struct msm_port *msm_port = UART_TO_MSM(port);
+
+ clk_enable(msm_port->clk);
+ ret = (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
+ clk_disable(msm_port->clk);
+
+ return ret;
}
static unsigned int msm_get_mctrl(struct uart_port *port)
@@ -280,21 +398,13 @@
return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
}
-
-static void msm_reset(struct uart_port *port)
-{
- /* reset everything */
- msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
- msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
- msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
- msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
- msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
- msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
-}
-
-void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
+static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
unsigned int mr;
+ struct msm_port *msm_port = UART_TO_MSM(port);
+
+ clk_enable(msm_port->clk);
+
mr = msm_read(port, UART_MR1);
if (!(mctrl & TIOCM_RTS)) {
@@ -305,20 +415,27 @@
mr |= UART_MR1_RX_RDY_CTL;
msm_write(port, mr, UART_MR1);
}
+
+ clk_disable(msm_port->clk);
}
static void msm_break_ctl(struct uart_port *port, int break_ctl)
{
+ struct msm_port *msm_port = UART_TO_MSM(port);
+
+ clk_enable(msm_port->clk);
+
if (break_ctl)
msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
else
msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
+
+ clk_disable(msm_port->clk);
}
-static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
+static void msm_set_baud_rate(struct uart_port *port, unsigned int baud)
{
unsigned int baud_code, rxstale, watermark;
- struct msm_port *msm_port = UART_TO_MSM(port);
switch (baud) {
case 300:
@@ -368,14 +485,10 @@
case 115200:
default:
baud_code = UART_CSR_115200;
- baud = 115200;
rxstale = 31;
break;
}
- if (msm_port->is_uartdm)
- msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
-
msm_write(port, baud_code, UART_CSR);
/* RX stale watermark */
@@ -390,27 +503,57 @@
/* set TX watermark */
msm_write(port, 10, UART_TFWR);
-
- if (msm_port->is_uartdm) {
- msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
- msm_write(port, 0xFFFFFF, UARTDM_DMRX);
- msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
- }
-
- return baud;
}
+static void msm_reset(struct uart_port *port)
+{
+ /* reset everything */
+ msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
+ msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
+ msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
+ msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
+ msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
+ msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
+}
static void msm_init_clock(struct uart_port *port)
{
struct msm_port *msm_port = UART_TO_MSM(port);
clk_enable(msm_port->clk);
- if (!IS_ERR(msm_port->pclk))
- clk_enable(msm_port->pclk);
- msm_serial_set_mnd_regs(port);
+
+#ifdef CONFIG_SERIAL_MSM_CLOCK_CONTROL
+ msm_port->clk_state = MSM_CLK_ON;
+#endif
+
+ if (port->uartclk == 19200000) {
+ /* clock is TCXO (19.2MHz) */
+ msm_write(port, 0x06, UART_MREG);
+ msm_write(port, 0xF1, UART_NREG);
+ msm_write(port, 0x0F, UART_DREG);
+ msm_write(port, 0x1A, UART_MNDREG);
+ } else {
+ /* clock must be TCXO/4 */
+ msm_write(port, 0x18, UART_MREG);
+ msm_write(port, 0xF6, UART_NREG);
+ msm_write(port, 0x0F, UART_DREG);
+ msm_write(port, 0x0A, UART_MNDREG);
+ }
}
+static void msm_deinit_clock(struct uart_port *port)
+{
+ struct msm_port *msm_port = UART_TO_MSM(port);
+
+#ifdef CONFIG_SERIAL_MSM_CLOCK_CONTROL
+ if (msm_port->clk_state != MSM_CLK_OFF)
+ clk_disable(msm_port->clk);
+ msm_port->clk_state = MSM_CLK_PORT_OFF;
+#else
+ clk_disable(msm_port->clk);
+#endif
+
+}
static int msm_startup(struct uart_port *port)
{
struct msm_port *msm_port = UART_TO_MSM(port);
@@ -425,7 +568,15 @@
if (unlikely(ret))
return ret;
+ if (unlikely(irq_set_irq_wake(port->irq, 1))) {
+ free_irq(port->irq, port);
+ return -ENXIO;
+ }
+
+#ifndef CONFIG_PM_RUNTIME
msm_init_clock(port);
+#endif
+ pm_runtime_get_sync(port->dev);
if (likely(port->fifosize > 12))
rfr_level = port->fifosize - 12;
@@ -448,31 +599,29 @@
msm_write(port, data, UART_IPR);
}
- data = 0;
- if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) {
- msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
- msm_reset(port);
- data = UART_CR_TX_ENABLE;
- }
+ msm_reset(port);
- data |= UART_CR_RX_ENABLE;
- msm_write(port, data, UART_CR); /* enable TX & RX */
-
- /* Make sure IPR is not 0 to start with*/
- if (msm_port->is_uartdm)
- msm_write(port, UART_IPR_STALE_LSB, UART_IPR);
+ msm_write(port, 0x05, UART_CR); /* enable TX & RX */
/* turn on RX and CTS interrupts */
msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
UART_IMR_CURRENT_CTS;
-
- if (msm_port->is_uartdm) {
- msm_write(port, 0xFFFFFF, UARTDM_DMRX);
- msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
- msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
- }
-
msm_write(port, msm_port->imr, UART_IMR);
+
+#ifdef CONFIG_SERIAL_MSM_RX_WAKEUP
+ if (use_low_power_wakeup(msm_port)) {
+ ret = irq_set_irq_wake(msm_port->wakeup.irq, 1);
+ if (unlikely(ret))
+ return ret;
+ ret = request_irq(msm_port->wakeup.irq, msm_rx_irq,
+ IRQF_TRIGGER_FALLING,
+ "msm_serial_wakeup", msm_port);
+ if (unlikely(ret))
+ return ret;
+ disable_irq(msm_port->wakeup.irq);
+ }
+#endif
+
return 0;
}
@@ -480,12 +629,25 @@
{
struct msm_port *msm_port = UART_TO_MSM(port);
+ clk_enable(msm_port->clk);
+
msm_port->imr = 0;
msm_write(port, 0, UART_IMR); /* disable interrupts */
clk_disable(msm_port->clk);
free_irq(port->irq, port);
+
+#ifdef CONFIG_SERIAL_MSM_RX_WAKEUP
+ if (use_low_power_wakeup(msm_port)) {
+ irq_set_irq_wake(msm_port->wakeup.irq, 0);
+ free_irq(msm_port->wakeup.irq, msm_port);
+ }
+#endif
+#ifndef CONFIG_PM_RUNTIME
+ msm_deinit_clock(port);
+#endif
+ pm_runtime_put_sync(port->dev);
}
static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
@@ -493,14 +655,14 @@
{
unsigned long flags;
unsigned int baud, mr;
+ struct msm_port *msm_port = UART_TO_MSM(port);
spin_lock_irqsave(&port->lock, flags);
+ clk_enable(msm_port->clk);
/* calculate and set baud rate */
baud = uart_get_baud_rate(port, termios, old, 300, 115200);
- baud = msm_set_baud_rate(port, baud);
- if (tty_termios_baud_rate(termios))
- tty_termios_encode_baud_rate(termios, baud, baud);
+ msm_set_baud_rate(port, baud);
/* calculate parity */
mr = msm_read(port, UART_MR2);
@@ -560,6 +722,7 @@
uart_update_timeout(port, termios->c_cflag, baud);
+ clk_disable(msm_port->clk);
spin_unlock_irqrestore(&port->lock, flags);
}
@@ -571,105 +734,48 @@
static void msm_release_port(struct uart_port *port)
{
struct platform_device *pdev = to_platform_device(port->dev);
- struct msm_port *msm_port = UART_TO_MSM(port);
- struct resource *uart_resource;
- struct resource *gsbi_resource;
+ struct resource *resource;
resource_size_t size;
- uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (unlikely(!uart_resource))
+ resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (unlikely(!resource))
return;
- size = resource_size(uart_resource);
+ size = resource->end - resource->start + 1;
release_mem_region(port->mapbase, size);
iounmap(port->membase);
port->membase = NULL;
-
- if (msm_port->gsbi_base) {
- iowrite32(GSBI_PROTOCOL_IDLE, msm_port->gsbi_base +
- GSBI_CONTROL);
-
- gsbi_resource = platform_get_resource_byname(pdev,
- IORESOURCE_MEM,
- "gsbi_resource");
-
- if (unlikely(!gsbi_resource))
- return;
-
- size = resource_size(gsbi_resource);
- release_mem_region(gsbi_resource->start, size);
- iounmap(msm_port->gsbi_base);
- msm_port->gsbi_base = NULL;
- }
}
static int msm_request_port(struct uart_port *port)
{
- struct msm_port *msm_port = UART_TO_MSM(port);
struct platform_device *pdev = to_platform_device(port->dev);
- struct resource *uart_resource;
- struct resource *gsbi_resource;
+ struct resource *resource;
resource_size_t size;
- int ret;
- uart_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "uart_resource");
- if (unlikely(!uart_resource))
+ resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (unlikely(!resource))
return -ENXIO;
+ size = resource->end - resource->start + 1;
- size = resource_size(uart_resource);
-
- if (!request_mem_region(port->mapbase, size, "msm_serial"))
+ if (unlikely(!request_mem_region(port->mapbase, size, "msm_serial")))
return -EBUSY;
port->membase = ioremap(port->mapbase, size);
if (!port->membase) {
- ret = -EBUSY;
- goto fail_release_port;
- }
-
- gsbi_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "gsbi_resource");
- /* Is this a GSBI-based port? */
- if (gsbi_resource) {
- size = resource_size(gsbi_resource);
-
- if (!request_mem_region(gsbi_resource->start, size,
- "msm_serial")) {
- ret = -EBUSY;
- goto fail_release_port;
- }
-
- msm_port->gsbi_base = ioremap(gsbi_resource->start, size);
- if (!msm_port->gsbi_base) {
- ret = -EBUSY;
- goto fail_release_gsbi;
- }
+ release_mem_region(port->mapbase, size);
+ return -EBUSY;
}
return 0;
-
-fail_release_gsbi:
- release_mem_region(gsbi_resource->start, size);
-fail_release_port:
- release_mem_region(port->mapbase, size);
- return ret;
}
static void msm_config_port(struct uart_port *port, int flags)
{
- struct msm_port *msm_port = UART_TO_MSM(port);
- int ret;
if (flags & UART_CONFIG_TYPE) {
port->type = PORT_MSM;
- ret = msm_request_port(port);
- if (ret)
- return;
+ msm_request_port(port);
}
-
- if (msm_port->is_uartdm)
- iowrite32(GSBI_PROTOCOL_UART, msm_port->gsbi_base +
- GSBI_CONTROL);
}
static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
@@ -684,22 +790,20 @@
static void msm_power(struct uart_port *port, unsigned int state,
unsigned int oldstate)
{
+#ifndef CONFIG_SERIAL_MSM_CLOCK_CONTROL
struct msm_port *msm_port = UART_TO_MSM(port);
switch (state) {
case 0:
clk_enable(msm_port->clk);
- if (!IS_ERR(msm_port->pclk))
- clk_enable(msm_port->pclk);
break;
case 3:
clk_disable(msm_port->clk);
- if (!IS_ERR(msm_port->pclk))
- clk_disable(msm_port->pclk);
break;
default:
printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
}
+#endif
}
static struct uart_ops msm_uart_pops = {
@@ -728,7 +832,7 @@
.iotype = UPIO_MEM,
.ops = &msm_uart_pops,
.flags = UPF_BOOT_AUTOCONF,
- .fifosize = 64,
+ .fifosize = 512,
.line = 0,
},
},
@@ -737,7 +841,7 @@
.iotype = UPIO_MEM,
.ops = &msm_uart_pops,
.flags = UPF_BOOT_AUTOCONF,
- .fifosize = 64,
+ .fifosize = 512,
.line = 1,
},
},
@@ -754,23 +858,56 @@
#define UART_NR ARRAY_SIZE(msm_uart_ports)
-static inline struct uart_port *get_port_from_line(unsigned int line)
+static inline struct uart_port * get_port_from_line(unsigned int line)
{
return &msm_uart_ports[line].uart;
}
#ifdef CONFIG_SERIAL_MSM_CONSOLE
+/*
+ * Wait for transmitter & holding register to empty
+ * Derived from wait_for_xmitr in 8250 serial driver by Russell King
+ */
+static inline void wait_for_xmitr(struct uart_port *port, int bits)
+{
+ unsigned int status, mr, tmout = 10000;
+
+ /* Wait up to 10ms for the character(s) to be sent. */
+ do {
+ status = msm_read(port, UART_SR);
+
+ if (--tmout == 0)
+ break;
+ udelay(1);
+ } while ((status & bits) != bits);
+
+ mr = msm_read(port, UART_MR1);
+
+ /* Wait up to 1s for flow control if necessary */
+ if (mr & UART_MR1_CTS_CTL) {
+ unsigned int tmout;
+ for (tmout = 1000000; tmout; tmout--) {
+ unsigned int isr = msm_read(port, UART_ISR);
+
+ /* CTS input is active lo */
+ if (!(isr & UART_IMR_CURRENT_CTS))
+ break;
+ udelay(1);
+ touch_nmi_watchdog();
+ }
+ }
+}
+
+
static void msm_console_putchar(struct uart_port *port, int c)
{
- struct msm_port *msm_port = UART_TO_MSM(port);
+ /* This call can incur significant delay if CTS flowcontrol is enabled
+ * on port and no serial cable is attached.
+ */
+ wait_for_xmitr(port, UART_SR_TX_READY);
- if (msm_port->is_uartdm)
- reset_dm_count(port);
-
- while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
- ;
- msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
+ msm_write(port, c, UART_TF);
}
static void msm_console_write(struct console *co, const char *s,
@@ -778,35 +915,48 @@
{
struct uart_port *port;
struct msm_port *msm_port;
+ int locked;
BUG_ON(co->index < 0 || co->index >= UART_NR);
port = get_port_from_line(co->index);
msm_port = UART_TO_MSM(port);
- spin_lock(&port->lock);
+ /* not pretty, but we can end up here via various convoluted paths */
+ if (port->sysrq || oops_in_progress)
+ locked = spin_trylock(&port->lock);
+ else {
+ locked = 1;
+ spin_lock(&port->lock);
+ }
+
uart_console_write(port, s, count, msm_console_putchar);
- spin_unlock(&port->lock);
+
+ if (locked)
+ spin_unlock(&port->lock);
}
static int __init msm_console_setup(struct console *co, char *options)
{
struct uart_port *port;
- struct msm_port *msm_port;
int baud, flow, bits, parity;
if (unlikely(co->index >= UART_NR || co->index < 0))
return -ENXIO;
port = get_port_from_line(co->index);
- msm_port = UART_TO_MSM(port);
if (unlikely(!port->membase))
return -ENXIO;
port->cons = co;
+ pm_runtime_get_noresume(port->dev);
+
+#ifndef CONFIG_PM_RUNTIME
msm_init_clock(port);
+#endif
+ pm_runtime_resume(port->dev);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
@@ -823,11 +973,6 @@
msm_reset(port);
- if (msm_port->is_uartdm) {
- msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
- msm_write(port, UART_CR_TX_ENABLE, UART_CR);
- }
-
printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
return uart_set_options(port, co, baud, parity, bits, flow);
@@ -845,7 +990,7 @@
.data = &msm_uart_driver,
};
-#define MSM_CONSOLE (&msm_console)
+#define MSM_CONSOLE &msm_console
#else
#define MSM_CONSOLE NULL
@@ -865,6 +1010,9 @@
struct resource *resource;
struct uart_port *port;
int irq;
+#ifdef CONFIG_SERIAL_MSM_RX_WAKEUP
+ struct msm_serial_platform_data *pdata = pdev->dev.platform_data;
+#endif
if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
return -ENXIO;
@@ -875,32 +1023,14 @@
port->dev = &pdev->dev;
msm_port = UART_TO_MSM(port);
- if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "gsbi_resource"))
- msm_port->is_uartdm = 1;
- else
- msm_port->is_uartdm = 0;
-
- if (msm_port->is_uartdm) {
- msm_port->clk = clk_get(&pdev->dev, "gsbi_uart_clk");
- msm_port->pclk = clk_get(&pdev->dev, "gsbi_pclk");
- } else {
- msm_port->clk = clk_get(&pdev->dev, "uart_clk");
- msm_port->pclk = ERR_PTR(-ENOENT);
- }
-
- if (unlikely(IS_ERR(msm_port->clk) || (IS_ERR(msm_port->pclk) &&
- msm_port->is_uartdm)))
- return PTR_ERR(msm_port->clk);
-
- if (msm_port->is_uartdm)
- clk_set_rate(msm_port->clk, 7372800);
-
+ msm_port->clk = clk_get(&pdev->dev, "uart_clk");
+ if (unlikely(IS_ERR(msm_port->clk)))
+ return PTR_ERR(msm_port->clk);
port->uartclk = clk_get_rate(msm_port->clk);
- printk(KERN_INFO "uartclk = %d\n", port->uartclk);
+ if (!port->uartclk)
+ port->uartclk = 19200000;
-
- resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "uart_resource");
+ resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!resource))
return -ENXIO;
port->mapbase = resource->start;
@@ -912,6 +1042,29 @@
platform_set_drvdata(pdev, port);
+
+#ifdef CONFIG_SERIAL_MSM_RX_WAKEUP
+ if (pdata == NULL)
+ msm_port->wakeup.irq = -1;
+ else {
+ msm_port->wakeup.irq = pdata->wakeup_irq;
+ msm_port->wakeup.ignore = 1;
+ msm_port->wakeup.inject_rx = pdata->inject_rx_on_wakeup;
+ msm_port->wakeup.rx_to_inject = pdata->rx_to_inject;
+
+ if (unlikely(msm_port->wakeup.irq <= 0))
+ return -EINVAL;
+ }
+#endif
+
+#ifdef CONFIG_SERIAL_MSM_CLOCK_CONTROL
+ msm_port->clk_state = MSM_CLK_PORT_OFF;
+ hrtimer_init(&msm_port->clk_off_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+ msm_port->clk_off_timer.function = msm_serial_clock_off;
+ msm_port->clk_off_delay = ktime_set(0, 1000000); /* 1 ms */
+#endif
+
+ pm_runtime_enable(port->dev);
return uart_add_one_port(&msm_uart_driver, port);
}
@@ -919,16 +1072,84 @@
{
struct msm_port *msm_port = platform_get_drvdata(pdev);
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+
clk_put(msm_port->clk);
return 0;
}
+#ifdef CONFIG_PM
+static int msm_serial_suspend(struct device *dev)
+{
+ struct uart_port *port;
+ struct platform_device *pdev = to_platform_device(dev);
+ port = get_port_from_line(pdev->id);
+
+ if (port) {
+ uart_suspend_port(&msm_uart_driver, port);
+ if (is_console(port))
+ msm_deinit_clock(port);
+ }
+
+ return 0;
+}
+
+static int msm_serial_resume(struct device *dev)
+{
+ struct uart_port *port;
+ struct platform_device *pdev = to_platform_device(dev);
+ port = get_port_from_line(pdev->id);
+
+ if (port) {
+ if (is_console(port))
+ msm_init_clock(port);
+ uart_resume_port(&msm_uart_driver, port);
+ }
+
+ return 0;
+}
+#else
+#define msm_serial_suspend NULL
+#define msm_serial_resume NULL
+#endif
+
+static int msm_serial_runtime_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct uart_port *port;
+ port = get_port_from_line(pdev->id);
+
+ dev_dbg(dev, "pm_runtime: suspending\n");
+ msm_deinit_clock(port);
+ return 0;
+}
+
+static int msm_serial_runtime_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct uart_port *port;
+ port = get_port_from_line(pdev->id);
+
+ dev_dbg(dev, "pm_runtime: resuming\n");
+ msm_init_clock(port);
+ return 0;
+}
+
+static struct dev_pm_ops msm_serial_dev_pm_ops = {
+ .suspend = msm_serial_suspend,
+ .resume = msm_serial_resume,
+ .runtime_suspend = msm_serial_runtime_suspend,
+ .runtime_resume = msm_serial_runtime_resume,
+};
+
static struct platform_driver msm_platform_driver = {
.remove = msm_serial_remove,
.driver = {
.name = "msm_serial",
.owner = THIS_MODULE,
+ .pm = &msm_serial_dev_pm_ops,
},
};
@@ -963,4 +1184,4 @@
MODULE_AUTHOR("Robert Love <rlove@google.com>");
MODULE_DESCRIPTION("Driver for msm7x serial device");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_serial.h
index e4acef5..65d0e30 100644
--- a/drivers/tty/serial/msm_serial.h
+++ b/drivers/tty/serial/msm_serial.h
@@ -46,11 +46,14 @@
#define UART_CSR_19200 0xBB
#define UART_CSR_14400 0xAA
#define UART_CSR_9600 0x99
+#define UART_CSR_7200 0x88
#define UART_CSR_4800 0x77
#define UART_CSR_2400 0x55
#define UART_CSR_1200 0x44
#define UART_CSR_600 0x33
#define UART_CSR_300 0x22
+#define UART_CSR_150 0x11
+#define UART_CSR_75 0x00
#define UART_TF 0x000C
#define UARTDM_TF 0x0070
@@ -128,60 +131,4 @@
#define UARTDM_NCF_TX 0x40
#define UARTDM_RX_TOTAL_SNAP 0x38
-#define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port)
-
-static inline
-void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
-{
- __raw_writel(val, port->membase + off);
-}
-
-static inline
-unsigned int msm_read(struct uart_port *port, unsigned int off)
-{
- return __raw_readl(port->membase + off);
-}
-
-/*
- * Setup the MND registers to use the TCXO clock.
- */
-static inline void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
-{
- msm_write(port, 0x06, UART_MREG);
- msm_write(port, 0xF1, UART_NREG);
- msm_write(port, 0x0F, UART_DREG);
- msm_write(port, 0x1A, UART_MNDREG);
-}
-
-/*
- * Setup the MND registers to use the TCXO clock divided by 4.
- */
-static inline void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
-{
- msm_write(port, 0x18, UART_MREG);
- msm_write(port, 0xF6, UART_NREG);
- msm_write(port, 0x0F, UART_DREG);
- msm_write(port, 0x0A, UART_MNDREG);
-}
-
-static inline
-void msm_serial_set_mnd_regs_from_uartclk(struct uart_port *port)
-{
- if (port->uartclk == 19200000)
- msm_serial_set_mnd_regs_tcxo(port);
- else
- msm_serial_set_mnd_regs_tcxoby4(port);
-}
-
-/*
- * TROUT has a specific defect that makes it report it's uartclk
- * as 19.2Mhz (TCXO) when it's actually 4.8Mhz (TCXO/4). This special
- * cases TROUT to use the right clock.
- */
-#ifdef CONFIG_MACH_TROUT
-#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_tcxoby4
-#else
-#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_from_uartclk
-#endif
-
#endif /* __DRIVERS_SERIAL_MSM_SERIAL_H */
diff --git a/drivers/tty/serial/msm_serial_debugger.c b/drivers/tty/serial/msm_serial_debugger.c
new file mode 100644
index 0000000..88b6784
--- /dev/null
+++ b/drivers/tty/serial/msm_serial_debugger.c
@@ -0,0 +1,421 @@
+/*
+ * drivers/serial/msm_serial_debuger.c
+ *
+ * Serial Debugger Interface for MSM7K
+ *
+ * Copyright (C) 2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdarg.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/console.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/kernel_debugger.h>
+#include <linux/kernel_stat.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+
+#include <mach/system.h>
+#include <mach/fiq.h>
+
+#include "msm_serial.h"
+
+static unsigned int debug_port_base;
+static int debug_signal_irq;
+static struct clk *debug_clk;
+static int debug_enable;
+static int debugger_enable;
+static struct {
+ unsigned int base;
+ int irq;
+ struct device *clk_device;
+ int signal_irq;
+} init_data;
+
+static inline void msm_write(unsigned int val, unsigned int off)
+{
+ __raw_writel(val, debug_port_base + off);
+}
+
+static inline unsigned int msm_read(unsigned int off)
+{
+ return __raw_readl(debug_port_base + off);
+}
+
+static void debug_port_init(void)
+{
+ /* reset everything */
+ msm_write(UART_CR_CMD_RESET_RX, UART_CR);
+ msm_write(UART_CR_CMD_RESET_TX, UART_CR);
+ msm_write(UART_CR_CMD_RESET_ERR, UART_CR);
+ msm_write(UART_CR_CMD_RESET_BREAK_INT, UART_CR);
+ msm_write(UART_CR_CMD_RESET_CTS, UART_CR);
+ msm_write(UART_CR_CMD_SET_RFR, UART_CR);
+
+ /* setup clock dividers */
+ if (clk_get_rate(debug_clk) == 19200000) {
+ /* clock is TCXO (19.2MHz) */
+ msm_write(0x06, UART_MREG);
+ msm_write(0xF1, UART_NREG);
+ msm_write(0x0F, UART_DREG);
+ msm_write(0x1A, UART_MNDREG);
+ } else {
+ /* clock must be TCXO/4 */
+ msm_write(0x18, UART_MREG);
+ msm_write(0xF6, UART_NREG);
+ msm_write(0x0F, UART_DREG);
+ msm_write(0x0A, UART_MNDREG);
+ }
+
+ msm_write(UART_CSR_115200, UART_CSR);
+
+ /* rx interrupt on every character -- keep it simple */
+ msm_write(0, UART_RFWR);
+
+ /* enable TX and RX */
+ msm_write(0x05, UART_CR);
+
+ /* enable RX interrupt */
+ msm_write(UART_IMR_RXLEV, UART_IMR);
+}
+
+static inline int debug_getc(void)
+{
+ if (msm_read(UART_SR) & UART_SR_RX_READY) {
+ return msm_read(UART_RF);
+ } else {
+ return -1;
+ }
+}
+
+static inline void debug_putc(unsigned int c)
+{
+ while (!(msm_read(UART_SR) & UART_SR_TX_READY)) ;
+ msm_write(c, UART_TF);
+}
+
+static inline void debug_flush(void)
+{
+ while (!(msm_read(UART_SR) & UART_SR_TX_EMPTY)) ;
+}
+
+static void debug_puts(char *s)
+{
+ unsigned c;
+ while ((c = *s++)) {
+ if (c == '\n')
+ debug_putc('\r');
+ debug_putc(c);
+ }
+}
+
+static void debug_prompt(void)
+{
+ debug_puts("debug> ");
+}
+
+int log_buf_copy(char *dest, int idx, int len);
+static void dump_kernel_log(void)
+{
+ char buf[1024];
+ int idx = 0;
+ int ret;
+ int saved_oip;
+
+ /* setting oops_in_progress prevents log_buf_copy()
+ * from trying to take a spinlock which will make it
+ * very unhappy in some cases...
+ */
+ saved_oip = oops_in_progress;
+ oops_in_progress = 1;
+ for (;;) {
+ ret = log_buf_copy(buf, idx, 1023);
+ if (ret <= 0)
+ break;
+ buf[ret] = 0;
+ debug_puts(buf);
+ idx += ret;
+ }
+ oops_in_progress = saved_oip;
+}
+
+static char *mode_name(unsigned cpsr)
+{
+ switch (cpsr & MODE_MASK) {
+ case USR_MODE: return "USR";
+ case FIQ_MODE: return "FIQ";
+ case IRQ_MODE: return "IRQ";
+ case SVC_MODE: return "SVC";
+ case ABT_MODE: return "ABT";
+ case UND_MODE: return "UND";
+ case SYSTEM_MODE: return "SYS";
+ default: return "???";
+ }
+}
+
+#define DEBUG_MAX 64
+static char debug_cmd[DEBUG_MAX];
+static int debug_busy;
+static int debug_abort;
+
+static int debug_printf(void *cookie, const char *fmt, ...)
+{
+ char buf[256];
+ va_list ap;
+
+ va_start(ap, fmt);
+ vsnprintf(buf, 128, fmt, ap);
+ va_end(ap);
+
+ debug_puts(buf);
+ return debug_abort;
+}
+
+/* Safe outside fiq context */
+static int debug_printf_nfiq(void *cookie, const char *fmt, ...)
+{
+ char buf[256];
+ va_list ap;
+ unsigned long irq_flags;
+
+ va_start(ap, fmt);
+ vsnprintf(buf, 128, fmt, ap);
+ va_end(ap);
+
+ local_irq_save(irq_flags);
+ debug_puts(buf);
+ debug_flush();
+ local_irq_restore(irq_flags);
+ return debug_abort;
+}
+
+#define dprintf(fmt...) debug_printf(0, fmt)
+
+unsigned int last_irqs[NR_IRQS];
+
+static void dump_irqs(void)
+{
+ int n;
+ dprintf("irqnr total since-last status name\n");
+ for (n = 1; n < NR_IRQS; n++) {
+ struct irqaction *act = irq_desc[n].action;
+ if (!act && !kstat_cpu(0).irqs[n])
+ continue;
+ dprintf("%5d: %10u %11u %8x %s\n", n,
+ kstat_cpu(0).irqs[n],
+ kstat_cpu(0).irqs[n] - last_irqs[n],
+ irq_desc[n].status,
+ (act && act->name) ? act->name : "???");
+ last_irqs[n] = kstat_cpu(0).irqs[n];
+ }
+}
+
+static void debug_exec(const char *cmd, unsigned *regs)
+{
+ if (!strcmp(cmd, "pc")) {
+ dprintf(" pc %08x cpsr %08x mode %s\n",
+ regs[15], regs[16], mode_name(regs[16]));
+ } else if (!strcmp(cmd, "regs")) {
+ dprintf(" r0 %08x r1 %08x r2 %08x r3 %08x\n",
+ regs[0], regs[1], regs[2], regs[3]);
+ dprintf(" r4 %08x r5 %08x r6 %08x r7 %08x\n",
+ regs[4], regs[5], regs[6], regs[7]);
+ dprintf(" r8 %08x r9 %08x r10 %08x r11 %08x mode %s\n",
+ regs[8], regs[9], regs[10], regs[11],
+ mode_name(regs[16]));
+ dprintf(" ip %08x sp %08x lr %08x pc %08x cpsr %08x\n",
+ regs[10], regs[13], regs[14], regs[15], regs[16]);
+ } else if (!strcmp(cmd, "reboot")) {
+ if (msm_hw_reset_hook)
+ msm_hw_reset_hook();
+ } else if (!strcmp(cmd, "irqs")) {
+ dump_irqs();
+ } else if (!strcmp(cmd, "kmsg")) {
+ dump_kernel_log();
+ } else if (!strcmp(cmd, "version")) {
+ dprintf("%s\n", linux_banner);
+ } else {
+ if (debug_busy) {
+ dprintf("command processor busy. trying to abort.\n");
+ debug_abort = -1;
+ } else {
+ strcpy(debug_cmd, cmd);
+ debug_busy = 1;
+ }
+ msm_trigger_irq(debug_signal_irq);
+ return;
+ }
+ debug_prompt();
+}
+
+static irqreturn_t debug_irq(int irq, void *dev)
+{
+ if (debug_busy) {
+ struct kdbg_ctxt ctxt;
+
+ ctxt.printf = debug_printf_nfiq;
+ kernel_debugger(&ctxt, debug_cmd);
+ debug_prompt();
+
+ debug_busy = 0;
+ }
+ return IRQ_HANDLED;
+}
+
+static char debug_buf[DEBUG_MAX];
+static int debug_count;
+
+static void debug_fiq(void *data, void *regs)
+{
+ int c;
+ static int last_c;
+
+ while ((c = debug_getc()) != -1) {
+ if (!debug_enable) {
+ if ((c == 13) || (c == 10)) {
+ debug_enable = true;
+ debug_count = 0;
+ debug_prompt();
+ }
+ } else if ((c >= ' ') && (c < 127)) {
+ if (debug_count < (DEBUG_MAX - 1)) {
+ debug_buf[debug_count++] = c;
+ debug_putc(c);
+ }
+ } else if ((c == 8) || (c == 127)) {
+ if (debug_count > 0) {
+ debug_count--;
+ debug_putc(8);
+ debug_putc(' ');
+ debug_putc(8);
+ }
+ } else if ((c == 13) || (c == 10)) {
+ if (c == '\r' || (c == '\n' && last_c != '\r')) {
+ debug_putc('\r');
+ debug_putc('\n');
+ }
+ if (debug_count) {
+ debug_buf[debug_count] = 0;
+ debug_count = 0;
+ debug_exec(debug_buf, regs);
+ } else {
+ debug_prompt();
+ }
+ }
+ last_c = c;
+ }
+ debug_flush();
+}
+
+#if defined(CONFIG_MSM_SERIAL_DEBUGGER_CONSOLE)
+static void debug_console_write(struct console *co,
+ const char *s, unsigned int count)
+{
+ unsigned long irq_flags;
+
+ /* disable irq's while TXing outside of FIQ context */
+ local_irq_save(irq_flags);
+ while (count--) {
+ if (*s == '\n')
+ debug_putc('\r');
+ debug_putc(*s++);
+ }
+ debug_flush();
+ local_irq_restore(irq_flags);
+}
+
+static struct console msm_serial_debug_console = {
+ .name = "debug_console",
+ .write = debug_console_write,
+ .flags = CON_PRINTBUFFER | CON_ANYTIME | CON_ENABLED,
+};
+#endif
+
+void msm_serial_debug_enable(int enable) {
+ debug_enable = enable;
+}
+
+void msm_serial_debug_init(unsigned int base, int irq,
+ struct device *clk_device, int signal_irq)
+{
+ int ret;
+ void *port;
+
+ debug_clk = clk_get(clk_device, "uart_clk");
+ if (debug_clk)
+ clk_enable(debug_clk);
+
+ port = ioremap(base, 4096);
+ if (!port)
+ return;
+
+ init_data.base = base;
+ init_data.irq = irq;
+ init_data.clk_device = clk_device;
+ init_data.signal_irq = signal_irq;
+ debug_port_base = (unsigned int) port;
+ debug_signal_irq = signal_irq;
+ debug_port_init();
+
+ debug_prompt();
+
+ msm_fiq_select(irq);
+ msm_fiq_set_handler(debug_fiq, 0);
+ msm_fiq_enable(irq);
+
+ ret = request_irq(signal_irq, debug_irq,
+ IRQF_TRIGGER_RISING, "debug", 0);
+ if (ret)
+ printk(KERN_ERR
+ "serial_debugger: could not install signal_irq");
+
+#if defined(CONFIG_MSM_SERIAL_DEBUGGER_CONSOLE)
+ register_console(&msm_serial_debug_console);
+#endif
+ debugger_enable = 1;
+}
+static int msm_serial_debug_remove(const char *val, struct kernel_param *kp)
+{
+ int ret;
+ static int pre_stat = 1;
+ ret = param_set_bool(val, kp);
+ if (ret)
+ return ret;
+
+ if (pre_stat == *(int *)kp->arg)
+ return 0;
+
+ pre_stat = *(int *)kp->arg;
+
+ if (*(int *)kp->arg) {
+ msm_serial_debug_init(init_data.base, init_data.irq,
+ init_data.clk_device, init_data.signal_irq);
+ printk(KERN_INFO "enable FIQ serial debugger\n");
+ return 0;
+ }
+
+#if defined(CONFIG_MSM_SERIAL_DEBUGGER_CONSOLE)
+ unregister_console(&msm_serial_debug_console);
+#endif
+ free_irq(init_data.signal_irq, 0);
+ msm_fiq_set_handler(NULL, 0);
+ msm_fiq_disable(init_data.irq);
+ msm_fiq_unselect(init_data.irq);
+ clk_disable(debug_clk);
+ printk(KERN_INFO "disable FIQ serial debugger\n");
+ return 0;
+}
+module_param_call(enable, msm_serial_debug_remove, param_get_bool,
+ &debugger_enable, S_IWUSR | S_IRUGO);
diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c
index 624701f..7c1a9e8 100644
--- a/drivers/tty/serial/msm_serial_hs.c
+++ b/drivers/tty/serial/msm_serial_hs.c
@@ -1,10 +1,14 @@
-/*
- * MSM 7k/8k High speed uart driver
+/* drivers/serial/msm_serial_hs.c
*
- * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
+ * MSM 7k High speed uart driver
+ *
* Copyright (c) 2008 Google Inc.
+ * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
* Modified: Nick Pelly <npelly@google.com>
*
+ * All source code in this file is licensed under the following license
+ * except where indicated.
+ *
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
@@ -44,163 +48,25 @@
#include <linux/dma-mapping.h>
#include <linux/dmapool.h>
#include <linux/wait.h>
-#include <linux/workqueue.h>
-
-#include <linux/atomic.h>
+#include <linux/sysfs.h>
+#include <linux/stat.h>
+#include <linux/device.h>
+#include <linux/wakelock.h>
+#include <linux/debugfs.h>
+#include <asm/atomic.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <mach/hardware.h>
#include <mach/dma.h>
-#include <linux/platform_data/msm_serial_hs.h>
+#include <mach/msm_serial_hs.h>
-/* HSUART Registers */
-#define UARTDM_MR1_ADDR 0x0
-#define UARTDM_MR2_ADDR 0x4
+#include "msm_serial_hs_hwreg.h"
-/* Data Mover result codes */
-#define RSLT_FIFO_CNTR_BMSK (0xE << 28)
-#define RSLT_VLD BIT(1)
+static int hs_serial_debug_mask = 1;
+module_param_named(debug_mask, hs_serial_debug_mask,
+ int, S_IRUGO | S_IWUSR | S_IWGRP);
-/* write only register */
-#define UARTDM_CSR_ADDR 0x8
-#define UARTDM_CSR_115200 0xFF
-#define UARTDM_CSR_57600 0xEE
-#define UARTDM_CSR_38400 0xDD
-#define UARTDM_CSR_28800 0xCC
-#define UARTDM_CSR_19200 0xBB
-#define UARTDM_CSR_14400 0xAA
-#define UARTDM_CSR_9600 0x99
-#define UARTDM_CSR_7200 0x88
-#define UARTDM_CSR_4800 0x77
-#define UARTDM_CSR_3600 0x66
-#define UARTDM_CSR_2400 0x55
-#define UARTDM_CSR_1200 0x44
-#define UARTDM_CSR_600 0x33
-#define UARTDM_CSR_300 0x22
-#define UARTDM_CSR_150 0x11
-#define UARTDM_CSR_75 0x00
-
-/* write only register */
-#define UARTDM_TF_ADDR 0x70
-#define UARTDM_TF2_ADDR 0x74
-#define UARTDM_TF3_ADDR 0x78
-#define UARTDM_TF4_ADDR 0x7C
-
-/* write only register */
-#define UARTDM_CR_ADDR 0x10
-#define UARTDM_IMR_ADDR 0x14
-
-#define UARTDM_IPR_ADDR 0x18
-#define UARTDM_TFWR_ADDR 0x1c
-#define UARTDM_RFWR_ADDR 0x20
-#define UARTDM_HCR_ADDR 0x24
-#define UARTDM_DMRX_ADDR 0x34
-#define UARTDM_IRDA_ADDR 0x38
-#define UARTDM_DMEN_ADDR 0x3c
-
-/* UART_DM_NO_CHARS_FOR_TX */
-#define UARTDM_NCF_TX_ADDR 0x40
-
-#define UARTDM_BADR_ADDR 0x44
-
-#define UARTDM_SIM_CFG_ADDR 0x80
-/* Read Only register */
-#define UARTDM_SR_ADDR 0x8
-
-/* Read Only register */
-#define UARTDM_RF_ADDR 0x70
-#define UARTDM_RF2_ADDR 0x74
-#define UARTDM_RF3_ADDR 0x78
-#define UARTDM_RF4_ADDR 0x7C
-
-/* Read Only register */
-#define UARTDM_MISR_ADDR 0x10
-
-/* Read Only register */
-#define UARTDM_ISR_ADDR 0x14
-#define UARTDM_RX_TOTAL_SNAP_ADDR 0x38
-
-#define UARTDM_RXFS_ADDR 0x50
-
-/* Register field Mask Mapping */
-#define UARTDM_SR_PAR_FRAME_BMSK BIT(5)
-#define UARTDM_SR_OVERRUN_BMSK BIT(4)
-#define UARTDM_SR_TXEMT_BMSK BIT(3)
-#define UARTDM_SR_TXRDY_BMSK BIT(2)
-#define UARTDM_SR_RXRDY_BMSK BIT(0)
-
-#define UARTDM_CR_TX_DISABLE_BMSK BIT(3)
-#define UARTDM_CR_RX_DISABLE_BMSK BIT(1)
-#define UARTDM_CR_TX_EN_BMSK BIT(2)
-#define UARTDM_CR_RX_EN_BMSK BIT(0)
-
-/* UARTDM_CR channel_comman bit value (register field is bits 8:4) */
-#define RESET_RX 0x10
-#define RESET_TX 0x20
-#define RESET_ERROR_STATUS 0x30
-#define RESET_BREAK_INT 0x40
-#define START_BREAK 0x50
-#define STOP_BREAK 0x60
-#define RESET_CTS 0x70
-#define RESET_STALE_INT 0x80
-#define RFR_LOW 0xD0
-#define RFR_HIGH 0xE0
-#define CR_PROTECTION_EN 0x100
-#define STALE_EVENT_ENABLE 0x500
-#define STALE_EVENT_DISABLE 0x600
-#define FORCE_STALE_EVENT 0x400
-#define CLEAR_TX_READY 0x300
-#define RESET_TX_ERROR 0x800
-#define RESET_TX_DONE 0x810
-
-#define UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00
-#define UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f
-#define UARTDM_MR1_CTS_CTL_BMSK 0x40
-#define UARTDM_MR1_RX_RDY_CTL_BMSK 0x80
-
-#define UARTDM_MR2_ERROR_MODE_BMSK 0x40
-#define UARTDM_MR2_BITS_PER_CHAR_BMSK 0x30
-
-/* bits per character configuration */
-#define FIVE_BPC (0 << 4)
-#define SIX_BPC (1 << 4)
-#define SEVEN_BPC (2 << 4)
-#define EIGHT_BPC (3 << 4)
-
-#define UARTDM_MR2_STOP_BIT_LEN_BMSK 0xc
-#define STOP_BIT_ONE (1 << 2)
-#define STOP_BIT_TWO (3 << 2)
-
-#define UARTDM_MR2_PARITY_MODE_BMSK 0x3
-
-/* Parity configuration */
-#define NO_PARITY 0x0
-#define EVEN_PARITY 0x1
-#define ODD_PARITY 0x2
-#define SPACE_PARITY 0x3
-
-#define UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80
-#define UARTDM_IPR_STALE_LSB_BMSK 0x1f
-
-/* These can be used for both ISR and IMR register */
-#define UARTDM_ISR_TX_READY_BMSK BIT(7)
-#define UARTDM_ISR_CURRENT_CTS_BMSK BIT(6)
-#define UARTDM_ISR_DELTA_CTS_BMSK BIT(5)
-#define UARTDM_ISR_RXLEV_BMSK BIT(4)
-#define UARTDM_ISR_RXSTALE_BMSK BIT(3)
-#define UARTDM_ISR_RXBREAK_BMSK BIT(2)
-#define UARTDM_ISR_RXHUNT_BMSK BIT(1)
-#define UARTDM_ISR_TXLEV_BMSK BIT(0)
-
-/* Field definitions for UART_DM_DMEN*/
-#define UARTDM_TX_DM_EN_BMSK 0x1
-#define UARTDM_RX_DM_EN_BMSK 0x2
-
-#define UART_FIFOSIZE 64
-#define UARTCLK 7372800
-
-/* Rx DMA request states */
enum flush_reason {
FLUSH_NONE,
FLUSH_DATA_READY,
@@ -210,7 +76,6 @@
FLUSH_SHUTDOWN,
};
-/* UART clock states */
enum msm_hs_clk_states_e {
MSM_HS_CLK_PORT_OFF, /* port not in use */
MSM_HS_CLK_OFF, /* clock disabled */
@@ -227,27 +92,9 @@
CLK_REQ_OFF_RXSTALE_FLUSHED,
};
-/**
- * struct msm_hs_tx
- * @tx_ready_int_en: ok to dma more tx?
- * @dma_in_flight: tx dma in progress
- * @xfer: top level DMA command pointer structure
- * @command_ptr: third level command struct pointer
- * @command_ptr_ptr: second level command list struct pointer
- * @mapped_cmd_ptr: DMA view of third level command struct
- * @mapped_cmd_ptr_ptr: DMA view of second level command list struct
- * @tx_count: number of bytes to transfer in DMA transfer
- * @dma_base: DMA view of UART xmit buffer
- *
- * This structure describes a single Tx DMA transaction. MSM DMA
- * commands have two levels of indirection. The top level command
- * ptr points to a list of command ptr which in turn points to a
- * single DMA 'command'. In our case each Tx transaction consists
- * of a single second level pointer pointing to a 'box type' command.
- */
struct msm_hs_tx {
- unsigned int tx_ready_int_en;
- unsigned int dma_in_flight;
+ unsigned int tx_ready_int_en; /* ok to dma more tx */
+ unsigned int dma_in_flight; /* tx dma in progress */
struct msm_dmov_cmd xfer;
dmov_box *command_ptr;
u32 *command_ptr_ptr;
@@ -255,25 +102,9 @@
dma_addr_t mapped_cmd_ptr_ptr;
int tx_count;
dma_addr_t dma_base;
+ struct tasklet_struct tlet;
};
-/**
- * struct msm_hs_rx
- * @flush: Rx DMA request state
- * @xfer: top level DMA command pointer structure
- * @cmdptr_dmaaddr: DMA view of second level command structure
- * @command_ptr: third level DMA command pointer structure
- * @command_ptr_ptr: second level DMA command list pointer
- * @mapped_cmd_ptr: DMA view of the third level command structure
- * @wait: wait for DMA completion before shutdown
- * @buffer: destination buffer for RX DMA
- * @rbuffer: DMA view of buffer
- * @pool: dma pool out of which coherent rx buffer is allocated
- * @tty_work: private work-queue for tty flip buffer push task
- *
- * This structure describes a single Rx DMA transaction. Rx DMA
- * transactions use box mode DMA commands.
- */
struct msm_hs_rx {
enum flush_reason flush;
struct msm_dmov_cmd xfer;
@@ -284,127 +115,271 @@
wait_queue_head_t wait;
dma_addr_t rbuffer;
unsigned char *buffer;
+ unsigned int buffer_pending;
struct dma_pool *pool;
- struct work_struct tty_work;
+ struct wake_lock wake_lock;
+ struct delayed_work flip_insert_work;
+ struct tasklet_struct tlet;
};
-/**
- * struct msm_hs_rx_wakeup
- * @irq: IRQ line to be configured as interrupt source on Rx activity
- * @ignore: boolean value. 1 = ignore the wakeup interrupt
- * @rx_to_inject: extra character to be inserted to Rx tty on wakeup
- * @inject_rx: 1 = insert rx_to_inject. 0 = do not insert extra character
- *
- * This is an optional structure required for UART Rx GPIO IRQ based
- * wakeup from low power state. UART wakeup can be triggered by RX activity
- * (using a wakeup GPIO on the UART RX pin). This should only be used if
- * there is not a wakeup GPIO on the UART CTS, and the first RX byte is
- * known (eg., with the Bluetooth Texas Instruments HCILL protocol),
- * since the first RX byte will always be lost. RTS will be asserted even
- * while the UART is clocked off in this mode of operation.
- */
-struct msm_hs_rx_wakeup {
+enum buffer_states {
+ NONE_PENDING = 0x0,
+ FIFO_OVERRUN = 0x1,
+ PARITY_ERROR = 0x2,
+ CHARS_NORMAL = 0x4,
+};
+
+/* optional low power wakeup, typically on a GPIO RX irq */
+struct msm_hs_wakeup {
int irq; /* < 0 indicates low power wakeup disabled */
- unsigned char ignore;
+ unsigned char ignore; /* bool */
+
+ /* bool: inject char into rx tty on wakeup */
unsigned char inject_rx;
char rx_to_inject;
};
-/**
- * struct msm_hs_port
- * @uport: embedded uart port structure
- * @imr_reg: shadow value of UARTDM_IMR
- * @clk: uart input clock handle
- * @tx: Tx transaction related data structure
- * @rx: Rx transaction related data structure
- * @dma_tx_channel: Tx DMA command channel
- * @dma_rx_channel Rx DMA command channel
- * @dma_tx_crci: Tx channel rate control interface number
- * @dma_rx_crci: Rx channel rate control interface number
- * @clk_off_timer: Timer to poll DMA event completion before clock off
- * @clk_off_delay: clk_off_timer poll interval
- * @clk_state: overall clock state
- * @clk_req_off_state: post flush clock states
- * @rx_wakeup: optional rx_wakeup feature related data
- * @exit_lpm_cb: optional callback to exit low power mode
- *
- * Low level serial port structure.
- */
struct msm_hs_port {
struct uart_port uport;
- unsigned long imr_reg;
+ unsigned long imr_reg; /* shadow value of UARTDM_IMR */
struct clk *clk;
+ struct clk *pclk;
struct msm_hs_tx tx;
struct msm_hs_rx rx;
-
+ /* gsbi uarts have to do additional writes to gsbi memory */
+ /* block and top control status block. The following pointers */
+ /* keep a handle to these blocks. */
+ unsigned char __iomem *mapped_gsbi;
int dma_tx_channel;
int dma_rx_channel;
int dma_tx_crci;
int dma_rx_crci;
-
- struct hrtimer clk_off_timer;
+ struct hrtimer clk_off_timer; /* to poll TXEMT before clock off */
ktime_t clk_off_delay;
enum msm_hs_clk_states_e clk_state;
enum msm_hs_clk_req_off_state_e clk_req_off_state;
- struct msm_hs_rx_wakeup rx_wakeup;
- void (*exit_lpm_cb)(struct uart_port *);
+ struct msm_hs_wakeup wakeup;
+ struct wake_lock dma_wake_lock; /* held while any DMA active */
};
#define MSM_UARTDM_BURST_SIZE 16 /* DM burst size (in bytes) */
#define UARTDM_TX_BUF_SIZE UART_XMIT_SIZE
#define UARTDM_RX_BUF_SIZE 512
-
+#define RETRY_TIMEOUT 5
#define UARTDM_NR 2
+static struct dentry *debug_base;
static struct msm_hs_port q_uart_port[UARTDM_NR];
static struct platform_driver msm_serial_hs_platform_driver;
static struct uart_driver msm_hs_driver;
static struct uart_ops msm_hs_ops;
-static struct workqueue_struct *msm_hs_workqueue;
#define UARTDM_TO_MSM(uart_port) \
container_of((uart_port), struct msm_hs_port, uport)
-static unsigned int use_low_power_rx_wakeup(struct msm_hs_port
- *msm_uport)
+static ssize_t show_clock(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- return (msm_uport->rx_wakeup.irq >= 0);
+ int state = 1;
+ enum msm_hs_clk_states_e clk_state;
+ unsigned long flags;
+
+ struct platform_device *pdev = container_of(dev, struct
+ platform_device, dev);
+ struct msm_hs_port *msm_uport = &q_uart_port[pdev->id];
+
+ spin_lock_irqsave(&msm_uport->uport.lock, flags);
+ clk_state = msm_uport->clk_state;
+ spin_unlock_irqrestore(&msm_uport->uport.lock, flags);
+
+ if (clk_state <= MSM_HS_CLK_OFF)
+ state = 0;
+
+ return sprintf(buf, "%d\n", state);
}
-static unsigned int msm_hs_read(struct uart_port *uport,
+static ssize_t set_clock(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ int state;
+ struct platform_device *pdev = container_of(dev, struct
+ platform_device, dev);
+ struct msm_hs_port *msm_uport = &q_uart_port[pdev->id];
+
+ state = buf[0] - '0';
+ switch (state) {
+ case 0: {
+ msm_hs_request_clock_off(&msm_uport->uport);
+ break;
+ }
+ case 1: {
+ msm_hs_request_clock_on(&msm_uport->uport);
+ break;
+ }
+ default: {
+ return -EINVAL;
+ }
+ }
+ return count;
+}
+
+static DEVICE_ATTR(clock, S_IWUSR | S_IRUGO, show_clock, set_clock);
+
+static inline unsigned int use_low_power_wakeup(struct msm_hs_port *msm_uport)
+{
+ return (msm_uport->wakeup.irq > 0);
+}
+
+static inline int is_gsbi_uart(struct msm_hs_port *msm_uport)
+{
+ /* assume gsbi uart if gsbi resource found in pdata */
+ return ((msm_uport->mapped_gsbi != NULL));
+}
+
+static inline unsigned int msm_hs_read(struct uart_port *uport,
unsigned int offset)
{
- return ioread32(uport->membase + offset);
+ return readl_relaxed(uport->membase + offset);
}
-static void msm_hs_write(struct uart_port *uport, unsigned int offset,
+static inline void msm_hs_write(struct uart_port *uport, unsigned int offset,
unsigned int value)
{
- iowrite32(value, uport->membase + offset);
+ writel_relaxed(value, uport->membase + offset);
}
static void msm_hs_release_port(struct uart_port *port)
{
- iounmap(port->membase);
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(port);
+ struct platform_device *pdev = to_platform_device(port->dev);
+ struct resource *gsbi_resource;
+ resource_size_t size;
+
+ if (is_gsbi_uart(msm_uport)) {
+ iowrite32(GSBI_PROTOCOL_IDLE, msm_uport->mapped_gsbi +
+ GSBI_CONTROL_ADDR);
+ gsbi_resource = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM,
+ "gsbi_resource");
+ size = gsbi_resource->end - gsbi_resource->start + 1;
+ release_mem_region(gsbi_resource->start, size);
+ iounmap(msm_uport->mapped_gsbi);
+ msm_uport->mapped_gsbi = NULL;
+ }
}
static int msm_hs_request_port(struct uart_port *port)
{
- port->membase = ioremap(port->mapbase, PAGE_SIZE);
- if (unlikely(!port->membase))
- return -ENOMEM;
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(port);
+ struct platform_device *pdev = to_platform_device(port->dev);
+ struct resource *gsbi_resource;
+ resource_size_t size;
- /* configure the CR Protection to Enable */
- msm_hs_write(port, UARTDM_CR_ADDR, CR_PROTECTION_EN);
+ gsbi_resource = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM,
+ "gsbi_resource");
+ if (gsbi_resource) {
+ size = gsbi_resource->end - gsbi_resource->start + 1;
+ if (unlikely(!request_mem_region(gsbi_resource->start, size,
+ "msm_serial_hs")))
+ return -EBUSY;
+ msm_uport->mapped_gsbi = ioremap(gsbi_resource->start,
+ size);
+ if (!msm_uport->mapped_gsbi) {
+ release_mem_region(gsbi_resource->start, size);
+ return -EBUSY;
+ }
+ }
+ /* no gsbi uart */
return 0;
}
+static int msm_serial_loopback_enable_set(void *data, u64 val)
+{
+ struct msm_hs_port *msm_uport = data;
+ struct uart_port *uport = &(msm_uport->uport);
+ unsigned long flags;
+ int ret = 0;
+
+ clk_enable(msm_uport->clk);
+ if (msm_uport->pclk)
+ clk_enable(msm_uport->pclk);
+
+ if (val) {
+ spin_lock_irqsave(&uport->lock, flags);
+ ret = msm_hs_read(uport, UARTDM_MR2_ADDR);
+ ret |= UARTDM_MR2_LOOP_MODE_BMSK;
+ msm_hs_write(uport, UARTDM_MR2_ADDR, ret);
+ spin_unlock_irqrestore(&uport->lock, flags);
+ } else {
+ spin_lock_irqsave(&uport->lock, flags);
+ ret = msm_hs_read(uport, UARTDM_MR2_ADDR);
+ ret &= ~UARTDM_MR2_LOOP_MODE_BMSK;
+ msm_hs_write(uport, UARTDM_MR2_ADDR, ret);
+ spin_unlock_irqrestore(&uport->lock, flags);
+ }
+ /* Calling CLOCK API. Hence mb() requires here. */
+ mb();
+ clk_disable(msm_uport->clk);
+ if (msm_uport->pclk)
+ clk_disable(msm_uport->pclk);
+
+ return 0;
+}
+
+static int msm_serial_loopback_enable_get(void *data, u64 *val)
+{
+ struct msm_hs_port *msm_uport = data;
+ struct uart_port *uport = &(msm_uport->uport);
+ unsigned long flags;
+ int ret = 0;
+
+ clk_enable(msm_uport->clk);
+ if (msm_uport->pclk)
+ clk_enable(msm_uport->pclk);
+
+ spin_lock_irqsave(&uport->lock, flags);
+ ret = msm_hs_read(&msm_uport->uport, UARTDM_MR2_ADDR);
+ spin_unlock_irqrestore(&uport->lock, flags);
+
+ clk_disable(msm_uport->clk);
+ if (msm_uport->pclk)
+ clk_disable(msm_uport->pclk);
+
+ *val = (ret & UARTDM_MR2_LOOP_MODE_BMSK) ? 1 : 0;
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(loopback_enable_fops, msm_serial_loopback_enable_get,
+ msm_serial_loopback_enable_set, "%llu\n");
+
+/*
+ * msm_serial_hs debugfs node: <debugfs_root>/msm_serial_hs/loopback.<id>
+ * writing 1 turns on internal loopback mode in HW. Useful for automation
+ * test scripts.
+ * writing 0 disables the internal loopback mode. Default is disabled.
+ */
+static void __init msm_serial_debugfs_init(struct msm_hs_port *msm_uport,
+ int id)
+{
+ char node_name[15];
+ snprintf(node_name, sizeof(node_name), "loopback.%d", id);
+ if (IS_ERR_OR_NULL(debugfs_create_file(node_name,
+ S_IRUGO | S_IWUSR,
+ debug_base,
+ msm_uport,
+ &loopback_enable_fops))) {
+ debugfs_remove_recursive(debug_base);
+ }
+}
+
static int __devexit msm_hs_remove(struct platform_device *pdev)
{
struct msm_hs_port *msm_uport;
struct device *dev;
+ struct msm_serial_hs_platform_data *pdata = pdev->dev.platform_data;
+
if (pdev->id < 0 || pdev->id >= UARTDM_NR) {
printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id);
@@ -414,6 +389,13 @@
msm_uport = &q_uart_port[pdev->id];
dev = msm_uport->uport.dev;
+ if (pdata && pdata->gpio_config)
+ if (pdata->gpio_config(0))
+ dev_err(dev, "GPIO config error\n");
+
+ sysfs_remove_file(&pdev->dev.kobj, &dev_attr_clock.attr);
+ debugfs_remove_recursive(debug_base);
+
dma_unmap_single(dev, msm_uport->rx.mapped_cmd_ptr, sizeof(dmov_box),
DMA_TO_DEVICE);
dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer,
@@ -427,6 +409,9 @@
dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr, sizeof(dmov_box),
DMA_TO_DEVICE);
+ wake_lock_destroy(&msm_uport->rx.wake_lock);
+ wake_lock_destroy(&msm_uport->dma_wake_lock);
+
uart_remove_one_port(&msm_hs_driver, &msm_uport->uport);
clk_put(msm_uport->clk);
@@ -443,64 +428,48 @@
return 0;
}
-static int msm_hs_init_clk_locked(struct uart_port *uport)
+static int msm_hs_init_clk(struct uart_port *uport)
{
int ret;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+ wake_lock(&msm_uport->dma_wake_lock);
+ /* Set up the MREG/NREG/DREG/MNDREG */
+ ret = clk_set_rate(msm_uport->clk, uport->uartclk);
+ if (ret) {
+ printk(KERN_WARNING "Error setting clock rate on UART\n");
+ return ret;
+ }
+
ret = clk_enable(msm_uport->clk);
if (ret) {
printk(KERN_ERR "Error could not turn on UART clk\n");
return ret;
}
-
- /* Set up the MREG/NREG/DREG/MNDREG */
- ret = clk_set_rate(msm_uport->clk, uport->uartclk);
- if (ret) {
- printk(KERN_WARNING "Error setting clock rate on UART\n");
- clk_disable(msm_uport->clk);
- return ret;
+ if (msm_uport->pclk) {
+ ret = clk_enable(msm_uport->pclk);
+ if (ret) {
+ dev_err(uport->dev,
+ "Error could not turn on UART pclk\n");
+ return ret;
+ }
}
msm_uport->clk_state = MSM_HS_CLK_ON;
return 0;
}
-/* Enable and Disable clocks (Used for power management) */
-static void msm_hs_pm(struct uart_port *uport, unsigned int state,
- unsigned int oldstate)
-{
- struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
-
- if (use_low_power_rx_wakeup(msm_uport) ||
- msm_uport->exit_lpm_cb)
- return; /* ignore linux PM states,
- use msm_hs_request_clock API */
-
- switch (state) {
- case 0:
- clk_enable(msm_uport->clk);
- break;
- case 3:
- clk_disable(msm_uport->clk);
- break;
- default:
- dev_err(uport->dev, "msm_serial: Unknown PM state %d\n",
- state);
- }
-}
-
/*
* programs the UARTDM_CSR register with correct bit rates
*
* Interrupts should be disabled before we are called, as
* we modify Set Baud rate
- * Set receive stale interrupt level, dependent on Bit Rate
+ * Set receive stale interrupt level, dependant on Bit Rate
* Goal is to have around 8 ms before indicate stale.
* roundup (((Bit Rate * .008) / 10) + 1
*/
static void msm_hs_set_bps_locked(struct uart_port *uport,
- unsigned int bps)
+ unsigned int bps)
{
unsigned long rxstale;
unsigned long data;
@@ -508,63 +477,63 @@
switch (bps) {
case 300:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_75);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0x00);
rxstale = 1;
break;
case 600:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_150);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0x11);
rxstale = 1;
break;
case 1200:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_300);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0x22);
rxstale = 1;
break;
case 2400:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_600);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0x33);
rxstale = 1;
break;
case 4800:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_1200);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0x44);
rxstale = 1;
break;
case 9600:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_2400);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0x55);
rxstale = 2;
break;
case 14400:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_3600);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0x66);
rxstale = 3;
break;
case 19200:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_4800);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0x77);
rxstale = 4;
break;
case 28800:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_7200);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0x88);
rxstale = 6;
break;
case 38400:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_9600);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0x99);
rxstale = 8;
break;
case 57600:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_14400);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0xaa);
rxstale = 16;
break;
case 76800:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_19200);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0xbb);
rxstale = 16;
break;
case 115200:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_28800);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0xcc);
rxstale = 31;
break;
case 230400:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_57600);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0xee);
rxstale = 31;
break;
case 460800:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_115200);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0xff);
rxstale = 31;
break;
case 4000000:
@@ -577,21 +546,28 @@
case 1152000:
case 1000000:
case 921600:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_115200);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0xff);
rxstale = 31;
break;
default:
- msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_2400);
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0xff);
/* default to 9600 */
bps = 9600;
rxstale = 2;
break;
}
- if (bps > 460800)
+ /*
+ * uart baud rate depends on CSR and MND Values
+ * we are updating CSR before and then calling
+ * clk_set_rate which updates MND Values. Hence
+ * dsb requires here.
+ */
+ mb();
+ if (bps > 460800) {
uport->uartclk = bps * 16;
- else
- uport->uartclk = UARTCLK;
-
+ } else {
+ uport->uartclk = 7372800;
+ }
if (clk_set_rate(msm_uport->clk, uport->uartclk)) {
printk(KERN_WARNING "Error setting clock rate on UART\n");
return;
@@ -603,6 +579,56 @@
msm_hs_write(uport, UARTDM_IPR_ADDR, data);
}
+
+static void msm_hs_set_std_bps_locked(struct uart_port *uport,
+ unsigned int bps)
+{
+ unsigned long rxstale;
+ unsigned long data;
+
+ switch (bps) {
+ case 9600:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0x99);
+ rxstale = 2;
+ break;
+ case 14400:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0xaa);
+ rxstale = 3;
+ break;
+ case 19200:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0xbb);
+ rxstale = 4;
+ break;
+ case 28800:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0xcc);
+ rxstale = 6;
+ break;
+ case 38400:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0xdd);
+ rxstale = 8;
+ break;
+ case 57600:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0xee);
+ rxstale = 16;
+ break;
+ case 115200:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0xff);
+ rxstale = 31;
+ break;
+ default:
+ msm_hs_write(uport, UARTDM_CSR_ADDR, 0x99);
+ /* default to 9600 */
+ bps = 9600;
+ rxstale = 2;
+ break;
+ }
+
+ data = rxstale & UARTDM_IPR_STALE_LSB_BMSK;
+ data |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2);
+
+ msm_hs_write(uport, UARTDM_IPR_ADDR, data);
+}
+
/*
* termios : new ktermios
* oldtermios: old ktermios previous setting
@@ -610,8 +636,8 @@
* Configure the serial port
*/
static void msm_hs_set_termios(struct uart_port *uport,
- struct ktermios *termios,
- struct ktermios *oldtermios)
+ struct ktermios *termios,
+ struct ktermios *oldtermios)
{
unsigned int bps;
unsigned long data;
@@ -629,18 +655,23 @@
if (bps == 200)
bps = 3200000;
- msm_hs_set_bps_locked(uport, bps);
+ uport->uartclk = clk_get_rate(msm_uport->clk);
+ if (!uport->uartclk)
+ msm_hs_set_std_bps_locked(uport, bps);
+ else
+ msm_hs_set_bps_locked(uport, bps);
data = msm_hs_read(uport, UARTDM_MR2_ADDR);
data &= ~UARTDM_MR2_PARITY_MODE_BMSK;
/* set parity */
if (PARENB == (c_cflag & PARENB)) {
- if (PARODD == (c_cflag & PARODD))
+ if (PARODD == (c_cflag & PARODD)) {
data |= ODD_PARITY;
- else if (CMSPAR == (c_cflag & CMSPAR))
+ } else if (CMSPAR == (c_cflag & CMSPAR)) {
data |= SPACE_PARITY;
- else
+ } else {
data |= EVEN_PARITY;
+ }
}
/* Set bits per char */
@@ -696,12 +727,22 @@
msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX);
if (msm_uport->rx.flush == FLUSH_NONE) {
+ wake_lock(&msm_uport->rx.wake_lock);
msm_uport->rx.flush = FLUSH_IGNORE;
- msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1);
+ /*
+ * Before using dmov APIs make sure that
+ * previous writel are completed. Hence
+ * dsb requires here.
+ */
+ mb();
+ /* do discard flush */
+ msm_dmov_stop_cmd(msm_uport->dma_rx_channel,
+ &msm_uport->rx.xfer, 0);
}
msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
-
+ /* calling other hardware component here clk_disable API. */
+ mb();
clk_disable(msm_uport->clk);
spin_unlock_irqrestore(&uport->lock, flags);
}
@@ -710,7 +751,7 @@
* Standard API, Transmitter
* Any character in the transmit shift register is sent
*/
-static unsigned int msm_hs_tx_empty(struct uart_port *uport)
+unsigned int msm_hs_tx_empty(struct uart_port *uport)
{
unsigned int data;
unsigned int ret = 0;
@@ -726,6 +767,7 @@
return ret;
}
+EXPORT_SYMBOL(msm_hs_tx_empty);
/*
* Standard API, Stop transmitter.
@@ -759,10 +801,15 @@
data &= ~UARTDM_RX_DM_EN_BMSK;
msm_hs_write(uport, UARTDM_DMEN_ADDR, data);
+ /* calling DMOV or CLOCK API. Hence mb() */
+ mb();
/* Disable the receiver */
- if (msm_uport->rx.flush == FLUSH_NONE)
- msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1);
-
+ if (msm_uport->rx.flush == FLUSH_NONE) {
+ wake_lock(&msm_uport->rx.wake_lock);
+ /* do discard flush */
+ msm_dmov_stop_cmd(msm_uport->dma_rx_channel,
+ &msm_uport->rx.xfer, 0);
+ }
if (msm_uport->rx.flush != FLUSH_SHUTDOWN)
msm_uport->rx.flush = FLUSH_STOP;
@@ -774,7 +821,9 @@
{
int left;
int tx_count;
+ int aligned_tx_count;
dma_addr_t src_addr;
+ dma_addr_t aligned_src_addr;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
struct msm_hs_tx *tx = &msm_uport->tx;
struct circ_buf *tx_buf = &msm_uport->uport.state->xmit;
@@ -797,8 +846,13 @@
tx_count = left;
src_addr = tx->dma_base + tx_buf->tail;
- dma_sync_single_for_device(uport->dev, src_addr, tx_count,
- DMA_TO_DEVICE);
+ /* Mask the src_addr to align on a cache
+ * and add those bytes to tx_count */
+ aligned_src_addr = src_addr & ~(dma_get_cache_alignment() - 1);
+ aligned_tx_count = tx_count + src_addr - aligned_src_addr;
+
+ dma_sync_single_for_device(uport->dev, aligned_src_addr,
+ aligned_tx_count, DMA_TO_DEVICE);
tx->command_ptr->num_rows = (((tx_count + 15) >> 4) << 16) |
((tx_count + 15) >> 4);
@@ -809,9 +863,6 @@
*tx->command_ptr_ptr = CMD_PTR_LP | DMOV_CMD_ADDR(tx->mapped_cmd_ptr);
- dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr_ptr,
- sizeof(u32 *), DMA_TO_DEVICE);
-
/* Save tx_count to use in Callback */
tx->tx_count = tx_count;
msm_hs_write(uport, UARTDM_NCF_TX_ADDR, tx_count);
@@ -819,6 +870,12 @@
/* Disable the tx_ready interrupt */
msm_uport->imr_reg &= ~UARTDM_ISR_TX_READY_BMSK;
msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+ /* Calling next DMOV API. Hence mb() here. */
+ mb();
+
+ dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr_ptr,
+ sizeof(u32 *), DMA_TO_DEVICE);
+
msm_dmov_enqueue_cmd(msm_uport->dma_tx_channel, &tx->xfer);
}
@@ -826,34 +883,197 @@
static void msm_hs_start_rx_locked(struct uart_port *uport)
{
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+ unsigned int buffer_pending = msm_uport->rx.buffer_pending;
+
+ msm_uport->rx.buffer_pending = 0;
+ if (buffer_pending && hs_serial_debug_mask)
+ printk(KERN_ERR "Error: rx started in buffer state = %x",
+ buffer_pending);
msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT);
msm_hs_write(uport, UARTDM_DMRX_ADDR, UARTDM_RX_BUF_SIZE);
msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_ENABLE);
msm_uport->imr_reg |= UARTDM_ISR_RXLEV_BMSK;
msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+ /* Calling next DMOV API. Hence mb() here. */
+ mb();
msm_uport->rx.flush = FLUSH_NONE;
msm_dmov_enqueue_cmd(msm_uport->dma_rx_channel, &msm_uport->rx.xfer);
- /* might have finished RX and be ready to clock off */
- hrtimer_start(&msm_uport->clk_off_timer, msm_uport->clk_off_delay,
- HRTIMER_MODE_REL);
+}
+
+static void flip_insert_work(struct work_struct *work)
+{
+ unsigned long flags;
+ int retval;
+ struct msm_hs_port *msm_uport =
+ container_of(work, struct msm_hs_port,
+ rx.flip_insert_work.work);
+ struct tty_struct *tty = msm_uport->uport.state->port.tty;
+
+ spin_lock_irqsave(&msm_uport->uport.lock, flags);
+ if (msm_uport->rx.buffer_pending == NONE_PENDING) {
+ if (hs_serial_debug_mask)
+ printk(KERN_ERR "Error: No buffer pending in %s",
+ __func__);
+ return;
+ }
+ if (msm_uport->rx.buffer_pending & FIFO_OVERRUN) {
+ retval = tty_insert_flip_char(tty, 0, TTY_OVERRUN);
+ if (retval)
+ msm_uport->rx.buffer_pending &= ~FIFO_OVERRUN;
+ }
+ if (msm_uport->rx.buffer_pending & PARITY_ERROR) {
+ retval = tty_insert_flip_char(tty, 0, TTY_PARITY);
+ if (retval)
+ msm_uport->rx.buffer_pending &= ~PARITY_ERROR;
+ }
+ if (msm_uport->rx.buffer_pending & CHARS_NORMAL) {
+ int rx_count, rx_offset;
+ rx_count = (msm_uport->rx.buffer_pending & 0xFFFF0000) >> 16;
+ rx_offset = (msm_uport->rx.buffer_pending & 0xFFD0) >> 5;
+ retval = tty_insert_flip_string(tty, msm_uport->rx.buffer +
+ rx_offset, rx_count);
+ msm_uport->rx.buffer_pending &= (FIFO_OVERRUN |
+ PARITY_ERROR);
+ if (retval != rx_count)
+ msm_uport->rx.buffer_pending |= CHARS_NORMAL |
+ retval << 8 | (rx_count - retval) << 16;
+ }
+ if (msm_uport->rx.buffer_pending)
+ schedule_delayed_work(&msm_uport->rx.flip_insert_work,
+ msecs_to_jiffies(RETRY_TIMEOUT));
+ else
+ if ((msm_uport->clk_state == MSM_HS_CLK_ON) &&
+ (msm_uport->rx.flush <= FLUSH_IGNORE)) {
+ if (hs_serial_debug_mask)
+ printk(KERN_WARNING
+ "msm_serial_hs: "
+ "Pending buffers cleared. "
+ "Restarting\n");
+ msm_hs_start_rx_locked(&msm_uport->uport);
+ }
+ spin_unlock_irqrestore(&msm_uport->uport.lock, flags);
+ tty_flip_buffer_push(tty);
+}
+
+static void msm_serial_hs_rx_tlet(unsigned long tlet_ptr)
+{
+ int retval;
+ int rx_count;
+ unsigned long status;
+ unsigned long flags;
+ unsigned int error_f = 0;
+ struct uart_port *uport;
+ struct msm_hs_port *msm_uport;
+ unsigned int flush;
+ struct tty_struct *tty;
+
+ msm_uport = container_of((struct tasklet_struct *)tlet_ptr,
+ struct msm_hs_port, rx.tlet);
+ uport = &msm_uport->uport;
+ tty = uport->state->port.tty;
+
+ status = msm_hs_read(uport, UARTDM_SR_ADDR);
+
+ spin_lock_irqsave(&uport->lock, flags);
+
+ clk_enable(msm_uport->clk);
+ msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_DISABLE);
+
+ /* overflow is not connect to data in a FIFO */
+ if (unlikely((status & UARTDM_SR_OVERRUN_BMSK) &&
+ (uport->read_status_mask & CREAD))) {
+ retval = tty_insert_flip_char(tty, 0, TTY_OVERRUN);
+ if (!retval)
+ msm_uport->rx.buffer_pending |= TTY_OVERRUN;
+ uport->icount.buf_overrun++;
+ error_f = 1;
+ }
+
+ if (!(uport->ignore_status_mask & INPCK))
+ status = status & ~(UARTDM_SR_PAR_FRAME_BMSK);
+
+ if (unlikely(status & UARTDM_SR_PAR_FRAME_BMSK)) {
+ /* Can not tell difference between parity & frame error */
+ uport->icount.parity++;
+ error_f = 1;
+ if (uport->ignore_status_mask & IGNPAR) {
+ retval = tty_insert_flip_char(tty, 0, TTY_PARITY);
+ if (!retval)
+ msm_uport->rx.buffer_pending |= TTY_PARITY;
+ }
+ }
+
+ if (error_f)
+ msm_hs_write(uport, UARTDM_CR_ADDR, RESET_ERROR_STATUS);
+
+ if (msm_uport->clk_req_off_state == CLK_REQ_OFF_FLUSH_ISSUED)
+ msm_uport->clk_req_off_state = CLK_REQ_OFF_RXSTALE_FLUSHED;
+ flush = msm_uport->rx.flush;
+ if (flush == FLUSH_IGNORE)
+ if (!msm_uport->rx.buffer_pending)
+ msm_hs_start_rx_locked(uport);
+
+ if (flush == FLUSH_STOP) {
+ msm_uport->rx.flush = FLUSH_SHUTDOWN;
+ wake_up(&msm_uport->rx.wait);
+ }
+ if (flush >= FLUSH_DATA_INVALID)
+ goto out;
+
+ rx_count = msm_hs_read(uport, UARTDM_RX_TOTAL_SNAP_ADDR);
+
+ /* order the read of rx.buffer */
+ rmb();
+
+ if (0 != (uport->read_status_mask & CREAD)) {
+ retval = tty_insert_flip_string(tty, msm_uport->rx.buffer,
+ rx_count);
+ if (retval != rx_count) {
+ msm_uport->rx.buffer_pending |= CHARS_NORMAL |
+ retval << 5 | (rx_count - retval) << 16;
+ }
+ }
+
+ /* order the read of rx.buffer and the start of next rx xfer */
+ wmb();
+
+ if (!msm_uport->rx.buffer_pending)
+ msm_hs_start_rx_locked(uport);
+
+out:
+ if (msm_uport->rx.buffer_pending) {
+ if (hs_serial_debug_mask)
+ printk(KERN_WARNING
+ "msm_serial_hs: "
+ "tty buffer exhausted. "
+ "Stalling\n");
+ schedule_delayed_work(&msm_uport->rx.flip_insert_work
+ , msecs_to_jiffies(RETRY_TIMEOUT));
+ }
+ clk_disable(msm_uport->clk);
+ /* release wakelock in 500ms, not immediately, because higher layers
+ * don't always take wakelocks when they should */
+ wake_lock_timeout(&msm_uport->rx.wake_lock, HZ / 2);
+ /* tty_flip_buffer_push() might call msm_hs_start(), so unlock */
+ spin_unlock_irqrestore(&uport->lock, flags);
+ if (flush < FLUSH_DATA_INVALID)
+ tty_flip_buffer_push(tty);
}
/* Enable the transmitter Interrupt */
-static void msm_hs_start_tx_locked(struct uart_port *uport)
+static void msm_hs_start_tx_locked(struct uart_port *uport )
{
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
clk_enable(msm_uport->clk);
- if (msm_uport->exit_lpm_cb)
- msm_uport->exit_lpm_cb(uport);
-
if (msm_uport->tx.tx_ready_int_en == 0) {
msm_uport->tx.tx_ready_int_en = 1;
- msm_hs_submit_tx_locked(uport);
+ if (msm_uport->tx.dma_in_flight == 0)
+ msm_hs_submit_tx_locked(uport);
}
clk_disable(msm_uport->clk);
@@ -870,23 +1090,31 @@
unsigned int result,
struct msm_dmov_errdata *err)
{
- unsigned long flags;
struct msm_hs_port *msm_uport;
- /* DMA did not finish properly */
- WARN_ON((((result & RSLT_FIFO_CNTR_BMSK) >> 28) == 1) &&
- !(result & RSLT_VLD));
+ WARN_ON(result != 0x80000002); /* DMA did not finish properly */
msm_uport = container_of(cmd_ptr, struct msm_hs_port, tx.xfer);
- spin_lock_irqsave(&msm_uport->uport.lock, flags);
+ tasklet_schedule(&msm_uport->tx.tlet);
+}
+
+static void msm_serial_hs_tx_tlet(unsigned long tlet_ptr)
+{
+ unsigned long flags;
+ struct msm_hs_port *msm_uport = container_of((struct tasklet_struct *)
+ tlet_ptr, struct msm_hs_port, tx.tlet);
+
+ spin_lock_irqsave(&(msm_uport->uport.lock), flags);
clk_enable(msm_uport->clk);
msm_uport->imr_reg |= UARTDM_ISR_TX_READY_BMSK;
- msm_hs_write(&msm_uport->uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+ msm_hs_write(&(msm_uport->uport), UARTDM_IMR_ADDR, msm_uport->imr_reg);
+ /* Calling clk API. Hence mb() requires. */
+ mb();
clk_disable(msm_uport->clk);
- spin_unlock_irqrestore(&msm_uport->uport.lock, flags);
+ spin_unlock_irqrestore(&(msm_uport->uport.lock), flags);
}
/*
@@ -900,87 +1128,11 @@
unsigned int result,
struct msm_dmov_errdata *err)
{
- int retval;
- int rx_count;
- unsigned long status;
- unsigned int error_f = 0;
- unsigned long flags;
- unsigned int flush;
- struct tty_struct *tty;
- struct uart_port *uport;
struct msm_hs_port *msm_uport;
msm_uport = container_of(cmd_ptr, struct msm_hs_port, rx.xfer);
- uport = &msm_uport->uport;
- spin_lock_irqsave(&uport->lock, flags);
- clk_enable(msm_uport->clk);
-
- tty = uport->state->port.tty;
-
- msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_DISABLE);
-
- status = msm_hs_read(uport, UARTDM_SR_ADDR);
-
- /* overflow is not connect to data in a FIFO */
- if (unlikely((status & UARTDM_SR_OVERRUN_BMSK) &&
- (uport->read_status_mask & CREAD))) {
- tty_insert_flip_char(tty, 0, TTY_OVERRUN);
- uport->icount.buf_overrun++;
- error_f = 1;
- }
-
- if (!(uport->ignore_status_mask & INPCK))
- status = status & ~(UARTDM_SR_PAR_FRAME_BMSK);
-
- if (unlikely(status & UARTDM_SR_PAR_FRAME_BMSK)) {
- /* Can not tell difference between parity & frame error */
- uport->icount.parity++;
- error_f = 1;
- if (uport->ignore_status_mask & IGNPAR)
- tty_insert_flip_char(tty, 0, TTY_PARITY);
- }
-
- if (error_f)
- msm_hs_write(uport, UARTDM_CR_ADDR, RESET_ERROR_STATUS);
-
- if (msm_uport->clk_req_off_state == CLK_REQ_OFF_FLUSH_ISSUED)
- msm_uport->clk_req_off_state = CLK_REQ_OFF_RXSTALE_FLUSHED;
-
- flush = msm_uport->rx.flush;
- if (flush == FLUSH_IGNORE)
- msm_hs_start_rx_locked(uport);
- if (flush == FLUSH_STOP)
- msm_uport->rx.flush = FLUSH_SHUTDOWN;
- if (flush >= FLUSH_DATA_INVALID)
- goto out;
-
- rx_count = msm_hs_read(uport, UARTDM_RX_TOTAL_SNAP_ADDR);
-
- if (0 != (uport->read_status_mask & CREAD)) {
- retval = tty_insert_flip_string(tty, msm_uport->rx.buffer,
- rx_count);
- BUG_ON(retval != rx_count);
- }
-
- msm_hs_start_rx_locked(uport);
-
-out:
- clk_disable(msm_uport->clk);
-
- spin_unlock_irqrestore(&uport->lock, flags);
-
- if (flush < FLUSH_DATA_INVALID)
- queue_work(msm_hs_workqueue, &msm_uport->rx.tty_work);
-}
-
-static void msm_hs_tty_flip_buffer_work(struct work_struct *work)
-{
- struct msm_hs_port *msm_uport =
- container_of(work, struct msm_hs_port, rx.tty_work);
- struct tty_struct *tty = msm_uport->uport.state->port.tty;
-
- tty_flip_buffer_push(tty);
+ tasklet_schedule(&msm_uport->rx.tlet);
}
/*
@@ -1002,46 +1154,53 @@
}
/*
- * True enables UART auto RFR, which indicates we are ready for data if the RX
- * buffer is not full. False disables auto RFR, and deasserts RFR to indicate
- * we are not ready for data. Must be called with UART clock on.
+ * Standard API, Set or clear RFR_signal
+ *
+ * Set RFR high, (Indicate we are not ready for data), we disable auto
+ * ready for receiving and then set RFR_N high. To set RFR to low we just turn
+ * back auto ready for receiving and it should lower RFR signal
+ * when hardware is ready
*/
-static void set_rfr_locked(struct uart_port *uport, int auto_rfr)
-{
- unsigned int data;
-
- data = msm_hs_read(uport, UARTDM_MR1_ADDR);
-
- if (auto_rfr) {
- /* enable auto ready-for-receiving */
- data |= UARTDM_MR1_RX_RDY_CTL_BMSK;
- msm_hs_write(uport, UARTDM_MR1_ADDR, data);
- } else {
- /* disable auto ready-for-receiving */
- data &= ~UARTDM_MR1_RX_RDY_CTL_BMSK;
- msm_hs_write(uport, UARTDM_MR1_ADDR, data);
- /* RFR is active low, set high */
- msm_hs_write(uport, UARTDM_CR_ADDR, RFR_HIGH);
- }
-}
-
-/*
- * Standard API, used to set or clear RFR
- */
-static void msm_hs_set_mctrl_locked(struct uart_port *uport,
+void msm_hs_set_mctrl_locked(struct uart_port *uport,
unsigned int mctrl)
{
- unsigned int auto_rfr;
+ unsigned int set_rts;
+ unsigned int data;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
clk_enable(msm_uport->clk);
- auto_rfr = TIOCM_RTS & mctrl ? 1 : 0;
- set_rfr_locked(uport, auto_rfr);
+ /* RTS is active low */
+ set_rts = TIOCM_RTS & mctrl ? 0 : 1;
+ data = msm_hs_read(uport, UARTDM_MR1_ADDR);
+ if (set_rts) {
+ /*disable auto ready-for-receiving */
+ data &= ~UARTDM_MR1_RX_RDY_CTL_BMSK;
+ msm_hs_write(uport, UARTDM_MR1_ADDR, data);
+ /* set RFR_N to high */
+ msm_hs_write(uport, UARTDM_CR_ADDR, RFR_HIGH);
+ } else {
+ /* Enable auto ready-for-receiving */
+ data |= UARTDM_MR1_RX_RDY_CTL_BMSK;
+ msm_hs_write(uport, UARTDM_MR1_ADDR, data);
+ }
+ /* Calling CLOCK API. Hence mb() requires. */
+ mb();
clk_disable(msm_uport->clk);
}
+void msm_hs_set_mctrl(struct uart_port *uport,
+ unsigned int mctrl)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&uport->lock, flags);
+ msm_hs_set_mctrl_locked(uport, mctrl);
+ spin_unlock_irqrestore(&uport->lock, flags);
+}
+EXPORT_SYMBOL(msm_hs_set_mctrl);
+
/* Standard API, Enable modem status (CTS) interrupt */
static void msm_hs_enable_ms_locked(struct uart_port *uport)
{
@@ -1052,6 +1211,8 @@
/* Enable DELTA_CTS Interrupt */
msm_uport->imr_reg |= UARTDM_ISR_DELTA_CTS_BMSK;
msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+ /* Calling CLOCK API. Hence mb() requires here. */
+ mb();
clk_disable(msm_uport->clk);
@@ -1065,40 +1226,49 @@
*/
static void msm_hs_break_ctl(struct uart_port *uport, int ctl)
{
+ unsigned long flags;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+ spin_lock_irqsave(&uport->lock, flags);
clk_enable(msm_uport->clk);
msm_hs_write(uport, UARTDM_CR_ADDR, ctl ? START_BREAK : STOP_BREAK);
+ /* Calling CLOCK API. Hence mb() requires here. */
+ mb();
clk_disable(msm_uport->clk);
+ spin_unlock_irqrestore(&uport->lock, flags);
}
static void msm_hs_config_port(struct uart_port *uport, int cfg_flags)
{
unsigned long flags;
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
spin_lock_irqsave(&uport->lock, flags);
if (cfg_flags & UART_CONFIG_TYPE) {
uport->type = PORT_MSM;
msm_hs_request_port(uport);
}
+ if (is_gsbi_uart(msm_uport)) {
+ iowrite32(GSBI_PROTOCOL_UART, msm_uport->mapped_gsbi +
+ GSBI_CONTROL_ADDR);
+ }
spin_unlock_irqrestore(&uport->lock, flags);
}
/* Handle CTS changes (Called from interrupt handler) */
-static void msm_hs_handle_delta_cts(struct uart_port *uport)
+static void msm_hs_handle_delta_cts_locked(struct uart_port *uport)
{
- unsigned long flags;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
- spin_lock_irqsave(&uport->lock, flags);
clk_enable(msm_uport->clk);
/* clear interrupt */
msm_hs_write(uport, UARTDM_CR_ADDR, RESET_CTS);
+ /* Calling CLOCK API. Hence mb() requires here. */
+ mb();
uport->icount.cts++;
clk_disable(msm_uport->clk);
- spin_unlock_irqrestore(&uport->lock, flags);
/* clear the IOCTL TIOCMIWAIT if called */
wake_up_interruptible(&uport->state->port.delta_msr_wait);
@@ -1116,11 +1286,10 @@
struct circ_buf *tx_buf = &uport->state->xmit;
/* Cancel if tx tty buffer is not empty, dma is in flight,
- * or tx fifo is not empty, or rx fifo is not empty */
+ * or tx fifo is not empty */
if (msm_uport->clk_state != MSM_HS_CLK_REQUEST_OFF ||
!uart_circ_empty(tx_buf) || msm_uport->tx.dma_in_flight ||
- (msm_uport->imr_reg & UARTDM_ISR_TXLEV_BMSK) ||
- !(msm_uport->imr_reg & UARTDM_ISR_RXLEV_BMSK)) {
+ msm_uport->imr_reg & UARTDM_ISR_TXLEV_BMSK) {
return -1;
}
@@ -1134,6 +1303,11 @@
case CLK_REQ_OFF_START:
msm_uport->clk_req_off_state = CLK_REQ_OFF_RXSTALE_ISSUED;
msm_hs_write(uport, UARTDM_CR_ADDR, FORCE_STALE_EVENT);
+ /*
+ * Before returning make sure that device writel completed.
+ * Hence mb() requires here.
+ */
+ mb();
return 0; /* RXSTALE flush not complete - retry */
case CLK_REQ_OFF_RXSTALE_ISSUED:
case CLK_REQ_OFF_FLUSH_ISSUED:
@@ -1150,17 +1324,18 @@
/* we really want to clock off */
clk_disable(msm_uport->clk);
+ if (msm_uport->pclk)
+ clk_disable(msm_uport->pclk);
msm_uport->clk_state = MSM_HS_CLK_OFF;
-
- if (use_low_power_rx_wakeup(msm_uport)) {
- msm_uport->rx_wakeup.ignore = 1;
- enable_irq(msm_uport->rx_wakeup.irq);
+ if (use_low_power_wakeup(msm_uport)) {
+ msm_uport->wakeup.ignore = 1;
+ enable_irq(msm_uport->wakeup.irq);
}
+ wake_unlock(&msm_uport->dma_wake_lock);
return 1;
}
-static enum hrtimer_restart msm_hs_clk_off_retry(struct hrtimer *timer)
-{
+static enum hrtimer_restart msm_hs_clk_off_retry(struct hrtimer *timer) {
unsigned long flags;
int ret = HRTIMER_NORESTART;
struct msm_hs_port *msm_uport = container_of(timer, struct msm_hs_port,
@@ -1183,7 +1358,7 @@
{
unsigned long flags;
unsigned long isr_status;
- struct msm_hs_port *msm_uport = dev;
+ struct msm_hs_port *msm_uport = (struct msm_hs_port *)dev;
struct uart_port *uport = &msm_uport->uport;
struct circ_buf *tx_buf = &uport->state->xmit;
struct msm_hs_tx *tx = &msm_uport->tx;
@@ -1195,20 +1370,29 @@
/* Uart RX starting */
if (isr_status & UARTDM_ISR_RXLEV_BMSK) {
+ wake_lock(&rx->wake_lock); /* hold wakelock while rx dma */
msm_uport->imr_reg &= ~UARTDM_ISR_RXLEV_BMSK;
msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+ /* Complete device write for IMR. Hence mb() requires. */
+ mb();
}
/* Stale rx interrupt */
if (isr_status & UARTDM_ISR_RXSTALE_BMSK) {
msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_DISABLE);
msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT);
+ /*
+ * Complete device write before calling DMOV API. Hence
+ * mb() requires here.
+ */
+ mb();
if (msm_uport->clk_req_off_state == CLK_REQ_OFF_RXSTALE_ISSUED)
msm_uport->clk_req_off_state =
- CLK_REQ_OFF_FLUSH_ISSUED;
+ CLK_REQ_OFF_FLUSH_ISSUED;
+
if (rx->flush == FLUSH_NONE) {
rx->flush = FLUSH_DATA_READY;
- msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1);
+ msm_dmov_flush(msm_uport->dma_rx_channel);
}
}
/* tx ready interrupt */
@@ -1221,7 +1405,11 @@
msm_hs_write(uport, UARTDM_IMR_ADDR,
msm_uport->imr_reg);
}
-
+ /*
+ * Complete both writes before starting new TX.
+ * Hence mb() requires here.
+ */
+ mb();
/* Complete DMA TX transactions and submit new transactions */
tx_buf->tail = (tx_buf->tail + tx->tx_count) & ~UART_XMIT_SIZE;
@@ -1238,6 +1426,11 @@
/* TX FIFO is empty */
msm_uport->imr_reg &= ~UARTDM_ISR_TXLEV_BMSK;
msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+ /*
+ * Complete device write before starting clock_off request.
+ * Hence mb() requires here.
+ */
+ mb();
if (!msm_hs_check_clock_off_locked(uport))
hrtimer_start(&msm_uport->clk_off_timer,
msm_uport->clk_off_delay,
@@ -1246,58 +1439,52 @@
/* Change in CTS interrupt */
if (isr_status & UARTDM_ISR_DELTA_CTS_BMSK)
- msm_hs_handle_delta_cts(uport);
+ msm_hs_handle_delta_cts_locked(uport);
spin_unlock_irqrestore(&uport->lock, flags);
return IRQ_HANDLED;
}
-void msm_hs_request_clock_off_locked(struct uart_port *uport)
-{
+/* request to turn off uart clock once pending TX is flushed */
+void msm_hs_request_clock_off(struct uart_port *uport) {
+ unsigned long flags;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+ spin_lock_irqsave(&uport->lock, flags);
if (msm_uport->clk_state == MSM_HS_CLK_ON) {
msm_uport->clk_state = MSM_HS_CLK_REQUEST_OFF;
msm_uport->clk_req_off_state = CLK_REQ_OFF_START;
- if (!use_low_power_rx_wakeup(msm_uport))
- set_rfr_locked(uport, 0);
msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK;
msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
+ /*
+ * Complete device write before retuning back.
+ * Hence mb() requires here.
+ */
+ mb();
}
-}
-
-/**
- * msm_hs_request_clock_off - request to (i.e. asynchronously) turn off uart
- * clock once pending TX is flushed and Rx DMA command is terminated.
- * @uport: uart_port structure for the device instance.
- *
- * This functions puts the device into a partially active low power mode. It
- * waits to complete all pending tx transactions, flushes ongoing Rx DMA
- * command and terminates UART side Rx transaction, puts UART HW in non DMA
- * mode and then clocks off the device. A client calls this when no UART
- * data is expected. msm_request_clock_on() must be called before any further
- * UART can be sent or received.
- */
-void msm_hs_request_clock_off(struct uart_port *uport)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&uport->lock, flags);
- msm_hs_request_clock_off_locked(uport);
spin_unlock_irqrestore(&uport->lock, flags);
}
+EXPORT_SYMBOL(msm_hs_request_clock_off);
-void msm_hs_request_clock_on_locked(struct uart_port *uport)
-{
+static void msm_hs_request_clock_on_locked(struct uart_port *uport) {
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
unsigned int data;
+ int ret = 0;
switch (msm_uport->clk_state) {
case MSM_HS_CLK_OFF:
+ wake_lock(&msm_uport->dma_wake_lock);
clk_enable(msm_uport->clk);
- disable_irq_nosync(msm_uport->rx_wakeup.irq);
- /* fall-through */
+ if (msm_uport->pclk)
+ ret = clk_enable(msm_uport->pclk);
+ disable_irq_nosync(msm_uport->wakeup.irq);
+ if (unlikely(ret)) {
+ dev_err(uport->dev, "Clock ON Failure"
+ "Stalling HSUART\n");
+ break;
+ }
+ /* else fall-through */
case MSM_HS_CLK_REQUEST_OFF:
if (msm_uport->rx.flush == FLUSH_STOP ||
msm_uport->rx.flush == FLUSH_SHUTDOWN) {
@@ -1305,12 +1492,12 @@
data = msm_hs_read(uport, UARTDM_DMEN_ADDR);
data |= UARTDM_RX_DM_EN_BMSK;
msm_hs_write(uport, UARTDM_DMEN_ADDR, data);
+ /* Complete above device write. Hence mb() here. */
+ mb();
}
hrtimer_try_to_cancel(&msm_uport->clk_off_timer);
if (msm_uport->rx.flush == FLUSH_SHUTDOWN)
msm_hs_start_rx_locked(uport);
- if (!use_low_power_rx_wakeup(msm_uport))
- set_rfr_locked(uport, 1);
if (msm_uport->rx.flush == FLUSH_STOP)
msm_uport->rx.flush = FLUSH_IGNORE;
msm_uport->clk_state = MSM_HS_CLK_ON;
@@ -1322,38 +1509,28 @@
}
}
-/**
- * msm_hs_request_clock_on - Switch the device from partially active low
- * power mode to fully active (i.e. clock on) mode.
- * @uport: uart_port structure for the device.
- *
- * This function switches on the input clock, puts UART HW into DMA mode
- * and enqueues an Rx DMA command if the device was in partially active
- * mode. It has no effect if called with the device in inactive state.
- */
-void msm_hs_request_clock_on(struct uart_port *uport)
-{
+void msm_hs_request_clock_on(struct uart_port *uport) {
unsigned long flags;
-
spin_lock_irqsave(&uport->lock, flags);
msm_hs_request_clock_on_locked(uport);
spin_unlock_irqrestore(&uport->lock, flags);
}
+EXPORT_SYMBOL(msm_hs_request_clock_on);
-static irqreturn_t msm_hs_rx_wakeup_isr(int irq, void *dev)
+static irqreturn_t msm_hs_wakeup_isr(int irq, void *dev)
{
unsigned int wakeup = 0;
unsigned long flags;
- struct msm_hs_port *msm_uport = dev;
+ struct msm_hs_port *msm_uport = (struct msm_hs_port *)dev;
struct uart_port *uport = &msm_uport->uport;
struct tty_struct *tty = NULL;
spin_lock_irqsave(&uport->lock, flags);
- if (msm_uport->clk_state == MSM_HS_CLK_OFF) {
- /* ignore the first irq - it is a pending irq that occurred
+ if (msm_uport->clk_state == MSM_HS_CLK_OFF) {
+ /* ignore the first irq - it is a pending irq that occured
* before enable_irq() */
- if (msm_uport->rx_wakeup.ignore)
- msm_uport->rx_wakeup.ignore = 0;
+ if (msm_uport->wakeup.ignore)
+ msm_uport->wakeup.ignore = 0;
else
wakeup = 1;
}
@@ -1362,23 +1539,24 @@
/* the uart was clocked off during an rx, wake up and
* optionally inject char into tty rx */
msm_hs_request_clock_on_locked(uport);
- if (msm_uport->rx_wakeup.inject_rx) {
+ if (msm_uport->wakeup.inject_rx) {
tty = uport->state->port.tty;
tty_insert_flip_char(tty,
- msm_uport->rx_wakeup.rx_to_inject,
+ msm_uport->wakeup.rx_to_inject,
TTY_NORMAL);
- queue_work(msm_hs_workqueue, &msm_uport->rx.tty_work);
}
}
spin_unlock_irqrestore(&uport->lock, flags);
+ if (wakeup && msm_uport->wakeup.inject_rx)
+ tty_flip_buffer_push(tty);
return IRQ_HANDLED;
}
static const char *msm_hs_type(struct uart_port *port)
{
- return (port->type == PORT_MSM) ? "MSM_HS_UART" : NULL;
+ return ("MSM HS UART");
}
/* Called when port is opened */
@@ -1391,7 +1569,6 @@
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
struct circ_buf *tx_buf = &uport->state->xmit;
struct msm_hs_tx *tx = &msm_uport->tx;
- struct msm_hs_rx *rx = &msm_uport->rx;
rfr_level = uport->fifosize;
if (rfr_level > 16)
@@ -1400,16 +1577,10 @@
tx->dma_base = dma_map_single(uport->dev, tx_buf->buf, UART_XMIT_SIZE,
DMA_TO_DEVICE);
- /* do not let tty layer execute RX in global workqueue, use a
- * dedicated workqueue managed by this driver */
- uport->state->port.tty->low_latency = 1;
-
/* turn on uart clk */
- ret = msm_hs_init_clk_locked(uport);
- if (unlikely(ret)) {
- printk(KERN_ERR "Turning uartclk failed!\n");
- goto err_msm_hs_init_clk;
- }
+ ret = msm_hs_init_clk(uport);
+ if (unlikely(ret))
+ return ret;
/* Set auto RFR Level */
data = msm_hs_read(uport, UARTDM_MR1_ADDR);
@@ -1449,7 +1620,9 @@
tx->dma_in_flight = 0;
tx->xfer.complete_func = msm_hs_dmov_tx_callback;
- tx->xfer.execute_func = NULL;
+
+ tx->xfer.crci_mask = msm_dmov_build_crci_mask(1,
+ msm_uport->dma_tx_crci);
tx->command_ptr->cmd = CMD_LC |
CMD_DST_CRCI(msm_uport->dma_tx_crci) | CMD_MODE_BOX;
@@ -1462,49 +1635,38 @@
tx->command_ptr->dst_row_addr =
msm_uport->uport.mapbase + UARTDM_TF_ADDR;
-
- /* Turn on Uart Receive */
- rx->xfer.complete_func = msm_hs_dmov_rx_callback;
- rx->xfer.execute_func = NULL;
-
- rx->command_ptr->cmd = CMD_LC |
- CMD_SRC_CRCI(msm_uport->dma_rx_crci) | CMD_MODE_BOX;
-
- rx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16)
- | (MSM_UARTDM_BURST_SIZE);
- rx->command_ptr->row_offset = MSM_UARTDM_BURST_SIZE;
- rx->command_ptr->src_row_addr = uport->mapbase + UARTDM_RF_ADDR;
-
-
msm_uport->imr_reg |= UARTDM_ISR_RXSTALE_BMSK;
/* Enable reading the current CTS, no harm even if CTS is ignored */
msm_uport->imr_reg |= UARTDM_ISR_CURRENT_CTS_BMSK;
msm_hs_write(uport, UARTDM_TFWR_ADDR, 0); /* TXLEV on empty TX fifo */
+ /*
+ * Complete all device write related configuration before
+ * queuing RX request. Hence mb() requires here.
+ */
+ mb();
+ if (use_low_power_wakeup(msm_uport)) {
+ ret = irq_set_irq_wake(msm_uport->wakeup.irq, 1);
+ if (unlikely(ret))
+ return ret;
+ }
ret = request_irq(uport->irq, msm_hs_isr, IRQF_TRIGGER_HIGH,
"msm_hs_uart", msm_uport);
- if (unlikely(ret)) {
- printk(KERN_ERR "Request msm_hs_uart IRQ failed!\n");
- goto err_request_irq;
- }
- if (use_low_power_rx_wakeup(msm_uport)) {
- ret = request_irq(msm_uport->rx_wakeup.irq,
- msm_hs_rx_wakeup_isr,
+ if (unlikely(ret))
+ return ret;
+ if (use_low_power_wakeup(msm_uport)) {
+ ret = request_irq(msm_uport->wakeup.irq, msm_hs_wakeup_isr,
IRQF_TRIGGER_FALLING,
- "msm_hs_rx_wakeup", msm_uport);
- if (unlikely(ret)) {
- printk(KERN_ERR "Request msm_hs_rx_wakeup IRQ failed!\n");
- free_irq(uport->irq, msm_uport);
- goto err_request_irq;
- }
- disable_irq(msm_uport->rx_wakeup.irq);
+ "msm_hs_wakeup", msm_uport);
+ if (unlikely(ret))
+ return ret;
+ disable_irq(msm_uport->wakeup.irq);
}
spin_lock_irqsave(&uport->lock, flags);
- msm_hs_write(uport, UARTDM_RFWR_ADDR, 0);
msm_hs_start_rx_locked(uport);
spin_unlock_irqrestore(&uport->lock, flags);
@@ -1513,17 +1675,12 @@
dev_err(uport->dev, "set active error:%d\n", ret);
pm_runtime_enable(uport->dev);
- return 0;
-err_request_irq:
-err_msm_hs_init_clk:
- dma_unmap_single(uport->dev, tx->dma_base,
- UART_XMIT_SIZE, DMA_TO_DEVICE);
- return ret;
+ return 0;
}
/* Initialize tx and rx data structures */
-static int __devinit uartdm_init_port(struct uart_port *uport)
+static int uartdm_init_port(struct uart_port *uport)
{
int ret = 0;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
@@ -1538,7 +1695,7 @@
tx->command_ptr_ptr = kmalloc(sizeof(u32 *), GFP_KERNEL | __GFP_DMA);
if (!tx->command_ptr_ptr) {
ret = -ENOMEM;
- goto err_tx_command_ptr_ptr;
+ goto free_tx_command_ptr;
}
tx->mapped_cmd_ptr = dma_map_single(uport->dev, tx->command_ptr,
@@ -1549,20 +1706,28 @@
tx->xfer.cmdptr = DMOV_CMD_ADDR(tx->mapped_cmd_ptr_ptr);
init_waitqueue_head(&rx->wait);
+ wake_lock_init(&rx->wake_lock, WAKE_LOCK_SUSPEND, "msm_serial_hs_rx");
+ wake_lock_init(&msm_uport->dma_wake_lock, WAKE_LOCK_SUSPEND,
+ "msm_serial_hs_dma");
+
+ tasklet_init(&rx->tlet, msm_serial_hs_rx_tlet,
+ (unsigned long) &rx->tlet);
+ tasklet_init(&tx->tlet, msm_serial_hs_tx_tlet,
+ (unsigned long) &tx->tlet);
rx->pool = dma_pool_create("rx_buffer_pool", uport->dev,
UARTDM_RX_BUF_SIZE, 16, 0);
if (!rx->pool) {
pr_err("%s(): cannot allocate rx_buffer_pool", __func__);
ret = -ENOMEM;
- goto err_dma_pool_create;
+ goto exit_tasket_init;
}
rx->buffer = dma_pool_alloc(rx->pool, GFP_KERNEL, &rx->rbuffer);
if (!rx->buffer) {
pr_err("%s(): cannot allocate rx->buffer", __func__);
ret = -ENOMEM;
- goto err_dma_pool_alloc;
+ goto free_pool;
}
/* Allocate the command pointer. Needs to be 64 bit aligned */
@@ -1570,14 +1735,14 @@
if (!rx->command_ptr) {
pr_err("%s(): cannot allocate rx->command_ptr", __func__);
ret = -ENOMEM;
- goto err_rx_command_ptr;
+ goto free_rx_buffer;
}
rx->command_ptr_ptr = kmalloc(sizeof(u32 *), GFP_KERNEL | __GFP_DMA);
if (!rx->command_ptr_ptr) {
pr_err("%s(): cannot allocate rx->command_ptr_ptr", __func__);
ret = -ENOMEM;
- goto err_rx_command_ptr_ptr;
+ goto free_rx_command_ptr;
}
rx->command_ptr->num_rows = ((UARTDM_RX_BUF_SIZE >> 4) << 16) |
@@ -1585,6 +1750,22 @@
rx->command_ptr->dst_row_addr = rx->rbuffer;
+ /* Set up Uart Receive */
+ msm_hs_write(uport, UARTDM_RFWR_ADDR, 0);
+
+ rx->xfer.complete_func = msm_hs_dmov_rx_callback;
+
+ rx->xfer.crci_mask = msm_dmov_build_crci_mask(1,
+ msm_uport->dma_rx_crci);
+
+ rx->command_ptr->cmd = CMD_LC |
+ CMD_SRC_CRCI(msm_uport->dma_rx_crci) | CMD_MODE_BOX;
+
+ rx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16)
+ | (MSM_UARTDM_BURST_SIZE);
+ rx->command_ptr->row_offset = MSM_UARTDM_BURST_SIZE;
+ rx->command_ptr->src_row_addr = uport->mapbase + UARTDM_RF_ADDR;
+
rx->mapped_cmd_ptr = dma_map_single(uport->dev, rx->command_ptr,
sizeof(dmov_box), DMA_TO_DEVICE);
@@ -1594,36 +1775,43 @@
sizeof(u32 *), DMA_TO_DEVICE);
rx->xfer.cmdptr = DMOV_CMD_ADDR(rx->cmdptr_dmaaddr);
- INIT_WORK(&rx->tty_work, msm_hs_tty_flip_buffer_work);
+ INIT_DELAYED_WORK(&rx->flip_insert_work, flip_insert_work);
return ret;
-err_rx_command_ptr_ptr:
+free_rx_command_ptr:
kfree(rx->command_ptr);
-err_rx_command_ptr:
+
+free_rx_buffer:
dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer,
- msm_uport->rx.rbuffer);
-err_dma_pool_alloc:
+ msm_uport->rx.rbuffer);
+
+free_pool:
dma_pool_destroy(msm_uport->rx.pool);
-err_dma_pool_create:
+
+exit_tasket_init:
+ wake_lock_destroy(&msm_uport->rx.wake_lock);
+ wake_lock_destroy(&msm_uport->dma_wake_lock);
+ tasklet_kill(&msm_uport->tx.tlet);
+ tasklet_kill(&msm_uport->rx.tlet);
dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr_ptr,
- sizeof(u32 *), DMA_TO_DEVICE);
+ sizeof(u32 *), DMA_TO_DEVICE);
dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr,
- sizeof(dmov_box), DMA_TO_DEVICE);
+ sizeof(dmov_box), DMA_TO_DEVICE);
kfree(msm_uport->tx.command_ptr_ptr);
-err_tx_command_ptr_ptr:
+
+free_tx_command_ptr:
kfree(msm_uport->tx.command_ptr);
return ret;
}
-static int __devinit msm_hs_probe(struct platform_device *pdev)
+static int __init msm_hs_probe(struct platform_device *pdev)
{
int ret;
struct uart_port *uport;
struct msm_hs_port *msm_uport;
struct resource *resource;
- const struct msm_serial_hs_platform_data *pdata =
- pdev->dev.platform_data;
+ struct msm_serial_hs_platform_data *pdata = pdev->dev.platform_data;
if (pdev->id < 0 || pdev->id >= UARTDM_NR) {
printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id);
@@ -1638,40 +1826,37 @@
resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!resource))
return -ENXIO;
+ uport->mapbase = resource->start; /* virtual address */
- uport->mapbase = resource->start;
+ uport->membase = ioremap(uport->mapbase, PAGE_SIZE);
+ if (unlikely(!uport->membase))
+ return -ENOMEM;
+
uport->irq = platform_get_irq(pdev, 0);
if (unlikely(uport->irq < 0))
return -ENXIO;
- if (unlikely(irq_set_irq_wake(uport->irq, 1)))
- return -ENXIO;
-
- if (pdata == NULL || pdata->rx_wakeup_irq < 0)
- msm_uport->rx_wakeup.irq = -1;
- else {
- msm_uport->rx_wakeup.irq = pdata->rx_wakeup_irq;
- msm_uport->rx_wakeup.ignore = 1;
- msm_uport->rx_wakeup.inject_rx = pdata->inject_rx_on_wakeup;
- msm_uport->rx_wakeup.rx_to_inject = pdata->rx_to_inject;
-
- if (unlikely(msm_uport->rx_wakeup.irq < 0))
- return -ENXIO;
-
- if (unlikely(irq_set_irq_wake(msm_uport->rx_wakeup.irq, 1)))
- return -ENXIO;
- }
-
if (pdata == NULL)
- msm_uport->exit_lpm_cb = NULL;
- else
- msm_uport->exit_lpm_cb = pdata->exit_lpm_cb;
+ msm_uport->wakeup.irq = -1;
+ else {
+ msm_uport->wakeup.irq = pdata->wakeup_irq;
+ msm_uport->wakeup.ignore = 1;
+ msm_uport->wakeup.inject_rx = pdata->inject_rx_on_wakeup;
+ msm_uport->wakeup.rx_to_inject = pdata->rx_to_inject;
+
+ if (unlikely(msm_uport->wakeup.irq < 0))
+ return -ENXIO;
+
+ if (pdata->gpio_config)
+ if (unlikely(pdata->gpio_config(1)))
+ dev_err(uport->dev, "Cannot configure"
+ "gpios\n");
+ }
resource = platform_get_resource_byname(pdev, IORESOURCE_DMA,
"uartdm_channels");
if (unlikely(!resource))
return -ENXIO;
-
msm_uport->dma_tx_channel = resource->start;
msm_uport->dma_rx_channel = resource->end;
@@ -1679,67 +1864,93 @@
"uartdm_crci");
if (unlikely(!resource))
return -ENXIO;
-
msm_uport->dma_tx_crci = resource->start;
msm_uport->dma_rx_crci = resource->end;
uport->iotype = UPIO_MEM;
- uport->fifosize = UART_FIFOSIZE;
+ uport->fifosize = 64;
uport->ops = &msm_hs_ops;
uport->flags = UPF_BOOT_AUTOCONF;
- uport->uartclk = UARTCLK;
+ uport->uartclk = 7372800;
msm_uport->imr_reg = 0x0;
+
msm_uport->clk = clk_get(&pdev->dev, "uartdm_clk");
if (IS_ERR(msm_uport->clk))
return PTR_ERR(msm_uport->clk);
+ msm_uport->pclk = clk_get(&pdev->dev, "uartdm_pclk");
+ /*
+ * Some configurations do not require explicit pclk control so
+ * do not flag error on pclk get failure.
+ */
+ if (IS_ERR(msm_uport->pclk))
+ msm_uport->pclk = NULL;
+
+ ret = clk_set_rate(msm_uport->clk, uport->uartclk);
+ if (ret) {
+ printk(KERN_WARNING "Error setting clock rate on UART\n");
+ return ret;
+ }
+
ret = uartdm_init_port(uport);
if (unlikely(ret))
return ret;
+ /* configure the CR Protection to Enable */
+ msm_hs_write(uport, UARTDM_CR_ADDR, CR_PROTECTION_EN);
+ /*
+ * Enable Command register protection before going ahead as this hw
+ * configuration makes sure that issued cmd to CR register gets complete
+ * before next issued cmd start. Hence mb() requires here.
+ */
+ mb();
+
msm_uport->clk_state = MSM_HS_CLK_PORT_OFF;
hrtimer_init(&msm_uport->clk_off_timer, CLOCK_MONOTONIC,
HRTIMER_MODE_REL);
msm_uport->clk_off_timer.function = msm_hs_clk_off_retry;
msm_uport->clk_off_delay = ktime_set(0, 1000000); /* 1ms */
+ ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_clock.attr);
+ if (unlikely(ret))
+ return ret;
+
+ msm_serial_debugfs_init(msm_uport, pdev->id);
+
uport->line = pdev->id;
return uart_add_one_port(&msm_hs_driver, uport);
}
static int __init msm_serial_hs_init(void)
{
- int ret, i;
+ int ret;
+ int i;
/* Init all UARTS as non-configured */
for (i = 0; i < UARTDM_NR; i++)
q_uart_port[i].uport.type = PORT_UNKNOWN;
- msm_hs_workqueue = create_singlethread_workqueue("msm_serial_hs");
- if (unlikely(!msm_hs_workqueue))
- return -ENOMEM;
-
ret = uart_register_driver(&msm_hs_driver);
if (unlikely(ret)) {
- printk(KERN_ERR "%s failed to load\n", __func__);
- goto err_uart_register_driver;
+ printk(KERN_ERR "%s failed to load\n", __FUNCTION__);
+ return ret;
}
+ debug_base = debugfs_create_dir("msm_serial_hs", NULL);
+ if (IS_ERR_OR_NULL(debug_base))
+ pr_info("msm_serial_hs: Cannot create debugfs dir\n");
- ret = platform_driver_register(&msm_serial_hs_platform_driver);
+ ret = platform_driver_probe(&msm_serial_hs_platform_driver,
+ msm_hs_probe);
if (ret) {
- printk(KERN_ERR "%s failed to load\n", __func__);
- goto err_platform_driver_register;
+ printk(KERN_ERR "%s failed to load\n", __FUNCTION__);
+ debugfs_remove_recursive(debug_base);
+ uart_unregister_driver(&msm_hs_driver);
+ return ret;
}
- return ret;
-
-err_platform_driver_register:
- uart_unregister_driver(&msm_hs_driver);
-err_uart_register_driver:
- destroy_workqueue(msm_hs_workqueue);
+ printk(KERN_INFO "msm_serial_hs module loaded\n");
return ret;
}
-module_init(msm_serial_hs_init);
/*
* Called by the upper layer when port is closed.
@@ -1752,31 +1963,37 @@
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
BUG_ON(msm_uport->rx.flush < FLUSH_STOP);
+ tasklet_kill(&msm_uport->tx.tlet);
+ wait_event(msm_uport->rx.wait, msm_uport->rx.flush == FLUSH_SHUTDOWN);
+ tasklet_kill(&msm_uport->rx.tlet);
+ cancel_delayed_work_sync(&msm_uport->rx.flip_insert_work);
spin_lock_irqsave(&uport->lock, flags);
clk_enable(msm_uport->clk);
+ pm_runtime_disable(uport->dev);
+ pm_runtime_set_suspended(uport->dev);
+
/* Disable the transmitter */
msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_TX_DISABLE_BMSK);
/* Disable the receiver */
msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_RX_DISABLE_BMSK);
- pm_runtime_disable(uport->dev);
- pm_runtime_set_suspended(uport->dev);
-
- /* Free the interrupt */
- free_irq(uport->irq, msm_uport);
- if (use_low_power_rx_wakeup(msm_uport))
- free_irq(msm_uport->rx_wakeup.irq, msm_uport);
-
msm_uport->imr_reg = 0;
msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg);
-
- wait_event(msm_uport->rx.wait, msm_uport->rx.flush == FLUSH_SHUTDOWN);
+ /*
+ * Complete all device write before actually disabling uartclk.
+ * Hence mb() requires here.
+ */
+ mb();
clk_disable(msm_uport->clk); /* to balance local clk_enable() */
- if (msm_uport->clk_state != MSM_HS_CLK_OFF)
+ if (msm_uport->clk_state != MSM_HS_CLK_OFF) {
clk_disable(msm_uport->clk); /* to balance clk_state */
+ if (msm_uport->pclk)
+ clk_disable(msm_uport->pclk);
+ wake_unlock(&msm_uport->dma_wake_lock);
+ }
msm_uport->clk_state = MSM_HS_CLK_PORT_OFF;
dma_unmap_single(uport->dev, msm_uport->tx.dma_base,
@@ -1784,20 +2001,22 @@
spin_unlock_irqrestore(&uport->lock, flags);
- if (cancel_work_sync(&msm_uport->rx.tty_work))
- msm_hs_tty_flip_buffer_work(&msm_uport->rx.tty_work);
+ if (use_low_power_wakeup(msm_uport))
+ irq_set_irq_wake(msm_uport->wakeup.irq, 0);
+
+ /* Free the interrupt */
+ free_irq(uport->irq, msm_uport);
+ if (use_low_power_wakeup(msm_uport))
+ free_irq(msm_uport->wakeup.irq, msm_uport);
}
static void __exit msm_serial_hs_exit(void)
{
- flush_workqueue(msm_hs_workqueue);
- destroy_workqueue(msm_hs_workqueue);
+ printk(KERN_INFO "msm_serial_hs module removed\n");
platform_driver_unregister(&msm_serial_hs_platform_driver);
uart_unregister_driver(&msm_hs_driver);
}
-module_exit(msm_serial_hs_exit);
-#ifdef CONFIG_PM_RUNTIME
static int msm_hs_runtime_idle(struct device *dev)
{
/*
@@ -1812,7 +2031,6 @@
struct platform_device *pdev = container_of(dev, struct
platform_device, dev);
struct msm_hs_port *msm_uport = &q_uart_port[pdev->id];
-
msm_hs_request_clock_on(&msm_uport->uport);
return 0;
}
@@ -1822,15 +2040,9 @@
struct platform_device *pdev = container_of(dev, struct
platform_device, dev);
struct msm_hs_port *msm_uport = &q_uart_port[pdev->id];
-
msm_hs_request_clock_off(&msm_uport->uport);
return 0;
}
-#else
-#define msm_hs_runtime_idle NULL
-#define msm_hs_runtime_resume NULL
-#define msm_hs_runtime_suspend NULL
-#endif
static const struct dev_pm_ops msm_hs_dev_pm_ops = {
.runtime_suspend = msm_hs_runtime_suspend,
@@ -1839,11 +2051,9 @@
};
static struct platform_driver msm_serial_hs_platform_driver = {
- .probe = msm_hs_probe,
- .remove = __devexit_p(msm_hs_remove),
+ .remove = msm_hs_remove,
.driver = {
.name = "msm_serial_hs",
- .owner = THIS_MODULE,
.pm = &msm_hs_dev_pm_ops,
},
};
@@ -1868,13 +2078,14 @@
.startup = msm_hs_startup,
.shutdown = msm_hs_shutdown,
.set_termios = msm_hs_set_termios,
- .pm = msm_hs_pm,
.type = msm_hs_type,
.config_port = msm_hs_config_port,
.release_port = msm_hs_release_port,
.request_port = msm_hs_request_port,
};
+module_init(msm_serial_hs_init);
+module_exit(msm_serial_hs_exit);
MODULE_DESCRIPTION("High Speed UART Driver for the MSM chipset");
MODULE_VERSION("1.2");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/tty/serial/msm_serial_hs_hwreg.h b/drivers/tty/serial/msm_serial_hs_hwreg.h
new file mode 100644
index 0000000..001d555
--- /dev/null
+++ b/drivers/tty/serial/msm_serial_hs_hwreg.h
@@ -0,0 +1,179 @@
+/* drivers/serial/msm_serial_hs_hwreg.h
+ *
+ * Copyright (c) 2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * All source code in this file is licensed under the following license
+ * except where indicated.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, you can find it at http://www.fsf.org
+ */
+
+#ifndef MSM_SERIAL_HS_HWREG_H
+#define MSM_SERIAL_HS_HWREG_H
+
+#define GSBI_CONTROL_ADDR 0x0
+#define GSBI_PROTOCOL_CODE_MASK 0x30
+#define GSBI_PROTOCOL_I2C_UART 0x60
+#define GSBI_PROTOCOL_UART 0x40
+#define GSBI_PROTOCOL_IDLE 0x0
+
+#define TCSR_ADM_1_A_CRCI_MUX_SEL 0x78
+#define TCSR_ADM_1_B_CRCI_MUX_SEL 0x7C
+#define ADM1_CRCI_GSBI6_RX_SEL 0x800
+#define ADM1_CRCI_GSBI6_TX_SEL 0x400
+
+#define UARTDM_MR1_ADDR 0x0
+#define UARTDM_MR2_ADDR 0x4
+
+/* write only register */
+#define UARTDM_CSR_ADDR 0x8
+#define UARTDM_CSR_115200 0xFF
+#define UARTDM_CSR_57600 0xEE
+#define UARTDM_CSR_38400 0xDD
+#define UARTDM_CSR_28800 0xCC
+#define UARTDM_CSR_19200 0xBB
+#define UARTDM_CSR_14400 0xAA
+#define UARTDM_CSR_9600 0x99
+#define UARTDM_CSR_7200 0x88
+#define UARTDM_CSR_4800 0x77
+#define UARTDM_CSR_3600 0x66
+#define UARTDM_CSR_2400 0x55
+#define UARTDM_CSR_1200 0x44
+#define UARTDM_CSR_600 0x33
+#define UARTDM_CSR_300 0x22
+#define UARTDM_CSR_150 0x11
+#define UARTDM_CSR_75 0x00
+
+/* write only register */
+#define UARTDM_TF_ADDR 0x70
+#define UARTDM_TF2_ADDR 0x74
+#define UARTDM_TF3_ADDR 0x78
+#define UARTDM_TF4_ADDR 0x7C
+
+/* write only register */
+#define UARTDM_CR_ADDR 0x10
+/* write only register */
+#define UARTDM_IMR_ADDR 0x14
+
+#define UARTDM_IPR_ADDR 0x18
+#define UARTDM_TFWR_ADDR 0x1c
+#define UARTDM_RFWR_ADDR 0x20
+#define UARTDM_HCR_ADDR 0x24
+#define UARTDM_DMRX_ADDR 0x34
+#define UARTDM_IRDA_ADDR 0x38
+#define UARTDM_DMEN_ADDR 0x3c
+
+/* UART_DM_NO_CHARS_FOR_TX */
+#define UARTDM_NCF_TX_ADDR 0x40
+
+#define UARTDM_BADR_ADDR 0x44
+
+#define UARTDM_SIM_CFG_ADDR 0x80
+
+/* Read Only register */
+#define UARTDM_SR_ADDR 0x8
+
+/* Read Only register */
+#define UARTDM_RF_ADDR 0x70
+#define UARTDM_RF2_ADDR 0x74
+#define UARTDM_RF3_ADDR 0x78
+#define UARTDM_RF4_ADDR 0x7C
+
+/* Read Only register */
+#define UARTDM_MISR_ADDR 0x10
+
+/* Read Only register */
+#define UARTDM_ISR_ADDR 0x14
+#define UARTDM_RX_TOTAL_SNAP_ADDR 0x38
+
+#define UARTDM_RXFS_ADDR 0x50
+
+/* Register field Mask Mapping */
+#define UARTDM_SR_RX_BREAK_BMSK BIT(6)
+#define UARTDM_SR_PAR_FRAME_BMSK BIT(5)
+#define UARTDM_SR_OVERRUN_BMSK BIT(4)
+#define UARTDM_SR_TXEMT_BMSK BIT(3)
+#define UARTDM_SR_TXRDY_BMSK BIT(2)
+#define UARTDM_SR_RXRDY_BMSK BIT(0)
+
+#define UARTDM_CR_TX_DISABLE_BMSK BIT(3)
+#define UARTDM_CR_RX_DISABLE_BMSK BIT(1)
+#define UARTDM_CR_TX_EN_BMSK BIT(2)
+#define UARTDM_CR_RX_EN_BMSK BIT(0)
+
+/* UARTDM_CR channel_comman bit value (register field is bits 8:4) */
+#define RESET_RX 0x10
+#define RESET_TX 0x20
+#define RESET_ERROR_STATUS 0x30
+#define RESET_BREAK_INT 0x40
+#define START_BREAK 0x50
+#define STOP_BREAK 0x60
+#define RESET_CTS 0x70
+#define RESET_STALE_INT 0x80
+#define RFR_LOW 0xD0
+#define RFR_HIGH 0xE0
+#define CR_PROTECTION_EN 0x100
+#define STALE_EVENT_ENABLE 0x500
+#define STALE_EVENT_DISABLE 0x600
+#define FORCE_STALE_EVENT 0x400
+#define CLEAR_TX_READY 0x300
+#define RESET_TX_ERROR 0x800
+#define RESET_TX_DONE 0x810
+
+#define UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00
+#define UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f
+#define UARTDM_MR1_CTS_CTL_BMSK 0x40
+#define UARTDM_MR1_RX_RDY_CTL_BMSK 0x80
+
+#define UARTDM_MR2_LOOP_MODE_BMSK 0x80
+#define UARTDM_MR2_ERROR_MODE_BMSK 0x40
+#define UARTDM_MR2_BITS_PER_CHAR_BMSK 0x30
+
+#define UARTDM_MR2_BITS_PER_CHAR_8 (0x3 << 4)
+
+/* bits per character configuration */
+#define FIVE_BPC (0 << 4)
+#define SIX_BPC (1 << 4)
+#define SEVEN_BPC (2 << 4)
+#define EIGHT_BPC (3 << 4)
+
+#define UARTDM_MR2_STOP_BIT_LEN_BMSK 0xc
+#define STOP_BIT_ONE (1 << 2)
+#define STOP_BIT_TWO (3 << 2)
+
+#define UARTDM_MR2_PARITY_MODE_BMSK 0x3
+
+/* Parity configuration */
+#define NO_PARITY 0x0
+#define EVEN_PARITY 0x1
+#define ODD_PARITY 0x2
+#define SPACE_PARITY 0x3
+
+#define UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80
+#define UARTDM_IPR_STALE_LSB_BMSK 0x1f
+
+/* These can be used for both ISR and IMR register */
+#define UARTDM_ISR_TX_READY_BMSK BIT(7)
+#define UARTDM_ISR_CURRENT_CTS_BMSK BIT(6)
+#define UARTDM_ISR_DELTA_CTS_BMSK BIT(5)
+#define UARTDM_ISR_RXLEV_BMSK BIT(4)
+#define UARTDM_ISR_RXSTALE_BMSK BIT(3)
+#define UARTDM_ISR_RXBREAK_BMSK BIT(2)
+#define UARTDM_ISR_RXHUNT_BMSK BIT(1)
+#define UARTDM_ISR_TXLEV_BMSK BIT(0)
+
+/* Field definitions for UART_DM_DMEN*/
+#define UARTDM_TX_DM_EN_BMSK 0x1
+#define UARTDM_RX_DM_EN_BMSK 0x2
+
+#endif /* MSM_SERIAL_HS_HWREG_H */
diff --git a/drivers/tty/serial/msm_serial_hs_lite.c b/drivers/tty/serial/msm_serial_hs_lite.c
new file mode 100644
index 0000000..83b734e
--- /dev/null
+++ b/drivers/tty/serial/msm_serial_hs_lite.c
@@ -0,0 +1,1216 @@
+/*
+ * drivers/serial/msm_serial.c - driver for msm7k serial device and console
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Acknowledgements:
+ * This file is based on msm_serial.c, originally
+ * Written by Robert Love <rlove@google.com> */
+
+#if defined(CONFIG_SERIAL_MSM_HSL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/hrtimer.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/console.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/nmi.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/gpio.h>
+#include <mach/board.h>
+#include <mach/msm_serial_hs_lite.h>
+#include <asm/mach-types.h>
+#include "msm_serial_hs_hwreg.h"
+
+struct msm_hsl_port {
+ struct uart_port uart;
+ char name[16];
+ struct clk *clk;
+ struct clk *pclk;
+ unsigned int imr;
+ unsigned int *uart_csr_code;
+ unsigned int *gsbi_mapbase;
+ unsigned int *mapped_gsbi;
+ int is_uartdm;
+ unsigned int old_snap_state;
+};
+
+#define UART_TO_MSM(uart_port) ((struct msm_hsl_port *) uart_port)
+#define is_console(port) ((port)->cons && \
+ (port)->cons->index == (port)->line)
+static inline void wait_for_xmitr(struct uart_port *port, int bits);
+static inline void msm_hsl_write(struct uart_port *port,
+ unsigned int val, unsigned int off)
+{
+ iowrite32(val, port->membase + off);
+}
+static inline unsigned int msm_hsl_read(struct uart_port *port,
+ unsigned int off)
+{
+ return ioread32(port->membase + off);
+}
+
+static unsigned int msm_serial_hsl_has_gsbi(struct uart_port *port)
+{
+ return UART_TO_MSM(port)->is_uartdm;
+}
+
+static int clk_en(struct uart_port *port, int enable)
+{
+ struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+ int ret = 0;
+
+ if (enable) {
+
+ ret = clk_enable(msm_hsl_port->clk);
+ if (ret)
+ goto err;
+ if (msm_hsl_port->pclk) {
+ ret = clk_enable(msm_hsl_port->pclk);
+ if (ret) {
+ clk_disable(msm_hsl_port->clk);
+ goto err;
+ }
+ }
+ } else {
+ clk_disable(msm_hsl_port->clk);
+ if (msm_hsl_port->pclk)
+ clk_disable(msm_hsl_port->pclk);
+ }
+err:
+ return ret;
+}
+
+static void msm_hsl_stop_tx(struct uart_port *port)
+{
+ struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+
+ clk_en(port, 1);
+
+ msm_hsl_port->imr &= ~UARTDM_ISR_TXLEV_BMSK;
+ msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
+
+ clk_en(port, 0);
+}
+
+static void msm_hsl_start_tx(struct uart_port *port)
+{
+ struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+
+ clk_en(port, 1);
+
+ msm_hsl_port->imr |= UARTDM_ISR_TXLEV_BMSK;
+ msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
+
+ clk_en(port, 0);
+}
+
+static void msm_hsl_stop_rx(struct uart_port *port)
+{
+ struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+
+ clk_en(port, 1);
+
+ msm_hsl_port->imr &= ~(UARTDM_ISR_RXLEV_BMSK |
+ UARTDM_ISR_RXSTALE_BMSK);
+ msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
+
+ clk_en(port, 0);
+}
+
+static void msm_hsl_enable_ms(struct uart_port *port)
+{
+ struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+
+ clk_en(port, 1);
+
+ msm_hsl_port->imr |= UARTDM_ISR_DELTA_CTS_BMSK;
+ msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
+
+ clk_en(port, 0);
+}
+
+static void handle_rx(struct uart_port *port, unsigned int misr)
+{
+ struct tty_struct *tty = port->state->port.tty;
+ unsigned int sr;
+ int count = 0;
+ struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+
+ /*
+ * Handle overrun. My understanding of the hardware is that overrun
+ * is not tied to the RX buffer, so we handle the case out of band.
+ */
+ if ((msm_hsl_read(port, UARTDM_SR_ADDR) & UARTDM_SR_OVERRUN_BMSK)) {
+ port->icount.overrun++;
+ tty_insert_flip_char(tty, 0, TTY_OVERRUN);
+ msm_hsl_write(port, RESET_ERROR_STATUS, UARTDM_CR_ADDR);
+ }
+
+ if (misr & UARTDM_ISR_RXSTALE_BMSK) {
+ count = msm_hsl_read(port, UARTDM_RX_TOTAL_SNAP_ADDR) -
+ msm_hsl_port->old_snap_state;
+ msm_hsl_port->old_snap_state = 0;
+ } else {
+ count = 4 * (msm_hsl_read(port, UARTDM_RFWR_ADDR));
+ msm_hsl_port->old_snap_state += count;
+ }
+
+ /* and now the main RX loop */
+ while (count > 0) {
+ unsigned int c;
+ char flag = TTY_NORMAL;
+
+ sr = msm_hsl_read(port, UARTDM_SR_ADDR);
+ if ((sr &
+ UARTDM_SR_RXRDY_BMSK) == 0) {
+ msm_hsl_port->old_snap_state -= count;
+ break;
+ }
+ c = msm_hsl_read(port, UARTDM_RF_ADDR);
+ if (sr & UARTDM_SR_RX_BREAK_BMSK) {
+ port->icount.brk++;
+ if (uart_handle_break(port))
+ continue;
+ } else if (sr & UARTDM_SR_PAR_FRAME_BMSK) {
+ port->icount.frame++;
+ } else {
+ port->icount.rx++;
+ }
+
+ /* Mask conditions we're ignorning. */
+ sr &= port->read_status_mask;
+ if (sr & UARTDM_SR_RX_BREAK_BMSK)
+ flag = TTY_BREAK;
+ else if (sr & UARTDM_SR_PAR_FRAME_BMSK)
+ flag = TTY_FRAME;
+
+ /* TODO: handle sysrq */
+ /* if (!uart_handle_sysrq_char(port, c)) */
+ tty_insert_flip_string(tty, (char *) &c,
+ (count > 4) ? 4 : count);
+ count -= 4;
+ }
+
+ tty_flip_buffer_push(tty);
+}
+
+static void handle_tx(struct uart_port *port)
+{
+ struct circ_buf *xmit = &port->state->xmit;
+ int sent_tx;
+ int tx_count;
+ int x;
+ unsigned int tf_pointer = 0;
+
+ tx_count = uart_circ_chars_pending(xmit);
+
+ if (tx_count > (UART_XMIT_SIZE - xmit->tail))
+ tx_count = UART_XMIT_SIZE - xmit->tail;
+ if (tx_count >= port->fifosize)
+ tx_count = port->fifosize;
+
+ /* Handle x_char */
+ if (port->x_char) {
+ wait_for_xmitr(port, UARTDM_ISR_TX_READY_BMSK);
+ msm_hsl_write(port, tx_count + 1, UARTDM_NCF_TX_ADDR);
+ msm_hsl_write(port, port->x_char, UARTDM_TF_ADDR);
+ port->icount.tx++;
+ port->x_char = 0;
+ } else if (tx_count) {
+ wait_for_xmitr(port, UARTDM_ISR_TX_READY_BMSK);
+ msm_hsl_write(port, tx_count, UARTDM_NCF_TX_ADDR);
+ }
+ if (!tx_count) {
+ msm_hsl_stop_tx(port);
+ return;
+ }
+
+ while (tf_pointer < tx_count) {
+ if (unlikely(!(msm_hsl_read(port, UARTDM_SR_ADDR) &
+ UARTDM_SR_TXRDY_BMSK)))
+ continue;
+ switch (tx_count - tf_pointer) {
+ case 1: {
+ x = xmit->buf[xmit->tail];
+ port->icount.tx++;
+ break;
+ }
+ case 2: {
+ x = xmit->buf[xmit->tail]
+ | xmit->buf[xmit->tail+1] << 8;
+ port->icount.tx += 2;
+ break;
+ }
+ case 3: {
+ x = xmit->buf[xmit->tail]
+ | xmit->buf[xmit->tail+1] << 8
+ | xmit->buf[xmit->tail + 2] << 16;
+ port->icount.tx += 3;
+ break;
+ }
+ default: {
+ x = *((int *)&(xmit->buf[xmit->tail]));
+ port->icount.tx += 4;
+ break;
+ }
+ }
+ msm_hsl_write(port, x, UARTDM_TF_ADDR);
+ xmit->tail = ((tx_count - tf_pointer < 4) ?
+ (tx_count - tf_pointer + xmit->tail) :
+ (xmit->tail + 4)) & (UART_XMIT_SIZE - 1);
+ tf_pointer += 4;
+ sent_tx = 1;
+ }
+
+ if (uart_circ_empty(xmit))
+ msm_hsl_stop_tx(port);
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(port);
+
+}
+
+static void handle_delta_cts(struct uart_port *port)
+{
+ msm_hsl_write(port, RESET_CTS, UARTDM_CR_ADDR);
+ port->icount.cts++;
+ wake_up_interruptible(&port->state->port.delta_msr_wait);
+}
+
+static irqreturn_t msm_hsl_irq(int irq, void *dev_id)
+{
+ struct uart_port *port = dev_id;
+ struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+ unsigned int misr;
+ unsigned long flags;
+
+ spin_lock_irqsave(&port->lock, flags);
+ clk_en(port, 1);
+ misr = msm_hsl_read(port, UARTDM_MISR_ADDR);
+ msm_hsl_write(port, 0, UARTDM_IMR_ADDR); /* disable interrupt */
+
+ if (misr & (UARTDM_ISR_RXSTALE_BMSK | UARTDM_ISR_RXLEV_BMSK)) {
+ handle_rx(port, misr);
+ if (misr & (UARTDM_ISR_RXSTALE_BMSK))
+ msm_hsl_write(port, RESET_STALE_INT, UARTDM_CR_ADDR);
+ msm_hsl_write(port, 6500, UARTDM_DMRX_ADDR);
+ msm_hsl_write(port, STALE_EVENT_ENABLE, UARTDM_CR_ADDR);
+ }
+ if (misr & UARTDM_ISR_TXLEV_BMSK)
+ handle_tx(port);
+
+ if (misr & UARTDM_ISR_DELTA_CTS_BMSK)
+ handle_delta_cts(port);
+
+ /* restore interrupt */
+ msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
+ clk_en(port, 0);
+ spin_unlock_irqrestore(&port->lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+static unsigned int msm_hsl_tx_empty(struct uart_port *port)
+{
+ unsigned int ret;
+
+ clk_en(port, 1);
+ ret = (msm_hsl_read(port, UARTDM_SR_ADDR) &
+ UARTDM_SR_TXEMT_BMSK) ? TIOCSER_TEMT : 0;
+ clk_en(port, 0);
+
+ return ret;
+}
+
+static void msm_hsl_reset(struct uart_port *port)
+{
+ /* reset everything */
+ msm_hsl_write(port, RESET_RX, UARTDM_CR_ADDR);
+ msm_hsl_write(port, RESET_TX, UARTDM_CR_ADDR);
+ msm_hsl_write(port, RESET_ERROR_STATUS, UARTDM_CR_ADDR);
+ msm_hsl_write(port, RESET_BREAK_INT, UARTDM_CR_ADDR);
+ msm_hsl_write(port, RESET_CTS, UARTDM_CR_ADDR);
+ msm_hsl_write(port, RFR_LOW, UARTDM_CR_ADDR);
+}
+
+static unsigned int msm_hsl_get_mctrl(struct uart_port *port)
+{
+ return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
+}
+
+static void msm_hsl_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+ unsigned int mr;
+ unsigned int loop_mode;
+
+ clk_en(port, 1);
+
+ mr = msm_hsl_read(port, UARTDM_MR1_ADDR);
+
+ if (!(mctrl & TIOCM_RTS)) {
+ mr &= ~UARTDM_MR1_RX_RDY_CTL_BMSK;
+ msm_hsl_write(port, mr, UARTDM_MR1_ADDR);
+ msm_hsl_write(port, RFR_HIGH, UARTDM_CR_ADDR);
+ } else {
+ mr |= UARTDM_MR1_RX_RDY_CTL_BMSK;
+ msm_hsl_write(port, mr, UARTDM_MR1_ADDR);
+ }
+
+ loop_mode = TIOCM_LOOP & mctrl;
+ if (loop_mode) {
+ mr = msm_hsl_read(port, UARTDM_MR2_ADDR);
+ mr |= UARTDM_MR2_LOOP_MODE_BMSK;
+ msm_hsl_write(port, mr, UARTDM_MR2_ADDR);
+
+ /* Reset TX */
+ msm_hsl_reset(port);
+
+ /* Turn on Uart Receiver & Transmitter*/
+ msm_hsl_write(port, UARTDM_CR_RX_EN_BMSK
+ | UARTDM_CR_TX_EN_BMSK, UARTDM_CR_ADDR);
+ }
+
+ clk_en(port, 0);
+}
+
+static void msm_hsl_break_ctl(struct uart_port *port, int break_ctl)
+{
+ clk_en(port, 1);
+
+ if (break_ctl)
+ msm_hsl_write(port, START_BREAK, UARTDM_CR_ADDR);
+ else
+ msm_hsl_write(port, STOP_BREAK, UARTDM_CR_ADDR);
+
+ clk_en(port, 0);
+}
+
+static void msm_hsl_set_baud_rate(struct uart_port *port, unsigned int baud)
+{
+ unsigned int baud_code, rxstale, watermark;
+
+ switch (baud) {
+ case 300:
+ baud_code = UARTDM_CSR_300;
+ rxstale = 1;
+ break;
+ case 600:
+ baud_code = UARTDM_CSR_600;
+ rxstale = 1;
+ break;
+ case 1200:
+ baud_code = UARTDM_CSR_1200;
+ rxstale = 1;
+ break;
+ case 2400:
+ baud_code = UARTDM_CSR_2400;
+ rxstale = 1;
+ break;
+ case 4800:
+ baud_code = UARTDM_CSR_4800;
+ rxstale = 1;
+ break;
+ case 9600:
+ baud_code = UARTDM_CSR_9600;
+ rxstale = 2;
+ break;
+ case 14400:
+ baud_code = UARTDM_CSR_14400;
+ rxstale = 3;
+ break;
+ case 19200:
+ baud_code = UARTDM_CSR_19200;
+ rxstale = 4;
+ break;
+ case 28800:
+ baud_code = UARTDM_CSR_28800;
+ rxstale = 6;
+ break;
+ case 38400:
+ baud_code = UARTDM_CSR_38400;
+ rxstale = 8;
+ break;
+ case 57600:
+ baud_code = UARTDM_CSR_57600;
+ rxstale = 16;
+ break;
+ case 115200:
+ default:
+ baud_code = UARTDM_CSR_115200;
+ rxstale = 31;
+ break;
+ }
+
+ msm_hsl_write(port, RESET_RX, UARTDM_CR_ADDR);
+ msm_hsl_write(port, baud_code, UARTDM_CSR_ADDR);
+
+ /* RX stale watermark */
+ watermark = UARTDM_IPR_STALE_LSB_BMSK & rxstale;
+ watermark |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2);
+ msm_hsl_write(port, watermark, UARTDM_IPR_ADDR);
+
+ /* set RX watermark */
+ watermark = (port->fifosize * 3) / 4;
+ msm_hsl_write(port, watermark, UARTDM_RFWR_ADDR);
+
+ /* set TX watermark */
+ msm_hsl_write(port, 0, UARTDM_TFWR_ADDR);
+
+ msm_hsl_write(port, RESET_STALE_INT, UARTDM_CR_ADDR);
+ msm_hsl_write(port, 6500, UARTDM_DMRX_ADDR);
+ msm_hsl_write(port, STALE_EVENT_ENABLE, UARTDM_CR_ADDR);
+}
+
+static void msm_hsl_init_clock(struct uart_port *port)
+{
+ clk_en(port, 1);
+}
+
+static void msm_hsl_deinit_clock(struct uart_port *port)
+{
+ clk_en(port, 0);
+}
+
+static int msm_hsl_startup(struct uart_port *port)
+{
+ struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+ struct platform_device *pdev = to_platform_device(port->dev);
+ const struct msm_serial_hslite_platform_data *pdata =
+ pdev->dev.platform_data;
+ unsigned int data, rfr_level;
+ int ret;
+ unsigned long flags;
+
+ snprintf(msm_hsl_port->name, sizeof(msm_hsl_port->name),
+ "msm_serial_hsl%d", port->line);
+
+ if (!(is_console(port)) || (!port->cons) ||
+ (port->cons && (!(port->cons->flags & CON_ENABLED)))) {
+
+ if (msm_serial_hsl_has_gsbi(port))
+ if ((ioread32(msm_hsl_port->mapped_gsbi +
+ GSBI_CONTROL_ADDR) & GSBI_PROTOCOL_I2C_UART)
+ != GSBI_PROTOCOL_I2C_UART)
+ iowrite32(GSBI_PROTOCOL_I2C_UART,
+ msm_hsl_port->mapped_gsbi +
+ GSBI_CONTROL_ADDR);
+
+ if (pdata && pdata->config_gpio) {
+ ret = gpio_request(pdata->uart_tx_gpio,
+ "UART_TX_GPIO");
+ if (unlikely(ret)) {
+ pr_err("%s: gpio request failed for:%d\n",
+ __func__, pdata->uart_tx_gpio);
+ return ret;
+ }
+
+ ret = gpio_request(pdata->uart_rx_gpio, "UART_RX_GPIO");
+ if (unlikely(ret)) {
+ pr_err("%s: gpio request failed for:%d\n",
+ __func__, pdata->uart_rx_gpio);
+ gpio_free(pdata->uart_tx_gpio);
+ return ret;
+ }
+ }
+ }
+#ifndef CONFIG_PM_RUNTIME
+ msm_hsl_init_clock(port);
+#endif
+ pm_runtime_get_sync(port->dev);
+
+ if (likely(port->fifosize > 12))
+ rfr_level = port->fifosize - 12;
+ else
+ rfr_level = port->fifosize;
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ /* set automatic RFR level */
+ data = msm_hsl_read(port, UARTDM_MR1_ADDR);
+ data &= ~UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK;
+ data &= ~UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK;
+ data |= UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK & (rfr_level << 2);
+ data |= UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK & rfr_level;
+ msm_hsl_write(port, data, UARTDM_MR1_ADDR);
+
+
+ /* Make sure IPR is not 0 to start with*/
+ msm_hsl_write(port, UARTDM_IPR_STALE_LSB_BMSK, UARTDM_IPR_ADDR);
+ data = 0;
+
+ if (!(is_console(port)) || (!port->cons) ||
+ (port->cons && (!(port->cons->flags & CON_ENABLED)))) {
+ msm_hsl_write(port, CR_PROTECTION_EN, UARTDM_CR_ADDR);
+ msm_hsl_write(port, UARTDM_MR2_BITS_PER_CHAR_8 | STOP_BIT_ONE,
+ UARTDM_MR2_ADDR); /* 8N1 */
+ msm_hsl_reset(port);
+ data = UARTDM_CR_TX_EN_BMSK;
+ }
+
+ data |= UARTDM_CR_RX_EN_BMSK;
+
+ msm_hsl_write(port, data, UARTDM_CR_ADDR); /* enable TX & RX */
+
+ /* turn on RX and CTS interrupts */
+ msm_hsl_port->imr = UARTDM_ISR_RXSTALE_BMSK
+ | UARTDM_ISR_DELTA_CTS_BMSK | UARTDM_ISR_RXLEV_BMSK;
+
+ spin_unlock_irqrestore(&port->lock, flags);
+
+ ret = request_irq(port->irq, msm_hsl_irq, IRQF_TRIGGER_HIGH,
+ msm_hsl_port->name, port);
+ if (unlikely(ret)) {
+ printk(KERN_ERR "%s: failed to request_irq\n", __func__);
+ return ret;
+ }
+
+ spin_lock_irqsave(&port->lock, flags);
+ msm_hsl_write(port, RESET_STALE_INT, UARTDM_CR_ADDR);
+ msm_hsl_write(port, 6500, UARTDM_DMRX_ADDR);
+ msm_hsl_write(port, STALE_EVENT_ENABLE, UARTDM_CR_ADDR);
+ msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
+ spin_unlock_irqrestore(&port->lock, flags);
+
+ return 0;
+}
+
+static void msm_hsl_shutdown(struct uart_port *port)
+{
+ struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+ struct platform_device *pdev = to_platform_device(port->dev);
+ const struct msm_serial_hslite_platform_data *pdata =
+ pdev->dev.platform_data;
+
+ clk_en(port, 1);
+
+ msm_hsl_port->imr = 0;
+ msm_hsl_write(port, 0, UARTDM_IMR_ADDR); /* disable interrupts */
+
+ clk_en(port, 0);
+
+ free_irq(port->irq, port);
+
+#ifndef CONFIG_PM_RUNTIME
+ msm_hsl_deinit_clock(port);
+#endif
+ pm_runtime_put_sync(port->dev);
+ if (!(is_console(port)) || (!port->cons) ||
+ (port->cons && (!(port->cons->flags & CON_ENABLED)))) {
+ if (pdata && pdata->config_gpio) {
+ gpio_free(pdata->uart_tx_gpio);
+ gpio_free(pdata->uart_rx_gpio);
+ }
+ }
+}
+
+static void msm_hsl_set_termios(struct uart_port *port,
+ struct ktermios *termios,
+ struct ktermios *old)
+{
+ unsigned long flags;
+ unsigned int baud, mr;
+
+ spin_lock_irqsave(&port->lock, flags);
+ clk_en(port, 1);
+
+ /* calculate and set baud rate */
+ baud = uart_get_baud_rate(port, termios, old, 300, 115200);
+
+ msm_hsl_set_baud_rate(port, baud);
+
+ /* calculate parity */
+ mr = msm_hsl_read(port, UARTDM_MR2_ADDR);
+ mr &= ~UARTDM_MR2_PARITY_MODE_BMSK;
+ if (termios->c_cflag & PARENB) {
+ if (termios->c_cflag & PARODD)
+ mr |= ODD_PARITY;
+ else if (termios->c_cflag & CMSPAR)
+ mr |= SPACE_PARITY;
+ else
+ mr |= EVEN_PARITY;
+ }
+
+ /* calculate bits per char */
+ mr &= ~UARTDM_MR2_BITS_PER_CHAR_BMSK;
+ switch (termios->c_cflag & CSIZE) {
+ case CS5:
+ mr |= FIVE_BPC;
+ break;
+ case CS6:
+ mr |= SIX_BPC;
+ break;
+ case CS7:
+ mr |= SEVEN_BPC;
+ break;
+ case CS8:
+ default:
+ mr |= EIGHT_BPC;
+ break;
+ }
+
+ /* calculate stop bits */
+ mr &= ~(STOP_BIT_ONE | STOP_BIT_TWO);
+ if (termios->c_cflag & CSTOPB)
+ mr |= STOP_BIT_TWO;
+ else
+ mr |= STOP_BIT_ONE;
+
+ /* set parity, bits per char, and stop bit */
+ msm_hsl_write(port, mr, UARTDM_MR2_ADDR);
+
+ /* calculate and set hardware flow control */
+ mr = msm_hsl_read(port, UARTDM_MR1_ADDR);
+ mr &= ~(UARTDM_MR1_CTS_CTL_BMSK | UARTDM_MR1_RX_RDY_CTL_BMSK);
+ if (termios->c_cflag & CRTSCTS) {
+ mr |= UARTDM_MR1_CTS_CTL_BMSK;
+ mr |= UARTDM_MR1_RX_RDY_CTL_BMSK;
+ }
+ msm_hsl_write(port, mr, UARTDM_MR1_ADDR);
+
+ /* Configure status bits to ignore based on termio flags. */
+ port->read_status_mask = 0;
+ if (termios->c_iflag & INPCK)
+ port->read_status_mask |= UARTDM_SR_PAR_FRAME_BMSK;
+ if (termios->c_iflag & (BRKINT | PARMRK))
+ port->read_status_mask |= UARTDM_SR_RX_BREAK_BMSK;
+
+ uart_update_timeout(port, termios->c_cflag, baud);
+
+ clk_en(port, 0);
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *msm_hsl_type(struct uart_port *port)
+{
+ return "MSM";
+}
+
+static void msm_hsl_release_port(struct uart_port *port)
+{
+ struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+ struct platform_device *pdev = to_platform_device(port->dev);
+ struct resource *uart_resource;
+ struct resource *gsbi_resource;
+ resource_size_t size;
+
+ uart_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "uartdm_resource");
+ if (unlikely(!uart_resource))
+ return;
+ size = uart_resource->end - uart_resource->start + 1;
+
+ release_mem_region(port->mapbase, size);
+ iounmap(port->membase);
+ port->membase = NULL;
+
+ if (msm_serial_hsl_has_gsbi(port)) {
+ iowrite32(GSBI_PROTOCOL_IDLE, msm_hsl_port->mapped_gsbi +
+ GSBI_CONTROL_ADDR);
+ gsbi_resource = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM,
+ "gsbi_resource");
+
+ size = gsbi_resource->end - gsbi_resource->start + 1;
+ iounmap(msm_hsl_port->mapped_gsbi);
+ msm_hsl_port->mapped_gsbi = NULL;
+ }
+}
+
+static int msm_hsl_request_port(struct uart_port *port)
+{
+ struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+ struct platform_device *pdev = to_platform_device(port->dev);
+ struct resource *uart_resource;
+ struct resource *gsbi_resource;
+ resource_size_t size;
+
+ uart_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "uartdm_resource");
+ if (unlikely(!uart_resource)) {
+ pr_err("%s: can't get uartdm resource\n", __func__);
+ return -ENXIO;
+ }
+ size = uart_resource->end - uart_resource->start + 1;
+
+ if (unlikely(!request_mem_region(port->mapbase, size,
+ "msm_serial_hsl"))) {
+ pr_err("%s: can't get mem region for uartdm\n", __func__);
+ return -EBUSY;
+ }
+
+ port->membase = ioremap(port->mapbase, size);
+ if (!port->membase) {
+ release_mem_region(port->mapbase, size);
+ return -EBUSY;
+ }
+
+ if (msm_serial_hsl_has_gsbi(port)) {
+ gsbi_resource = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM,
+ "gsbi_resource");
+ if (unlikely(!gsbi_resource)) {
+ pr_err("%s: can't get gsbi resource\n", __func__);
+ return -ENXIO;
+ }
+
+ size = gsbi_resource->end - gsbi_resource->start + 1;
+ msm_hsl_port->mapped_gsbi = ioremap(gsbi_resource->start,
+ size);
+ if (!msm_hsl_port->mapped_gsbi) {
+ return -EBUSY;
+ }
+ }
+
+ return 0;
+}
+
+static void msm_hsl_config_port(struct uart_port *port, int flags)
+{
+ struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+ if (flags & UART_CONFIG_TYPE) {
+ port->type = PORT_MSM;
+ if (msm_hsl_request_port(port))
+ return;
+ }
+ if (msm_serial_hsl_has_gsbi(port))
+ if ((ioread32(msm_hsl_port->mapped_gsbi + GSBI_CONTROL_ADDR) &
+ GSBI_PROTOCOL_I2C_UART) != GSBI_PROTOCOL_I2C_UART)
+ iowrite32(GSBI_PROTOCOL_I2C_UART,
+ msm_hsl_port->mapped_gsbi + GSBI_CONTROL_ADDR);
+}
+
+static int msm_hsl_verify_port(struct uart_port *port,
+ struct serial_struct *ser)
+{
+ if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
+ return -EINVAL;
+ if (unlikely(port->irq != ser->irq))
+ return -EINVAL;
+ return 0;
+}
+
+static void msm_hsl_power(struct uart_port *port, unsigned int state,
+ unsigned int oldstate)
+{
+ int ret;
+ struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+
+ switch (state) {
+ case 0:
+ ret = clk_set_rate(msm_hsl_port->clk, 1843200);
+ if (ret)
+ pr_err("%s(): Error setting UART clock rate\n",
+ __func__);
+ clk_en(port, 1);
+ break;
+ case 3:
+ clk_en(port, 0);
+ break;
+ default:
+ pr_err("%s(): msm_serial_hsl: Unknown PM state %d\n",
+ __func__, state);
+ }
+}
+
+static struct uart_ops msm_hsl_uart_pops = {
+ .tx_empty = msm_hsl_tx_empty,
+ .set_mctrl = msm_hsl_set_mctrl,
+ .get_mctrl = msm_hsl_get_mctrl,
+ .stop_tx = msm_hsl_stop_tx,
+ .start_tx = msm_hsl_start_tx,
+ .stop_rx = msm_hsl_stop_rx,
+ .enable_ms = msm_hsl_enable_ms,
+ .break_ctl = msm_hsl_break_ctl,
+ .startup = msm_hsl_startup,
+ .shutdown = msm_hsl_shutdown,
+ .set_termios = msm_hsl_set_termios,
+ .type = msm_hsl_type,
+ .release_port = msm_hsl_release_port,
+ .request_port = msm_hsl_request_port,
+ .config_port = msm_hsl_config_port,
+ .verify_port = msm_hsl_verify_port,
+ .pm = msm_hsl_power,
+};
+
+static struct msm_hsl_port msm_hsl_uart_ports[] = {
+ {
+ .uart = {
+ .iotype = UPIO_MEM,
+ .ops = &msm_hsl_uart_pops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .fifosize = 64,
+ .line = 0,
+ },
+ },
+ {
+ .uart = {
+ .iotype = UPIO_MEM,
+ .ops = &msm_hsl_uart_pops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .fifosize = 64,
+ .line = 1,
+ },
+ },
+ {
+ .uart = {
+ .iotype = UPIO_MEM,
+ .ops = &msm_hsl_uart_pops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .fifosize = 64,
+ .line = 2,
+ },
+ },
+};
+
+#define UART_NR ARRAY_SIZE(msm_hsl_uart_ports)
+
+static inline struct uart_port *get_port_from_line(unsigned int line)
+{
+ return &msm_hsl_uart_ports[line].uart;
+}
+
+/*
+ * Wait for transmitter & holding register to empty
+ * Derived from wait_for_xmitr in 8250 serial driver by Russell King */
+void wait_for_xmitr(struct uart_port *port, int bits)
+{
+ if (!(msm_hsl_read(port, UARTDM_SR_ADDR) & UARTDM_SR_TXEMT_BMSK)) {
+ while ((msm_hsl_read(port, UARTDM_ISR_ADDR) & bits) != bits) {
+ udelay(1);
+ touch_nmi_watchdog();
+ cpu_relax();
+ }
+ msm_hsl_write(port, CLEAR_TX_READY, UARTDM_CR_ADDR);
+ }
+}
+
+#ifdef CONFIG_SERIAL_MSM_HSL_CONSOLE
+static void msm_hsl_console_putchar(struct uart_port *port, int ch)
+{
+ wait_for_xmitr(port, UARTDM_ISR_TX_READY_BMSK);
+ msm_hsl_write(port, 1, UARTDM_NCF_TX_ADDR);
+
+ while (!(msm_hsl_read(port, UARTDM_SR_ADDR) & UARTDM_SR_TXRDY_BMSK)) {
+ udelay(1);
+ touch_nmi_watchdog();
+ }
+
+ msm_hsl_write(port, ch, UARTDM_TF_ADDR);
+}
+
+static void msm_hsl_console_write(struct console *co, const char *s,
+ unsigned int count)
+{
+ struct uart_port *port;
+ struct msm_hsl_port *msm_hsl_port;
+ int locked;
+
+ BUG_ON(co->index < 0 || co->index >= UART_NR);
+
+ port = get_port_from_line(co->index);
+ msm_hsl_port = UART_TO_MSM(port);
+
+ /* not pretty, but we can end up here via various convoluted paths */
+ if (port->sysrq || oops_in_progress)
+ locked = spin_trylock(&port->lock);
+ else {
+ locked = 1;
+ spin_lock(&port->lock);
+ }
+ msm_hsl_write(port, 0, UARTDM_IMR_ADDR);
+ uart_console_write(port, s, count, msm_hsl_console_putchar);
+ msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
+ if (locked == 1)
+ spin_unlock(&port->lock);
+}
+
+static int __init msm_hsl_console_setup(struct console *co, char *options)
+{
+ struct uart_port *port;
+ int baud, flow, bits, parity;
+ int ret;
+
+ if (unlikely(co->index >= UART_NR || co->index < 0))
+ return -ENXIO;
+
+ port = get_port_from_line(co->index);
+
+ if (unlikely(!port->membase))
+ return -ENXIO;
+
+ port->cons = co;
+
+ pm_runtime_get_noresume(port->dev);
+
+#ifndef CONFIG_PM_RUNTIME
+ msm_hsl_init_clock(port);
+#endif
+ pm_runtime_resume(port->dev);
+
+ if (options)
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+ bits = 8;
+ parity = 'n';
+ flow = 'n';
+ msm_hsl_write(port, UARTDM_MR2_BITS_PER_CHAR_8 | STOP_BIT_ONE,
+ UARTDM_MR2_ADDR); /* 8N1 */
+
+ if (baud < 300 || baud > 115200)
+ baud = 115200;
+ msm_hsl_set_baud_rate(port, baud);
+
+ ret = uart_set_options(port, co, baud, parity, bits, flow);
+ msm_hsl_reset(port);
+ /* Enable transmitter */
+ msm_hsl_write(port, CR_PROTECTION_EN, UARTDM_CR_ADDR);
+ msm_hsl_write(port, UARTDM_CR_TX_EN_BMSK, UARTDM_CR_ADDR);
+
+ printk(KERN_INFO "msm_serial_hsl: console setup on port #%d\n",
+ port->line);
+
+ return ret;
+}
+
+static struct uart_driver msm_hsl_uart_driver;
+
+static struct console msm_hsl_console = {
+ .name = "ttyHSL",
+ .write = msm_hsl_console_write,
+ .device = uart_console_device,
+ .setup = msm_hsl_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &msm_hsl_uart_driver,
+};
+
+#define MSM_HSL_CONSOLE (&msm_hsl_console)
+
+#else
+#define MSM_HSL_CONSOLE NULL
+#endif
+
+static struct uart_driver msm_hsl_uart_driver = {
+ .owner = THIS_MODULE,
+ .driver_name = "msm_serial_hsl",
+ .dev_name = "ttyHSL",
+ .nr = UART_NR,
+ .cons = MSM_HSL_CONSOLE,
+};
+
+static int __devinit msm_serial_hsl_probe(struct platform_device *pdev)
+{
+ struct msm_hsl_port *msm_hsl_port;
+ struct resource *uart_resource;
+ struct resource *gsbi_resource;
+ struct uart_port *port;
+ int ret;
+
+ if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
+ return -ENXIO;
+
+ printk(KERN_INFO "msm_serial_hsl: detected port #%d\n", pdev->id);
+
+ port = get_port_from_line(pdev->id);
+ port->dev = &pdev->dev;
+ msm_hsl_port = UART_TO_MSM(port);
+
+ gsbi_resource = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM,
+ "gsbi_resource");
+ if (gsbi_resource) {
+ msm_hsl_port->is_uartdm = 1;
+ msm_hsl_port->clk = clk_get(&pdev->dev, "gsbi_uart_clk");
+ msm_hsl_port->pclk = clk_get(&pdev->dev, "gsbi_pclk");
+ } else {
+ msm_hsl_port->is_uartdm = 0;
+ msm_hsl_port->clk = clk_get(&pdev->dev, "uartdm_clk");
+ msm_hsl_port->pclk = NULL;
+ }
+
+ if (unlikely(IS_ERR(msm_hsl_port->clk))) {
+ printk(KERN_ERR "%s: Error getting clk\n", __func__);
+ return PTR_ERR(msm_hsl_port->clk);
+ }
+ if (unlikely(IS_ERR(msm_hsl_port->pclk))) {
+ printk(KERN_ERR "%s: Error getting pclk\n", __func__);
+ return PTR_ERR(msm_hsl_port->pclk);
+ }
+
+
+ uart_resource = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM,
+ "uartdm_resource");
+ if (unlikely(!uart_resource)) {
+ printk(KERN_ERR "getting uartdm_resource failed\n");
+ return -ENXIO;
+ }
+ port->mapbase = uart_resource->start;
+
+ port->irq = platform_get_irq(pdev, 0);
+ if (unlikely(port->irq < 0)) {
+ printk(KERN_ERR "%s: getting irq failed\n", __func__);
+ return -ENXIO;
+ }
+
+ device_set_wakeup_capable(&pdev->dev, 1);
+ platform_set_drvdata(pdev, port);
+ pm_runtime_enable(port->dev);
+ ret = uart_add_one_port(&msm_hsl_uart_driver, port);
+
+ return ret;
+}
+
+static int __devexit msm_serial_hsl_remove(struct platform_device *pdev)
+{
+ struct msm_hsl_port *msm_hsl_port = platform_get_drvdata(pdev);
+ struct uart_port *port;
+
+ port = get_port_from_line(pdev->id);
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+
+ device_set_wakeup_capable(&pdev->dev, 0);
+ platform_set_drvdata(pdev, NULL);
+ uart_remove_one_port(&msm_hsl_uart_driver, port);
+
+ clk_put(msm_hsl_port->pclk);
+ clk_put(msm_hsl_port->clk);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int msm_serial_hsl_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct uart_port *port;
+ port = get_port_from_line(pdev->id);
+
+ if (port) {
+ uart_suspend_port(&msm_hsl_uart_driver, port);
+ if (device_may_wakeup(dev))
+ enable_irq_wake(port->irq);
+
+ if (is_console(port))
+ msm_hsl_deinit_clock(port);
+ }
+
+ return 0;
+}
+
+static int msm_serial_hsl_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct uart_port *port;
+ port = get_port_from_line(pdev->id);
+
+ if (port) {
+ if (is_console(port))
+ msm_hsl_init_clock(port);
+ uart_resume_port(&msm_hsl_uart_driver, port);
+
+ if (device_may_wakeup(dev))
+ disable_irq_wake(port->irq);
+ }
+
+ return 0;
+}
+#else
+#define msm_serial_hsl_suspend NULL
+#define msm_serial_hsl_resume NULL
+#endif
+
+static int msm_hsl_runtime_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct uart_port *port;
+ port = get_port_from_line(pdev->id);
+
+ dev_dbg(dev, "pm_runtime: suspending\n");
+ msm_hsl_deinit_clock(port);
+ return 0;
+}
+
+static int msm_hsl_runtime_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct uart_port *port;
+ port = get_port_from_line(pdev->id);
+
+ dev_dbg(dev, "pm_runtime: resuming\n");
+ msm_hsl_init_clock(port);
+ return 0;
+}
+
+static struct dev_pm_ops msm_hsl_dev_pm_ops = {
+ .suspend = msm_serial_hsl_suspend,
+ .resume = msm_serial_hsl_resume,
+ .runtime_suspend = msm_hsl_runtime_suspend,
+ .runtime_resume = msm_hsl_runtime_resume,
+};
+
+static struct platform_driver msm_hsl_platform_driver = {
+ .probe = msm_serial_hsl_probe,
+ .remove = __devexit_p(msm_serial_hsl_remove),
+ .driver = {
+ .name = "msm_serial_hsl",
+ .owner = THIS_MODULE,
+ .pm = &msm_hsl_dev_pm_ops,
+ },
+};
+
+static int __init msm_serial_hsl_init(void)
+{
+ int ret;
+
+ ret = uart_register_driver(&msm_hsl_uart_driver);
+ if (unlikely(ret))
+ return ret;
+
+ ret = platform_driver_register(&msm_hsl_platform_driver);
+ if (unlikely(ret))
+ uart_unregister_driver(&msm_hsl_uart_driver);
+
+ printk(KERN_INFO "msm_serial_hsl: driver initialized\n");
+
+ return ret;
+}
+
+static void __exit msm_serial_hsl_exit(void)
+{
+#ifdef CONFIG_SERIAL_MSM_HSL_CONSOLE
+ unregister_console(&msm_hsl_console);
+#endif
+ platform_driver_unregister(&msm_hsl_platform_driver);
+ uart_unregister_driver(&msm_hsl_uart_driver);
+}
+
+module_init(msm_serial_hsl_init);
+module_exit(msm_serial_hsl_exit);
+
+MODULE_DESCRIPTION("Driver for msm HSUART serial device");
+MODULE_LICENSE("GPL v2");