msm: clock-local: Consolidate definitions of clk_ops
Move clk_ops_rcg and clk_ops_branch into clock-local.c and stop
exporting a handful of local clock functions to arch specific
drivers. Only expose the clk_ops structs.
This cuts down on the lines of code and discourages use of the
clock-local code outside of clock-local.c.
Change-Id: Iba248a4d11714b91e945bb1846a42924d1d4f8db
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 2bfadf6..26ccaa3 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -431,34 +431,6 @@
writel_relaxed(pll_mode, MM_PLL2_MODE_REG);
}
-static struct clk_ops clk_ops_rcg_8x60 = {
- .enable = rcg_clk_enable,
- .disable = rcg_clk_disable,
- .auto_off = rcg_clk_disable,
- .handoff = rcg_clk_handoff,
- .set_rate = rcg_clk_set_rate,
- .list_rate = rcg_clk_list_rate,
- .is_enabled = rcg_clk_is_enabled,
- .round_rate = rcg_clk_round_rate,
- .reset = rcg_clk_reset,
- .get_parent = rcg_clk_get_parent,
- .set_flags = rcg_clk_set_flags,
-};
-
-static struct clk_ops clk_ops_branch = {
- .enable = branch_clk_enable,
- .disable = branch_clk_disable,
- .auto_off = branch_clk_disable,
- .is_enabled = branch_clk_is_enabled,
- .reset = branch_clk_reset,
- .get_parent = branch_clk_get_parent,
- .set_flags = branch_clk_set_flags,
-};
-
-static struct clk_ops clk_ops_reset = {
- .reset = branch_clk_reset,
-};
-
/*
* Clock Descriptions
*/
@@ -965,7 +937,7 @@
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
- .ops = &clk_ops_rcg_8x60, \
+ .ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP1(LOW, 27000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -1010,7 +982,7 @@
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
- .ops = &clk_ops_rcg_8x60, \
+ .ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -1074,7 +1046,7 @@
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
- .ops = &clk_ops_rcg_8x60, \
+ .ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -1142,7 +1114,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "pdm_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(pdm_clk.c),
},
@@ -1185,7 +1157,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "prng_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
@@ -1211,7 +1183,7 @@
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
- .ops = &clk_ops_rcg_8x60, \
+ .ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -1271,7 +1243,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "tsif_ref_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
CLK_INIT(tsif_ref_clk.c),
},
};
@@ -1302,7 +1274,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "tssc_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(tssc_clk.c),
},
@@ -1340,7 +1312,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "usb_hs1_xcvr_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_xcvr_clk.c),
},
@@ -1374,7 +1346,7 @@
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
- .ops = &clk_ops_rcg_8x60, \
+ .ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP1(NOMINAL, 60000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -2001,7 +1973,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "cam_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000),
CLK_INIT(cam_clk.c),
},
@@ -2033,7 +2005,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "csi_src_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 192000000, NOMINAL, 384000000),
CLK_INIT(csi_src_clk.c),
},
@@ -2107,7 +2079,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "dsi_byte_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
CLK_INIT(dsi_byte_clk.c),
},
};
@@ -2188,7 +2160,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "gfx2d0_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
HIGH, 228571000),
CLK_INIT(gfx2d0_clk.c),
@@ -2232,7 +2204,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "gfx2d1_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
HIGH, 228571000),
CLK_INIT(gfx2d1_clk.c),
@@ -2303,7 +2275,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "gfx3d_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 96000000, NOMINAL, 200000000,
HIGH, 320000000),
CLK_INIT(gfx3d_clk.c),
@@ -2355,7 +2327,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "ijpeg_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 228571000),
CLK_INIT(ijpeg_clk.c),
.depends = &ijpeg_axi_clk.c,
@@ -2397,7 +2369,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "jpegd_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(jpegd_clk.c),
.depends = &jpegd_axi_clk.c,
@@ -2468,7 +2440,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mdp_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 85330000, NOMINAL, 200000000,
HIGH, 228571000),
CLK_INIT(mdp_clk.c),
@@ -2503,7 +2475,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mdp_vsync_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(mdp_vsync_clk.c),
},
@@ -2555,7 +2527,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "pixel_mdp_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 85333000, NOMINAL, 170000000),
CLK_INIT(pixel_mdp_clk.c),
},
@@ -2630,7 +2602,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "rot_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 80000000, NOMINAL, 160000000),
CLK_INIT(rot_clk.c),
.depends = &rot_axi_clk.c,
@@ -2682,7 +2654,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "tv_src_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
CLK_INIT(tv_src_clk.c),
},
@@ -2813,7 +2785,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "vcodec_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
HIGH, 228571000),
CLK_INIT(vcodec_clk.c),
@@ -2860,7 +2832,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "vpe_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 76800000, NOMINAL, 160000000,
HIGH, 200000000),
CLK_INIT(vpe_clk.c),
@@ -2919,7 +2891,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "vfe_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 228570000,
HIGH, 266667000),
CLK_INIT(vfe_clk.c),
@@ -3007,7 +2979,7 @@
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
- .ops = &clk_ops_rcg_8x60, \
+ .ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -3099,7 +3071,7 @@
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "pcm_clk",
- .ops = &clk_ops_rcg_8x60,
+ .ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 24580000),
CLK_INIT(pcm_clk.c),
},
@@ -3843,10 +3815,10 @@
/* The halt status bits for PDM and TSSC may be incorrect at boot.
* Toggle these clocks on and off to refresh them. */
- rcg_clk_enable(&pdm_clk.c);
- rcg_clk_disable(&pdm_clk.c);
- rcg_clk_enable(&tssc_clk.c);
- rcg_clk_disable(&tssc_clk.c);
+ clk_prepare_enable(&pdm_clk.c);
+ clk_disable_unprepare(&pdm_clk.c);
+ clk_prepare_enable(&tssc_clk.c);
+ clk_disable_unprepare(&tssc_clk.c);
}
static int __init msm8660_clock_late_init(void)