msm: 8625: Add support for msm8625
Support added for 8625, irqs defined, IO mapping.
Cleanup footswitch devices also done.
Change-Id: I85d40b28d8b4746a2ec83733c01ba4bc9ecc3f09
Signed-off-by: Taniya Das <tdas@codeaurora.org>
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index f08bfb7..32b4a99 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -247,6 +247,14 @@
select MSM_RPM_REGULATOR
select MULTI_IRQ_HANDLER
+config ARCH_MSM8625
+ bool "MSM8625"
+ select ARCH_MSM_CORTEX_A5
+ select CPU_V7
+ select MSM_GPIOMUX
+ select ARM_GIC
+ select ARCH_MSM_CORTEXMP
+ select MULTI_IRQ_HANDLER
endmenu
choice
@@ -296,6 +304,10 @@
select MSM_SMP
bool
+config ARCH_MSM_CORTEXMP
+ select MSM_SMP
+ bool
+
config ARCH_MSM_CORTEX_A5
bool
select HAVE_HW_BRKPT_RESERVED_RW_ACCESS
@@ -305,6 +317,8 @@
select MSM_DALRPC
select MSM_PROC_COMM_REGULATOR
select MULTI_IRQ_HANDLER
+ select ARM_GIC
+ select ARCH_MSM_CORTEXMP
config MSM_VIC
bool
@@ -434,6 +448,14 @@
help
Support for the Qualcomm MSM7627A Reference Design.
+config MACH_MSM8625_RUMI3
+ depends on ARCH_MSM8625
+ depends on !MSM_STACKED_MEMORY
+ default y
+ bool "MSM8625 RUMI3"
+ help
+ Support for the Qualcomm MSM8625 RUMI3 Emulation Platform.
+
config MACH_MSM7X30_SURF
depends on ARCH_MSM7X30
depends on !MSM_STACKED_MEMORY
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 234fb53..168e7f8 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -227,6 +227,8 @@
obj-$(CONFIG_MACH_MSM7X27A_FFA) += board-msm7x27a.o board-msm7627a-storage.o board-msm7627a-bt.o board-msm7627a-camera.o board-msm7627a-display.o
obj-$(CONFIG_MACH_MSM7627A_QRD1) += board-qrd7627a.o board-msm7627a-storage.o board-msm7627a-bt.o board-msm7627a-camera.o board-msm7627a-display.o
obj-$(CONFIG_MACH_MSM7627A_EVB) += board-qrd7627a.o board-msm7627a-storage.o board-msm7627a-bt.o board-msm7627a-camera.o board-msm7627a-display.o
+obj-$(CONFIG_ARCH_MSM8625) += devices-msm7x27a.o
+obj-$(CONFIG_MACH_MSM8625_RUMI3) += board-msm7x27a.o
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o memory_topology.o
obj-$(CONFIG_ARCH_MSM7X30) += clock-local.o clock-7x30.o acpuclock-7x30.o
obj-$(CONFIG_MACH_MSM7X25_SURF) += board-msm7x27.o devices-msm7x25.o
diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot
index bc15a01..7ac2d9f 100644
--- a/arch/arm/mach-msm/Makefile.boot
+++ b/arch/arm/mach-msm/Makefile.boot
@@ -17,6 +17,10 @@
zreladdr-$(CONFIG_ARCH_MSM7X27A) := 0x00208000
params_phys-$(CONFIG_ARCH_MSM7X27A) := 0x00200100
+# MSM8625
+ zreladdr-$(CONFIG_ARCH_MSM8625) := 0x00208000
+params_phys-$(CONFIG_ARCH_MSM8625) := 0x00200100
+
# MSM7x30
zreladdr-$(CONFIG_ARCH_MSM7X30) := 0x00208000
params_phys-$(CONFIG_ARCH_MSM7X30) := 0x00200100
diff --git a/arch/arm/mach-msm/board-msm7x27a.c b/arch/arm/mach-msm/board-msm7x27a.c
index 77db796..8b50c53 100644
--- a/arch/arm/mach-msm/board-msm7x27a.c
+++ b/arch/arm/mach-msm/board-msm7x27a.c
@@ -14,6 +14,7 @@
#include <linux/gpio_event.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>
#include <mach/msm_hsusb.h>
@@ -677,6 +678,11 @@
&msm_gsbi1_qup_i2c_device,
};
+static struct platform_device *msm8625_rumi3_devices[] __initdata = {
+ &msm8625_device_dmov,
+ &msm8625_device_uart1,
+};
+
static struct platform_device *surf_ffa_devices[] __initdata = {
&msm_device_dmov,
&msm_device_smd,
@@ -1052,6 +1058,13 @@
ARRAY_SIZE(rumi_sim_devices));
}
+static void __init msm8625_rumi3_init(void)
+{
+ msm7x2x_misc_init();
+ platform_add_devices(msm8625_rumi3_devices,
+ ARRAY_SIZE(msm8625_rumi3_devices));
+}
+
#define LED_GPIO_PDM 96
#define UART1DM_RX_GPIO 45
@@ -1210,3 +1223,11 @@
.init_early = msm7x2x_init_early,
.handle_irq = vic_handle_irq,
MACHINE_END
+MACHINE_START(MSM8625_RUMI3, "QCT MSM8625 RUMI3")
+ .boot_params = PHYS_OFFSET + 0x100,
+ .map_io = msm8625_map_io,
+ .init_irq = msm8625_init_irq,
+ .init_machine = msm8625_rumi3_init,
+ .timer = &msm_timer,
+ .handle_irq = gic_handle_irq,
+MACHINE_END
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
index 104b2e0..a5751b2 100644
--- a/arch/arm/mach-msm/devices-msm7x27a.c
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -16,12 +16,14 @@
#include <linux/msm_kgsl.h>
#include <linux/regulator/machine.h>
#include <linux/init.h>
+#include <linux/irq.h>
#include <mach/irqs.h>
#include <mach/msm_iomap.h>
#include <mach/board.h>
#include <mach/dma.h>
#include <mach/dal_axi.h>
#include <asm/mach/flash.h>
+#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/mmc.h>
#include <mach/rpc_hsusb.h>
@@ -786,15 +788,60 @@
.num_resources = ARRAY_SIZE(gpio_resources),
};
-static int msm7627a_init_gpio(void)
-{
- platform_device_register(&msm_device_gpio);
- return 0;
-}
-postcore_initcall(msm7627a_init_gpio);
+struct platform_device *msm_footswitch_devices[] = {
+ FS_PCOM(FS_GFX3D, "fs_gfx3d"),
+};
+unsigned msm_num_footswitch_devices = ARRAY_SIZE(msm_footswitch_devices);
+
+/* MSM8625 Devices */
+
+static struct resource msm8625_resources_uart1[] = {
+ {
+ .start = MSM8625_INT_UART1,
+ .end = MSM8625_INT_UART1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = MSM_UART1_PHYS,
+ .end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device msm8625_device_uart1 = {
+ .name = "msm_serial",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(msm8625_resources_uart1),
+ .resource = msm8625_resources_uart1,
+};
+
+static struct resource msm8625_dmov_resource[] = {
+ {
+ .start = MSM8625_INT_ADM_AARM,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 0xA9700000,
+ .end = 0xA9700000 + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device msm8625_device_dmov = {
+ .name = "msm_dmov",
+ .id = -1,
+ .resource = msm8625_dmov_resource,
+ .num_resources = ARRAY_SIZE(msm8625_dmov_resource),
+ .dev = {
+ .platform_data = &msm_dmov_pdata,
+ },
+};
int __init msm7x2x_misc_init(void)
{
+ if (machine_is_msm8625_rumi3())
+ return 0;
+
msm_clock_init(&msm7x27a_clock_init_data);
if (cpu_is_msm7x27aa())
acpuclk_init(&acpuclk_7x27aa_soc_data);
@@ -826,13 +873,37 @@
void __init msm_common_io_init(void)
{
msm_map_common_io();
+ if (socinfo_init() < 0)
+ pr_err("%s: socinfo_init() failed!\n", __func__);
msm7x27x_cache_init();
+}
+
+void __init msm8625_init_irq(void)
+{
+ gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
+ (void *)MSM_QGIC_CPU_BASE);
+
+ /* Edge trigger PPIs
+ */
+ writel_relaxed(0x555555F5, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
+
+ writel_relaxed(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
+ mb();
+}
+
+void __init msm8625_map_io(void)
+{
+ msm_map_msm8625_io();
+
if (socinfo_init() < 0)
pr_err("%s: socinfo_init() failed!\n", __func__);
}
-struct platform_device *msm_footswitch_devices[] = {
- FS_PCOM(FS_GFX3D, "fs_gfx3d"),
-};
-unsigned msm_num_footswitch_devices = ARRAY_SIZE(msm_footswitch_devices);
+static int msm7627a_init_gpio(void)
+{
+ platform_device_register(&msm_device_gpio);
+ return 0;
+}
+postcore_initcall(msm7627a_init_gpio);
+
diff --git a/arch/arm/mach-msm/devices-msm7x2xa.h b/arch/arm/mach-msm/devices-msm7x2xa.h
index a9c87ba..a59ade3 100644
--- a/arch/arm/mach-msm/devices-msm7x2xa.h
+++ b/arch/arm/mach-msm/devices-msm7x2xa.h
@@ -23,4 +23,6 @@
extern struct platform_device msm7x27a_device_csic0;
extern struct platform_device msm7x27a_device_csic1;
extern struct platform_device msm7x27a_device_clkctl;
+void __init msm8625_init_irq(void);
+void __init msm8625_map_io(void);
#endif
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index bbb815e..176d14a 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -41,6 +41,7 @@
extern struct platform_device msm_device_uart1;
extern struct platform_device msm_device_uart2;
extern struct platform_device msm_device_uart3;
+extern struct platform_device msm8625_device_uart1;
extern struct platform_device msm_device_uart_dm1;
extern struct platform_device msm_device_uart_dm2;
@@ -128,6 +129,7 @@
extern struct platform_device msm8960_device_dmov;
extern struct platform_device apq8064_device_dmov;
extern struct platform_device msm9615_device_dmov;
+extern struct platform_device msm8625_device_dmov;
extern struct platform_device msm_device_dmov_adm0;
extern struct platform_device msm_device_dmov_adm1;
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 0eee135..d9bc654 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -448,6 +448,7 @@
void msm_map_msm7x30_io(void);
void msm_map_fsm9xxx_io(void);
void msm_map_copper_io(void);
+void msm_map_msm8625_io(void);
void msm_init_irq(void);
void msm_copper_init_irq(void);
void vic_handle_irq(struct pt_regs *regs);
diff --git a/arch/arm/mach-msm/include/mach/irqs-7xxx.h b/arch/arm/mach-msm/include/mach/irqs-7xxx.h
index 21ae436..c90b4ee 100644
--- a/arch/arm/mach-msm/include/mach/irqs-7xxx.h
+++ b/arch/arm/mach-msm/include/mach/irqs-7xxx.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*/
@@ -79,11 +79,5 @@
#define INT_CE_IRQ (32 + 24)
#endif
-/* 7x00A uses 122, but 7x25 has up to 132. */
-#define NR_GPIO_IRQS 133
-#define NR_MSM_IRQS 64
-#define NR_BOARD_IRQS 64
-#define NR_MSM_GPIOS NR_GPIO_IRQS
-
#define INT_ADSP_A11_SMSM INT_ADSP_A11
#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-8625.h b/arch/arm/mach-msm/include/mach/irqs-8625.h
new file mode 100644
index 0000000..3ff73eb
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8625.h
@@ -0,0 +1,89 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_8625_H
+#define __ASM_ARCH_MSM_IRQS_8625_H
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+/* As per QGIC2 PPI 16 aka 0 is reserved */
+#define MSM8625_INT_A5_PMU_IRQ (GIC_PPI_START + 1)
+#define MSM8625_INT_DEBUG_TIMER_EXP (GIC_PPI_START + 2)
+#define MSM8625_INT_GP_TIMER_EXP (GIC_PPI_START + 3)
+#define MSM8625_INT_COMMRX (GIC_PPI_START + 4)
+#define MSM8625_INT_COMMTX (GIC_PPI_START + 5)
+
+/* rest of the PPI's not used
+ */
+
+#define MSM8625_INT_A9_M2A_0 (GIC_SPI_START + 0)
+#define MSM8625_INT_A9_M2A_1 (GIC_SPI_START + 1)
+#define MSM8625_INT_A9_M2A_2 (GIC_SPI_START + 2)
+#define MSM8625_INT_A9_M2A_3 (GIC_SPI_START + 3)
+#define MSM8625_INT_A9_M2A_4 (GIC_SPI_START + 4)
+#define MSM8625_INT_A9_M2A_5 (GIC_SPI_START + 5)
+#define MSM8625_INT_A9_M2A_6 (GIC_SPI_START + 6)
+#define MSM8625_INT_ACSR_MP_CORE_IPC0 (GIC_SPI_START + 7)
+#define MSM8625_INT_ACSR_MP_CORE_IPC1 (GIC_SPI_START + 8)
+#define MSM8625_INT_UART1 (GIC_SPI_START + 9)
+#define MSM8625_INT_UART2 (GIC_SPI_START + 10)
+#define MSM8625_INT_UART3 (GIC_SPI_START + 11)
+#define MSM8625_INT_UART1_RX (GIC_SPI_START + 12)
+#define MSM8625_INT_UART2_RX (GIC_SPI_START + 13)
+#define MSM8625_INT_UART3_RX (GIC_SPI_START + 14)
+#define MSM8625_INT_USB_OTG (GIC_SPI_START + 15)
+#define MSM8625_INT_DSI_IRQ (GIC_SPI_START + 16)
+#define MSM8625_INT_CSI_IRQ_1 (GIC_SPI_START + 17)
+#define MSM8625_INT_CSI_IRQ_0 (GIC_SPI_START + 18)
+#define MSM8625_INT_MDP (GIC_SPI_START + 19)
+#define MSM8625_INT_GRAPHICS (GIC_SPI_START + 20)
+#define MSM8625_INT_ADM_AARM (GIC_SPI_START + 21)
+#define MSM8625_INT_ADSP_A11 (GIC_SPI_START + 22)
+#define MSM8625_INT_ADSP_A9_A11 (GIC_SPI_START + 23)
+#define MSM8625_INT_SDC1_0 (GIC_SPI_START + 24)
+#define MSM8625_INT_SDC1_1 (GIC_SPI_START + 25)
+#define MSM8625_INT_SDC2_0 (GIC_SPI_START + 26)
+#define MSM8625_INT_SDC2_1 (GIC_SPI_START + 27)
+#define MSM8625_INT_KEYSENSE (GIC_SPI_START + 28)
+#define MSM8625_INT_TCHSCRN_SSBI (GIC_SPI_START + 29)
+#define MSM8625_INT_TCHSCRN1 (GIC_SPI_START + 30)
+#define MSM8625_INT_TCHSCRN2 (GIC_SPI_START + 31)
+
+#define MSM8625_INT_GPIO_GROUP1 (GIC_SPI_START + 32 + 0)
+#define MSM8625_INT_GPIO_GROUP2 (GIC_SPI_START + 32 + 1)
+#define MSM8625_INT_PWB_I2C (GIC_SPI_START + 32 + 2)
+#define MSM8625_INT_SOFTRESET (GIC_SPI_START + 32 + 3)
+#define MSM8625_INT_NAND_WR_ER_DONE (GIC_SPI_START + 32 + 4)
+#define MSM8625_INT_NAND_OP_DONE (GIC_SPI_START + 32 + 5)
+#define MSM8625_INT_PBUS_ARM11 (GIC_SPI_START + 32 + 6)
+#define MSM8625_INT_AXI_MPU_SMI (GIC_SPI_START + 32 + 7)
+#define MSM8625_INT_AXI_MPU_EBI1 (GIC_SPI_START + 32 + 8)
+#define MSM8625_INT_AD_HSSD (GIC_SPI_START + 32 + 9)
+#define MSM8625_INT_NOTUSED (GIC_SPI_START + 32 + 10)
+#define MSM8625_INT_ARM11_DMA (GIC_SPI_START + 32 + 11)
+#define MSM8625_INT_TSIF_IRQ (GIC_SPI_START + 32 + 12)
+#define MSM8625_INT_UART1DM_IRQ (GIC_SPI_START + 32 + 13)
+#define MSM8625_INT_UART1DM_RX (GIC_SPI_START + 32 + 14)
+#define MSM8625_INT_USB_HS (GIC_SPI_START + 32 + 15)
+#define MSM8625_INT_SDC3_0 (GIC_SPI_START + 32 + 16)
+#define MSM8625_INT_SDC3_1 (GIC_SPI_START + 32 + 17)
+#define MSM8625_INT_SDC4_0 (GIC_SPI_START + 32 + 18)
+#define MSM8625_INT_SDC4_1 (GIC_SPI_START + 32 + 19)
+#define MSM8625_INT_UART2DM_IRQ (GIC_SPI_START + 32 + 20)
+#define MSM8625_INT_UART2DM_RX (GIC_SPI_START + 32 + 21)
+#define MSM8625_INT_L2CC_EM (GIC_SPI_START + 32 + 22)
+#define MSM8625_INT_L2CC_INTR (GIC_SPI_START + 32 + 23)
+#define MSM8625_INT_CE_IRQ (GIC_SPI_START + 32 + 24)
+
+#define MSM8625_INT_ADSP_A11_SMSM MSM8625_INT_ADSP_A11
+#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 8c1e4ff..954b673 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2012, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
@@ -19,6 +19,8 @@
#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
+#include "irqs-8625.h"
+
#if defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_APQ8064) || \
defined(CONFIG_ARCH_MSM8930)
@@ -63,6 +65,11 @@
#elif defined(CONFIG_ARCH_MSM7X01A) || defined(CONFIG_ARCH_MSM7X25) \
|| defined(CONFIG_ARCH_MSM7X27)
#include "irqs-7xxx.h"
+
+#define NR_GPIO_IRQS 133
+#define NR_MSM_IRQS 256
+#define NR_BOARD_IRQS 256
+#define NR_MSM_GPIOS NR_GPIO_IRQS
#elif defined(CONFIG_ARCH_FSM9XXX)
#include "irqs-fsm9xxx.h"
#include "sirc.h"
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h b/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h
index d545a5f..ba50a30 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2012, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
@@ -49,8 +49,6 @@
#define MSM_TMR0_BASE MSM_TMR_BASE
-#define MSM_QGIC_DIST_BASE MSM_VIC_BASE
-
#define MSM_GPIO1_BASE IOMEM(0xFA003000)
#define MSM_GPIO1_PHYS 0xA9200000
#define MSM_GPIO1_SIZE SZ_4K
@@ -67,6 +65,30 @@
#define MSM_L2CC_PHYS 0xC0400000
#define MSM_L2CC_SIZE SZ_4K
+#define MSM_QGIC_DIST_BASE IOMEM(0xFA000000)
+#define MSM_QGIC_DIST_PHYS 0xC0000000
+#define MSM_QGIC_DIST_SIZE SZ_4K
+
+#define MSM_QGIC_CPU_BASE IOMEM(0xFA007000)
+#define MSM_QGIC_CPU_PHYS 0xC0002000
+#define MSM_QGIC_CPU_SIZE SZ_256
+
+#define MSM_SCU_BASE IOMEM(0xFA008000)
+#define MSM_SCU_PHYS 0xC0600000
+#define MSM_SCU_SIZE SZ_256
+
+#define MSM_SPM0_BASE IOMEM(0xFA009000)
+#define MSM_SPM0_PHYS 0xC0200000
+#define MSM_SPM0_SIZE SZ_4K
+
+#define MSM_SPM1_BASE IOMEM(0xFA00A000)
+#define MSM_SPM1_PHYS 0xC0700000
+#define MSM_SPM1_SIZE SZ_4K
+
+#define MSM_CFG_CTL_BASE IOMEM(0xFA00B000)
+#define MSM_CFG_CTL_PHYS 0xA9800000
+#define MSM_CFG_CTL_SIZE SZ_4K
+
#define MSM_SHARED_RAM_BASE IOMEM(0xFA100000)
#define MSM_SHARED_RAM_SIZE SZ_1M
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 0f9d707..79c9aed 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -3,7 +3,7 @@
* MSM7K, QSD io support
*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2012, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
@@ -397,6 +397,47 @@
}
#endif /* CONFIG_ARCH_MSM9615 */
+#ifdef CONFIG_ARCH_MSM8625
+static struct map_desc msm8625_io_desc[] __initdata = {
+ MSM_DEVICE(QGIC_DIST),
+ MSM_DEVICE(QGIC_CPU),
+ MSM_DEVICE(TMR),
+ MSM_DEVICE(TMR0),
+ MSM_DEVICE(CSR),
+ MSM_DEVICE(SCU),
+ MSM_DEVICE(CFG_CTL),
+ MSM_DEVICE(GPIO1),
+ MSM_DEVICE(GPIO2),
+ MSM_DEVICE(CLK_CTL),
+ MSM_DEVICE(SPM0),
+ MSM_DEVICE(SPM1),
+#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
+ defined(CONFIG_DEBUG_MSM_UART3)
+ MSM_DEVICE(DEBUG_UART),
+#endif
+#ifdef CONFIG_CACHE_L2X0
+ {
+ .virtual = (unsigned long) MSM_L2CC_BASE,
+ .pfn = __phys_to_pfn(MSM_L2CC_PHYS),
+ .length = MSM_L2CC_SIZE,
+ .type = MT_DEVICE,
+ },
+#endif
+ {
+ .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
+ .length = MSM_SHARED_RAM_SIZE,
+ .type = MT_DEVICE,
+ },
+};
+
+void __init msm_map_msm8625_io(void)
+{
+ msm_map_io(msm8625_io_desc, ARRAY_SIZE(msm8625_io_desc));
+}
+#else
+void __init msm_map_msm8625_io(void) { return; }
+#endif /* CONFIG_ARCH_MSM8625 */
+
void __iomem *
__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
{