microblaze: Fix cache_line_lenght
We used cache_line as cache_line_lenght. For this reason
we did cache flushing 4 times longer than was necessary.
Signed-off-by: Michal Simek <monstr@monstr.eu>
diff --git a/arch/microblaze/kernel/cpu/cpuinfo-static.c b/arch/microblaze/kernel/cpu/cpuinfo-static.c
index adb448f..6558429e 100644
--- a/arch/microblaze/kernel/cpu/cpuinfo-static.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo-static.c
@@ -72,12 +72,12 @@
ci->use_icache = fcpu(cpu, "xlnx,use-icache");
ci->icache_tagbits = fcpu(cpu, "xlnx,addr-tag-bits");
ci->icache_write = fcpu(cpu, "xlnx,allow-icache-wr");
- ci->icache_line = fcpu(cpu, "xlnx,icache-line-len") << 2;
- if (!ci->icache_line) {
+ ci->icache_line_length = fcpu(cpu, "xlnx,icache-line-len") << 2;
+ if (!ci->icache_line_length) {
if (fcpu(cpu, "xlnx,icache-use-fsl"))
- ci->icache_line = 4 << 2;
+ ci->icache_line_length = 4 << 2;
else
- ci->icache_line = 1 << 2;
+ ci->icache_line_length = 1 << 2;
}
ci->icache_size = fcpu(cpu, "i-cache-size");
ci->icache_base = fcpu(cpu, "i-cache-baseaddr");
@@ -86,12 +86,12 @@
ci->use_dcache = fcpu(cpu, "xlnx,use-dcache");
ci->dcache_tagbits = fcpu(cpu, "xlnx,dcache-addr-tag");
ci->dcache_write = fcpu(cpu, "xlnx,allow-dcache-wr");
- ci->dcache_line = fcpu(cpu, "xlnx,dcache-line-len") << 2;
- if (!ci->dcache_line) {
+ ci->dcache_line_length = fcpu(cpu, "xlnx,dcache-line-len") << 2;
+ if (!ci->dcache_line_length) {
if (fcpu(cpu, "xlnx,dcache-use-fsl"))
- ci->dcache_line = 4 << 2;
+ ci->dcache_line_length = 4 << 2;
else
- ci->dcache_line = 1 << 2;
+ ci->dcache_line_length = 1 << 2;
}
ci->dcache_size = fcpu(cpu, "d-cache-size");
ci->dcache_base = fcpu(cpu, "d-cache-baseaddr");