msm: kgsl: Program both IOMMUs at our disposal on 8064
APQ8064 has two AXI ports attached to the GPU with an IOMMU on both.
The VBIF can be programmed to use a round-robin arbitration to access
the ports equally, so we need to program both IOMMUs with the same
pagetable to make sure that the GPU can get where it needs to go.
All this involves a board file infrastructure change that affects 8960
too, but no functional changes are happening for that platform.
Change-Id: Ic0dedbad5198ed9c453711e58a3f1220ef5d5b4e
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
diff --git a/arch/arm/mach-msm/board-8064-gpu.c b/arch/arm/mach-msm/board-8064-gpu.c
index 0357c40..213215e 100644
--- a/arch/arm/mach-msm/board-8064-gpu.c
+++ b/arch/arm/mach-msm/board-8064-gpu.c
@@ -122,6 +122,31 @@
},
};
+static const char *kgsl_3d0_iommu0_ctx_names[] = {
+ "gfx3d_user",
+ /* priv_ctx goes here */
+};
+
+static const char *kgsl_3d0_iommu1_ctx_names[] = {
+ "gfx3d1_user",
+ /* priv_ctx goes here */
+};
+
+static struct kgsl_device_iommu_data kgsl_3d0_iommu_data[] = {
+ {
+ .iommu_ctx_names = kgsl_3d0_iommu0_ctx_names,
+ .iommu_ctx_count = ARRAY_SIZE(kgsl_3d0_iommu0_ctx_names),
+ .physstart = 0x07C00000,
+ .physend = 0x07C00000 + SZ_1M - 1,
+ },
+ {
+ .iommu_ctx_names = kgsl_3d0_iommu1_ctx_names,
+ .iommu_ctx_count = ARRAY_SIZE(kgsl_3d0_iommu1_ctx_names),
+ .physstart = 0x07D00000,
+ .physend = 0x07D00000 + SZ_1M - 1,
+ },
+};
+
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
.pwrlevel = {
{
@@ -154,8 +179,8 @@
#ifdef CONFIG_MSM_BUS_SCALING
.bus_scale_table = &grp3d_bus_scale_pdata,
#endif
- .iommu_user_ctx_name = "gfx3d_user",
- .iommu_priv_ctx_name = NULL,
+ .iommu_data = kgsl_3d0_iommu_data,
+ .iommu_count = ARRAY_SIZE(kgsl_3d0_iommu_data),
};
struct platform_device device_kgsl_3d0 = {
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index 4d4b88f..8ec4633 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -2291,6 +2291,20 @@
},
};
+static const char *kgsl_3d0_iommu_ctx_names[] = {
+ "gfx3d_user",
+ /* priv_ctx goes here */
+};
+
+static struct kgsl_device_iommu_data kgsl_3d0_iommu_data[] = {
+ {
+ .iommu_ctx_names = kgsl_3d0_iommu_ctx_names,
+ .iommu_ctx_count = ARRAY_SIZE(kgsl_3d0_iommu_ctx_names),
+ .physstart = 0x07C00000,
+ .physend = 0x07C00000 + SZ_1M - 1,
+ },
+};
+
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
.pwrlevel = {
{
@@ -2327,8 +2341,8 @@
#ifdef CONFIG_MSM_BUS_SCALING
.bus_scale_table = &grp3d_bus_scale_pdata,
#endif
- .iommu_user_ctx_name = "gfx3d_user",
- .iommu_priv_ctx_name = NULL,
+ .iommu_data = kgsl_3d0_iommu_data,
+ .iommu_count = ARRAY_SIZE(kgsl_3d0_iommu_data),
};
struct platform_device msm_kgsl_3d0 = {
@@ -2356,6 +2370,19 @@
},
};
+static const char *kgsl_2d0_iommu_ctx_names[] = {
+ "gfx2d0_2d0",
+};
+
+static struct kgsl_device_iommu_data kgsl_2d0_iommu_data[] = {
+ {
+ .iommu_ctx_names = kgsl_2d0_iommu_ctx_names,
+ .iommu_ctx_count = ARRAY_SIZE(kgsl_2d0_iommu_ctx_names),
+ .physstart = 0x07D00000,
+ .physend = 0x07D00000 + SZ_1M - 1,
+ },
+};
+
static struct kgsl_device_platform_data kgsl_2d0_pdata = {
.pwrlevel = {
{
@@ -2380,8 +2407,8 @@
#ifdef CONFIG_MSM_BUS_SCALING
.bus_scale_table = &grp2d0_bus_scale_pdata,
#endif
- .iommu_user_ctx_name = "gfx2d0_2d0",
- .iommu_priv_ctx_name = NULL,
+ .iommu_data = kgsl_2d0_iommu_data,
+ .iommu_count = ARRAY_SIZE(kgsl_2d0_iommu_data),
};
struct platform_device msm_kgsl_2d0 = {
@@ -2394,6 +2421,19 @@
},
};
+static const char *kgsl_2d1_iommu_ctx_names[] = {
+ "gfx2d0_2d1",
+};
+
+static struct kgsl_device_iommu_data kgsl_2d1_iommu_data[] = {
+ {
+ .iommu_ctx_names = kgsl_2d1_iommu_ctx_names,
+ .iommu_ctx_count = ARRAY_SIZE(kgsl_2d1_iommu_ctx_names),
+ .physstart = 0x07E00000,
+ .physend = 0x07E00000 + SZ_1M - 1,
+ },
+};
+
static struct resource kgsl_2d1_resources[] = {
{
.name = KGSL_2D1_REG_MEMORY,
@@ -2433,8 +2473,8 @@
#ifdef CONFIG_MSM_BUS_SCALING
.bus_scale_table = &grp2d1_bus_scale_pdata,
#endif
- .iommu_user_ctx_name = "gfx2d1_2d1",
- .iommu_priv_ctx_name = NULL,
+ .iommu_data = kgsl_2d1_iommu_data,
+ .iommu_count = ARRAY_SIZE(kgsl_2d1_iommu_data),
};
struct platform_device msm_kgsl_2d1 = {
diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c
index e4e561c..194067b 100644
--- a/drivers/gpu/msm/kgsl_iommu.c
+++ b/drivers/gpu/msm/kgsl_iommu.c
@@ -24,11 +24,23 @@
#include "kgsl_mmu.h"
#include "kgsl_sharedmem.h"
+/*
+ * On APQ8064, KGSL can control a maximum of 4 IOMMU devices: 2 user and 2
+ * priv domains, 1 each for each of the AXI ports attached to the GPU. 8660
+ * and 8960 have only one AXI port, so maximum allowable IOMMU devices for those
+ * chips is 2.
+ */
+
+#define KGSL_IOMMU_MAX_DEV 4
+
+struct kgsl_iommu_device {
+ struct device *dev;
+ int attached;
+};
+
struct kgsl_iommu {
- struct device *iommu_user_dev;
- int iommu_user_dev_attached;
- struct device *iommu_priv_dev;
- int iommu_priv_dev_attached;
+ struct kgsl_iommu_device dev[KGSL_IOMMU_MAX_DEV];
+ int dev_count;
};
static int kgsl_iommu_pt_equal(struct kgsl_pagetable *pt,
@@ -58,89 +70,101 @@
{
struct iommu_domain *domain;
struct kgsl_iommu *iommu = mmu->priv;
+ int i;
BUG_ON(mmu->hwpagetable == NULL);
BUG_ON(mmu->hwpagetable->priv == NULL);
domain = mmu->hwpagetable->priv;
- if (iommu->iommu_user_dev_attached) {
- iommu_detach_device(domain, iommu->iommu_user_dev);
- iommu->iommu_user_dev_attached = 0;
+ for (i = 0; i < iommu->dev_count; i++) {
+ iommu_detach_device(domain, iommu->dev[i].dev);
+ iommu->dev[i].attached = 0;
KGSL_MEM_INFO(mmu->device,
- "iommu %p detached from user dev of MMU: %p\n",
- domain, mmu);
- }
- if (iommu->iommu_priv_dev_attached) {
- iommu_detach_device(domain, iommu->iommu_priv_dev);
- iommu->iommu_priv_dev_attached = 0;
- KGSL_MEM_INFO(mmu->device,
- "iommu %p detached from priv dev of MMU: %p\n",
- domain, mmu);
+ "iommu %p detached from user dev of MMU: %p\n",
+ domain, mmu);
}
}
static int kgsl_attach_pagetable_iommu_domain(struct kgsl_mmu *mmu)
{
struct iommu_domain *domain;
- int ret = 0;
struct kgsl_iommu *iommu = mmu->priv;
+ int i, ret = 0;
BUG_ON(mmu->hwpagetable == NULL);
BUG_ON(mmu->hwpagetable->priv == NULL);
domain = mmu->hwpagetable->priv;
- if (iommu->iommu_user_dev && !iommu->iommu_user_dev_attached) {
- ret = iommu_attach_device(domain, iommu->iommu_user_dev);
- if (ret) {
- KGSL_MEM_ERR(mmu->device,
- "Failed to attach device, err %d\n", ret);
- goto done;
- }
- iommu->iommu_user_dev_attached = 1;
- KGSL_MEM_INFO(mmu->device,
- "iommu %p attached to user dev of MMU: %p\n",
+ for (i = 0; i < iommu->dev_count; i++) {
+ if (iommu->dev[i].attached == 0) {
+ ret = iommu_attach_device(domain, iommu->dev[i].dev);
+ if (ret) {
+ KGSL_MEM_ERR(mmu->device,
+ "Failed to attach device, err %d\n",
+ ret);
+ goto done;
+ }
+
+ iommu->dev[i].attached = 1;
+ KGSL_MEM_INFO(mmu->device,
+ "iommu %p detached from user dev of MMU: %p\n",
domain, mmu);
- }
- if (iommu->iommu_priv_dev && !iommu->iommu_priv_dev_attached) {
- ret = iommu_attach_device(domain, iommu->iommu_priv_dev);
- if (ret) {
- KGSL_MEM_ERR(mmu->device,
- "Failed to attach device, err %d\n", ret);
- iommu_detach_device(domain, iommu->iommu_user_dev);
- iommu->iommu_user_dev_attached = 0;
- goto done;
}
- iommu->iommu_priv_dev_attached = 1;
- KGSL_MEM_INFO(mmu->device,
- "iommu %p attached to priv dev of MMU: %p\n",
- domain, mmu);
}
+
done:
return ret;
}
+static int _get_iommu_ctxs(struct kgsl_iommu *iommu, struct kgsl_device *device,
+ struct kgsl_device_iommu_data *data)
+{
+ int i;
+
+ for (i = 0; i < data->iommu_ctx_count; i++) {
+ if (iommu->dev_count >= KGSL_IOMMU_MAX_DEV) {
+ KGSL_CORE_ERR("Tried to attach too many IOMMU "
+ "devices\n");
+ return -ENOMEM;
+ }
+
+ if (!data->iommu_ctx_names[i])
+ continue;
+
+ iommu->dev[iommu->dev_count].dev =
+ msm_iommu_get_ctx(data->iommu_ctx_names[i]);
+ if (iommu->dev[iommu->dev_count].dev == NULL) {
+ KGSL_CORE_ERR("Failed to iommu dev handle for "
+ "device %s\n", data->iommu_ctx_names[i]);
+ return -EINVAL;
+ }
+
+ iommu->dev_count++;
+ }
+
+ return 0;
+}
+
static int kgsl_get_iommu_ctxt(struct kgsl_iommu *iommu,
struct kgsl_device *device)
{
- int status = 0;
struct platform_device *pdev =
container_of(device->parentdev, struct platform_device, dev);
struct kgsl_device_platform_data *pdata_dev = pdev->dev.platform_data;
- if (pdata_dev->iommu_user_ctx_name)
- iommu->iommu_user_dev = msm_iommu_get_ctx(
- pdata_dev->iommu_user_ctx_name);
- if (pdata_dev->iommu_priv_ctx_name)
- iommu->iommu_priv_dev = msm_iommu_get_ctx(
- pdata_dev->iommu_priv_ctx_name);
- if (!iommu->iommu_user_dev) {
- KGSL_CORE_ERR("Failed to get user iommu dev handle for "
- "device %s\n",
- pdata_dev->iommu_user_ctx_name);
- status = -EINVAL;
+ int i, ret = 0;
+
+ /* Go through the IOMMU data and attach all the domains */
+
+ for (i = 0; i < pdata_dev->iommu_count; i++) {
+ ret = _get_iommu_ctxs(iommu, device,
+ &pdata_dev->iommu_data[i]);
+ if (ret)
+ break;
}
- return status;
+
+ return ret;
}
static void kgsl_iommu_setstate(struct kgsl_device *device,
@@ -182,8 +206,6 @@
return -ENOMEM;
}
- iommu->iommu_priv_dev_attached = 0;
- iommu->iommu_user_dev_attached = 0;
status = kgsl_get_iommu_ctxt(iommu, device);
if (status) {
kfree(iommu);
diff --git a/include/linux/msm_kgsl.h b/include/linux/msm_kgsl.h
index 37b9d35..5e39f89 100644
--- a/include/linux/msm_kgsl.h
+++ b/include/linux/msm_kgsl.h
@@ -140,6 +140,13 @@
#define KGSL_2D1_REG_MEMORY "kgsl_2d1_reg_memory"
#define KGSL_2D1_IRQ "kgsl_2d1_irq"
+struct kgsl_device_iommu_data {
+ const char **iommu_ctx_names;
+ int iommu_ctx_count;
+ unsigned int physstart;
+ unsigned int physend;
+};
+
struct kgsl_device_platform_data {
struct kgsl_pwrlevel pwrlevel[KGSL_MAX_PWRLEVELS];
int init_level;
@@ -150,8 +157,8 @@
unsigned int clk_map;
unsigned int idle_needed;
struct msm_bus_scale_pdata *bus_scale_table;
- const char *iommu_user_ctx_name;
- const char *iommu_priv_ctx_name;
+ struct kgsl_device_iommu_data *iommu_data;
+ int iommu_count;
};
#endif