ASoC: msm: Migrate audio drivers to new clock apis.
Use the split clock APIs to do low latency actions (enable/disable)
frequently. Use the high latency functions (prepare/unprepare)
sparingly to help performance.
Using these split apis instead of the 2 current APIs, allows the
clock driver to perform the slow steps with a mutex lock held and
removes the need to busy wait for the slow steps to finish.
Change-Id: Ic5b89183e86e788397be50d7b6f1d798c13ff417
Signed-off-by: Asish Bhattacharya <asishb@codeaurora.org>
diff --git a/sound/soc/msm/msm8660.c b/sound/soc/msm/msm8660.c
index 8469507..4cbfd45 100644
--- a/sound/soc/msm/msm8660.c
+++ b/sound/soc/msm/msm8660.c
@@ -170,7 +170,7 @@
/* Master clock OSR 256 */
/* Initially set to Lowest sample rate Needed */
clk_set_rate(rx_osr_clk, 8000 * 256);
- ret = clk_enable(rx_osr_clk);
+ ret = clk_prepare_enable(rx_osr_clk);
if (ret != 0) {
pr_debug("Unable to enable i2s_spkr_osr_clk\n");
clk_put(rx_osr_clk);
@@ -179,16 +179,16 @@
rx_bit_clk = clk_get(NULL, "i2s_spkr_bit_clk");
if (IS_ERR(rx_bit_clk)) {
pr_debug("Failed to get i2s_spkr_bit_clk\n");
- clk_disable(rx_osr_clk);
+ clk_disable_unprepare(rx_osr_clk);
clk_put(rx_osr_clk);
return PTR_ERR(rx_bit_clk);
}
clk_set_rate(rx_bit_clk, 8);
- ret = clk_enable(rx_bit_clk);
+ ret = clk_prepare_enable(rx_bit_clk);
if (ret != 0) {
pr_debug("Unable to enable i2s_spkr_bit_clk\n");
clk_put(rx_bit_clk);
- clk_disable(rx_osr_clk);
+ clk_disable_unprepare(rx_osr_clk);
clk_put(rx_osr_clk);
return ret;
}
@@ -203,7 +203,7 @@
}
/* Master clock OSR 256 */
clk_set_rate(tx_osr_clk, 8000 * 256);
- ret = clk_enable(tx_osr_clk);
+ ret = clk_prepare_enable(tx_osr_clk);
if (ret != 0) {
pr_debug("Unable to enable i2s_mic_osr_clk\n");
clk_put(tx_osr_clk);
@@ -212,16 +212,16 @@
tx_bit_clk = clk_get(NULL, "i2s_mic_bit_clk");
if (IS_ERR(tx_bit_clk)) {
pr_debug("Failed to get i2s_mic_bit_clk\n");
- clk_disable(tx_osr_clk);
+ clk_disable_unprepare(tx_osr_clk);
clk_put(tx_osr_clk);
return PTR_ERR(tx_bit_clk);
}
clk_set_rate(tx_bit_clk, 8);
- ret = clk_enable(tx_bit_clk);
+ ret = clk_prepare_enable(tx_bit_clk);
if (ret != 0) {
pr_debug("Unable to enable i2s_mic_bit_clk\n");
clk_put(tx_bit_clk);
- clk_disable(tx_osr_clk);
+ clk_disable_unprepare(tx_osr_clk);
clk_put(tx_osr_clk);
return ret;
}
@@ -243,12 +243,12 @@
timpani_poweramp_off();
msleep(30);
if (rx_bit_clk) {
- clk_disable(rx_bit_clk);
+ clk_disable_unprepare(rx_bit_clk);
clk_put(rx_bit_clk);
rx_bit_clk = NULL;
}
if (rx_osr_clk) {
- clk_disable(rx_osr_clk);
+ clk_disable_unprepare(rx_osr_clk);
clk_put(rx_osr_clk);
rx_osr_clk = NULL;
}
@@ -257,12 +257,12 @@
msm_snddev_disable_dmic_power();
msleep(30);
if (tx_bit_clk) {
- clk_disable(tx_bit_clk);
+ clk_disable_unprepare(tx_bit_clk);
clk_put(tx_bit_clk);
tx_bit_clk = NULL;
}
if (tx_osr_clk) {
- clk_disable(tx_osr_clk);
+ clk_disable_unprepare(tx_osr_clk);
clk_put(tx_osr_clk);
tx_osr_clk = NULL;
}