arm/tegra: pinmux: ioremap registers
Use ioremap to obtain access to registers instead of using static
mappings. This reduces the number of users of the static mappings, which
will eventually allow them to be removed.
Note that on Tegra30, the number of register "banks" will decrease to 2,
and the packing of specific bits into registers will change significantly.
That's why this change adds the "*_bank" fields to the pingroup tables,
rather than implementing some more hard-coded scheme.
Also, completely remove the implementation of suspend/resume; Tegra doesn't
yet support suspend/resume, and the implementation is complex for the
general pinmux driver:
* Not all registers are used within each bank, so we probably shouldn't
just iterate over every register in the bank, and save/restore it,
since that would mean touching undefined registers.
* Registers are shared between pingroups, so we can't simply iterate over
each pingroup, and save/restore the registers it uses.
It'd probably be best have probe() calculate a bitmask of actually-used
registers for each bank, and have suspend/resume iterate over those
bitmaps.
Oh, and Real Soon Now, I should be looking into converting this driver to
the new pinmux/pinctrl subsystem, so I didn't want to put too much work
into the current incarnation.
v2: s/space/bank/ to match comments on reg_* fields in pinmux.h.
Re-order bank/reg parameters to pg_readl/pg_writel.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
index fb21217..1d20165 100644
--- a/arch/arm/mach-tegra/pinmux.c
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -170,15 +170,17 @@
}
}
+static int nbanks;
+static void __iomem **regs;
-static inline unsigned long pg_readl(unsigned long offset)
+static inline u32 pg_readl(u32 bank, u32 reg)
{
- return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
+ return readl(regs[bank] + reg);
}
-static inline void pg_writel(unsigned long value, unsigned long offset)
+static inline void pg_writel(u32 val, u32 bank, u32 reg)
{
- writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
+ writel(val, regs[bank] + reg);
}
static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
@@ -218,10 +220,10 @@
spin_lock_irqsave(&mux_lock, flags);
- reg = pg_readl(pingroups[pg].mux_reg);
+ reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
reg &= ~(0x3 << pingroups[pg].mux_bit);
reg |= mux << pingroups[pg].mux_bit;
- pg_writel(reg, pingroups[pg].mux_reg);
+ pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
spin_unlock_irqrestore(&mux_lock, flags);
@@ -242,11 +244,11 @@
spin_lock_irqsave(&mux_lock, flags);
- reg = pg_readl(pingroups[pg].tri_reg);
+ reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
reg &= ~(0x1 << pingroups[pg].tri_bit);
if (tristate)
reg |= 1 << pingroups[pg].tri_bit;
- pg_writel(reg, pingroups[pg].tri_reg);
+ pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
spin_unlock_irqrestore(&mux_lock, flags);
@@ -273,10 +275,10 @@
spin_lock_irqsave(&mux_lock, flags);
- reg = pg_readl(pingroups[pg].pupd_reg);
+ reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
reg &= ~(0x3 << pingroups[pg].pupd_bit);
reg |= pupd << pingroups[pg].pupd_bit;
- pg_writel(reg, pingroups[pg].pupd_reg);
+ pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
spin_unlock_irqrestore(&mux_lock, flags);
@@ -363,12 +365,12 @@
spin_lock_irqsave(&mux_lock, flags);
- reg = pg_readl(drive_pingroups[pg].reg);
+ reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
if (hsm == TEGRA_HSM_ENABLE)
reg |= (1 << 2);
else
reg &= ~(1 << 2);
- pg_writel(reg, drive_pingroups[pg].reg);
+ pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
spin_unlock_irqrestore(&mux_lock, flags);
@@ -388,12 +390,12 @@
spin_lock_irqsave(&mux_lock, flags);
- reg = pg_readl(drive_pingroups[pg].reg);
+ reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
if (schmitt == TEGRA_SCHMITT_ENABLE)
reg |= (1 << 3);
else
reg &= ~(1 << 3);
- pg_writel(reg, drive_pingroups[pg].reg);
+ pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
spin_unlock_irqrestore(&mux_lock, flags);
@@ -413,10 +415,10 @@
spin_lock_irqsave(&mux_lock, flags);
- reg = pg_readl(drive_pingroups[pg].reg);
+ reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
reg &= ~(0x3 << 4);
reg |= drive << 4;
- pg_writel(reg, drive_pingroups[pg].reg);
+ pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
spin_unlock_irqrestore(&mux_lock, flags);
@@ -436,10 +438,10 @@
spin_lock_irqsave(&mux_lock, flags);
- reg = pg_readl(drive_pingroups[pg].reg);
+ reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
reg &= ~(0x1f << 12);
reg |= pull_down << 12;
- pg_writel(reg, drive_pingroups[pg].reg);
+ pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
spin_unlock_irqrestore(&mux_lock, flags);
@@ -459,10 +461,10 @@
spin_lock_irqsave(&mux_lock, flags);
- reg = pg_readl(drive_pingroups[pg].reg);
+ reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
reg &= ~(0x1f << 12);
reg |= pull_up << 12;
- pg_writel(reg, drive_pingroups[pg].reg);
+ pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
spin_unlock_irqrestore(&mux_lock, flags);
@@ -482,10 +484,10 @@
spin_lock_irqsave(&mux_lock, flags);
- reg = pg_readl(drive_pingroups[pg].reg);
+ reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
reg &= ~(0x3 << 28);
reg |= slew_rising << 28;
- pg_writel(reg, drive_pingroups[pg].reg);
+ pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
spin_unlock_irqrestore(&mux_lock, flags);
@@ -505,10 +507,10 @@
spin_lock_irqsave(&mux_lock, flags);
- reg = pg_readl(drive_pingroups[pg].reg);
+ reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
reg &= ~(0x3 << 30);
reg |= slew_falling << 30;
- pg_writel(reg, drive_pingroups[pg].reg);
+ pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
spin_unlock_irqrestore(&mux_lock, flags);
@@ -668,6 +670,74 @@
static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
{
+ struct resource *res;
+ int i;
+ int config_bad = 0;
+
+ for (i = 0; ; i++) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+ if (!res)
+ break;
+ }
+ nbanks = i;
+
+ for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
+ if (pingroups[i].tri_bank >= nbanks) {
+ dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
+ config_bad = 1;
+ }
+
+ if (pingroups[i].mux_bank >= nbanks) {
+ dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
+ config_bad = 1;
+ }
+
+ if (pingroups[i].pupd_bank >= nbanks) {
+ dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
+ config_bad = 1;
+ }
+ }
+
+ for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
+ if (drive_pingroups[i].reg_bank >= nbanks) {
+ dev_err(&pdev->dev,
+ "drive pingroup %d: bad reg_bank\n", i);
+ config_bad = 1;
+ }
+ }
+
+ if (config_bad)
+ return -ENODEV;
+
+ regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
+ if (!regs) {
+ dev_err(&pdev->dev, "Can't alloc regs pointer\n");
+ return -ENODEV;
+ }
+
+ for (i = 0; i < nbanks; i++) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+ if (!res) {
+ dev_err(&pdev->dev, "Missing MEM resource\n");
+ return -ENODEV;
+ }
+
+ if (!devm_request_mem_region(&pdev->dev, res->start,
+ resource_size(res),
+ dev_name(&pdev->dev))) {
+ dev_err(&pdev->dev,
+ "Couldn't request MEM resource %d\n", i);
+ return -ENODEV;
+ }
+
+ regs[i] = devm_ioremap(&pdev->dev, res->start,
+ resource_size(res));
+ if (!regs) {
+ dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
+ return -ENODEV;
+ }
+ }
+
return 0;
}
@@ -710,6 +780,7 @@
int len;
for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
+ unsigned long reg;
unsigned long tri;
unsigned long mux;
unsigned long pupd;
@@ -722,8 +793,9 @@
seq_printf(s, "TEGRA_MUX_NONE");
len = strlen("NONE");
} else {
- mux = (pg_readl(pingroups[i].mux_reg) >>
- pingroups[i].mux_bit) & 0x3;
+ reg = pg_readl(pingroups[i].mux_bank,
+ pingroups[i].mux_reg);
+ mux = (reg >> pingroups[i].mux_bit) & 0x3;
if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
len = 5;
@@ -739,8 +811,9 @@
seq_printf(s, "TEGRA_PUPD_NORMAL");
len = strlen("NORMAL");
} else {
- pupd = (pg_readl(pingroups[i].pupd_reg) >>
- pingroups[i].pupd_bit) & 0x3;
+ reg = pg_readl(pingroups[i].pupd_bank,
+ pingroups[i].pupd_reg);
+ pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
len = strlen(pupd_name(pupd));
}
@@ -749,8 +822,9 @@
if (pingroups[i].tri_reg < 0) {
seq_printf(s, "TEGRA_TRI_NORMAL");
} else {
- tri = (pg_readl(pingroups[i].tri_reg) >>
- pingroups[i].tri_bit) & 0x1;
+ reg = pg_readl(pingroups[i].tri_bank,
+ pingroups[i].tri_reg);
+ tri = (reg >> pingroups[i].tri_bit) & 0x1;
seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
}
@@ -785,7 +859,8 @@
dbg_pad_field(s, 7 - len);
- reg = pg_readl(drive_pingroups[i].reg);
+ reg = pg_readl(drive_pingroups[i].reg_bank,
+ drive_pingroups[i].reg);
if (HSM_EN(reg)) {
seq_printf(s, "TEGRA_HSM_ENABLE");
len = 16;