)]}'
{
  "commit": "4bb0d3ec3e5b1e9e2399cdc641b3b6521ac9cdaa",
  "tree": "5e8d7646f5c6a2cec990b6d591f230d496b20664",
  "parents": [
    "2a0694d15d55d0deed928786a6393d5e45e37d76"
  ],
  "author": {
    "name": "Zachary Amsden",
    "email": "zach@vmware.com",
    "time": "Sat Sep 03 15:56:36 2005 -0700"
  },
  "committer": {
    "name": "Linus Torvalds",
    "email": "torvalds@evo.osdl.org",
    "time": "Mon Sep 05 00:06:11 2005 -0700"
  },
  "message": "[PATCH] i386: inline asm cleanup\n\ni386 Inline asm cleanup.  Use cr/dr accessor functions.\n\nAlso, a potential bugfix.  Also, some CR accessors really should be volatile.\nReads from CR0 (numeric state may change in an exception handler), writes to\nCR4 (flipping CR4.TSD) and reads from CR2 (page fault) prevent instruction\nre-ordering.  I did not add memory clobber to CR3 / CR4 / CR0 updates, as it\nwas not there to begin with, and in no case should kernel memory be clobbered,\nexcept when doing a TLB flush, which already has memory clobber.\n\nI noticed that page invalidation does not have a memory clobber.  I can\u0027t find\na bug as a result, but there is definitely a potential for a bug here:\n\n#define __flush_tlb_single(addr) \\\n\t__asm__ __volatile__(\"invlpg %0\": :\"m\" (*(char *) addr))\n\nSigned-off-by: Zachary Amsden \u003czach@vmware.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n",
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