msm: krait-l2-accessor: Add missing barriers
The Krait processor requires a barrier to be executed
between writing to L2CPUCPSELR and accessing L2CPUCPDR, to
ensure that the write to L2CPUCPSELR is reflected in the
access to L2CPUCPDR.
Change-Id: Ifda47c189721237786e5f3fefb8506bbd830d365
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
diff --git a/arch/arm/mach-msm/msm-krait-l2-accessors.c b/arch/arm/mach-msm/msm-krait-l2-accessors.c
index b03e2d2..3d341e3 100644
--- a/arch/arm/mach-msm/msm-krait-l2-accessors.c
+++ b/arch/arm/mach-msm/msm-krait-l2-accessors.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -29,14 +29,13 @@
mb();
asm volatile ("mcr p15, 3, %[l2cpselr], c15, c0, 6\n\t"
+ "isb\n\t"
"mcr p15, 3, %[l2cpdr], c15, c0, 7\n\t"
- :
+ "isb\n\t"
+ "mrc p15, 3, %[l2cpdr_read], c15, c0, 7\n\t"
+ : [l2cpdr_read]"=r" (ret_val)
: [l2cpselr]"r" (reg_addr), [l2cpdr]"r" (val)
);
- isb();
- /* Ensure the value took */
- asm volatile ("mrc p15, 3, %0, c15, c0, 7" : "=r" (ret_val));
-
raw_spin_unlock_irqrestore(&l2_access_lock, flags);
return ret_val;
@@ -53,11 +52,12 @@
raw_spin_lock_irqsave(&l2_access_lock, flags);
mb();
asm volatile ("mcr p15, 3, %[l2cpselr], c15, c0, 6\n\t"
+ "isb\n\t"
"mcr p15, 3, %[l2cpdr], c15, c0, 7\n\t"
+ "isb\n\t"
:
: [l2cpselr]"r" (reg_addr), [l2cpdr]"r" (val)
);
- isb();
raw_spin_unlock_irqrestore(&l2_access_lock, flags);
}
EXPORT_SYMBOL(set_l2_indirect_reg);
@@ -72,6 +72,7 @@
raw_spin_lock_irqsave(&l2_access_lock, flags);
asm volatile ("mcr p15, 3, %[l2cpselr], c15, c0, 6\n\t"
+ "isb\n\t"
"mrc p15, 3, %[l2cpdr], c15, c0, 7\n\t"
: [l2cpdr]"=r" (val)
: [l2cpselr]"r" (reg_addr)