)]}'
{
  "commit": "4f40bf46897ddb57f149c0758f0cef0cc7782f7f",
  "tree": "98a0e6000bf92f26b0a2f75afbe8daf8f6f602d5",
  "parents": [
    "59e4220a1112bf65924bc2e47b5757911b6f349b"
  ],
  "author": {
    "name": "akeemting",
    "email": "akeem@jmicron.com",
    "time": "Wed Dec 03 21:19:16 2008 -0800"
  },
  "committer": {
    "name": "David S. Miller",
    "email": "davem@davemloft.net",
    "time": "Wed Dec 03 21:19:16 2008 -0800"
  },
  "message": "jme: GHC register control fix for new hardware\n\nDue to the hardware design, except the first chip on the market,\nother chips needs to setup the clock source for MAC processor\nimplicitly through Global Host Control Register(GHC).\n(Strange design huh?)\n\n10/100M uses the PCI-E as clock source, and 1G uses GPHY.\n\nAnd I reordered the code a little, to make it easier to read.\n\nFound-by: \"Ethan\" \u003cethanhsiao@jmicron.com\u003e\nFixed-by: \"akeemting\" \u003cakeem@jmicron.com\u003e\nSigned-off-by: \"Guo-Fu Tseng\" \u003ccooldavid@cooldavid.org\u003e\nAcked-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c3873879003b80004125183c7d2951abb7f81ccc",
      "old_mode": 33188,
      "old_path": "drivers/net/jme.c",
      "new_id": "e10d9f38662c6fce4e35c5e658bff0c8dbd98608",
      "new_mode": 33188,
      "new_path": "drivers/net/jme.c"
    },
    {
      "type": "modify",
      "old_id": "f863aee6648b49b0db38d2cdc077640669a2a424",
      "old_mode": 33188,
      "old_path": "drivers/net/jme.h",
      "new_id": "adaf3ddbf7835387bf6bca79f024d65919739ccb",
      "new_mode": 33188,
      "new_path": "drivers/net/jme.h"
    }
  ]
}