msm: acpuclock-7201: Add support for PLL4@1209Mhz for 8625
In 8625 PLL4 will be running @ 1.2GHz. So we need to add
new acpuclock table which is having new configuration for
the PLLs.
The hardware design requires CPU frequencies >= 800MHz to be
sourced from PLL4 for best reliability, so it is used instead
of PLL2(which runs at similar rate).
Change-Id: Ia76615d3cce3201eeba0bb60cb5681344d2e40a2
Signed-off-by: Pankaj Kumar <pakuma@codeaurora.org>
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
index 903694e..f7e67cb 100644
--- a/arch/arm/mach-msm/devices-msm7x27a.c
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -1532,6 +1532,36 @@
.size = ARRAY_SIZE(msm_clock_8625_dummy),
};
+enum {
+ MSM8625,
+ MSM8625A,
+};
+
+static int __init msm8625_cpu_id(void)
+{
+ int raw_id, cpu;
+
+ raw_id = socinfo_get_raw_id();
+ switch (raw_id) {
+ /* Part number for 1GHz part */
+ case 0x770:
+ case 0x771:
+ case 0x780:
+ cpu = MSM8625;
+ break;
+ /* Part number for 1.2GHz part */
+ case 0x773:
+ case 0x774:
+ case 0x781:
+ cpu = MSM8625A;
+ break;
+ default:
+ pr_err("Invalid Raw ID\n");
+ return -ENODEV;
+ }
+ return cpu;
+}
+
int __init msm7x2x_misc_init(void)
{
if (machine_is_msm8625_rumi3()) {
@@ -1540,10 +1570,16 @@
}
msm_clock_init(&msm7x27a_clock_init_data);
- if (cpu_is_msm7x27aa() || cpu_is_msm8625())
+ if (cpu_is_msm7x27aa())
acpuclk_init(&acpuclk_7x27aa_soc_data);
- else
+ else if (cpu_is_msm8625()) {
+ if (msm8625_cpu_id() == MSM8625)
+ acpuclk_init(&acpuclk_7x27aa_soc_data);
+ else if (msm8625_cpu_id() == MSM8625A)
+ acpuclk_init(&acpuclk_8625_soc_data);
+ } else {
acpuclk_init(&acpuclk_7x27a_soc_data);
+ }
return 0;