msm: clock: Use device names to distinguish between USB clocks
Drivers should now use their device names to distinguish between
clocks of the same type rather than the clock name. Clock names
are updated to match the new naming convention.
CRs-Fixed: 327559
Change-Id: I78757806589e037a0655a63e7ee20c935214c99d
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
diff --git a/drivers/usb/host/ehci-msm-hsic.c b/drivers/usb/host/ehci-msm-hsic.c
index eb0b203..af7f2cf 100644
--- a/drivers/usb/host/ehci-msm-hsic.c
+++ b/drivers/usb/host/ehci-msm-hsic.c
@@ -1,6 +1,6 @@
/* ehci-msm-hsic.c - HSUSB Host Controller Driver Implementation
*
- * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* Partly derived from ehci-fsl.c and ehci-hcd.c
* Copyright (c) 2000-2004 by David Brownell
@@ -43,9 +43,9 @@
struct ehci_hcd ehci;
struct device *dev;
struct clk *ahb_clk;
- struct clk *sys_clk;
- struct clk *fs_xcvr_clk;
- struct clk *hsic_clk;
+ struct clk *core_clk;
+ struct clk *alt_core_clk;
+ struct clk *phy_clk;
struct clk *cal_clk;
struct regulator *hsic_vddcx;
bool async_int;
@@ -270,18 +270,18 @@
{
int ret;
- clk_enable(mehci->fs_xcvr_clk);
+ clk_enable(mehci->alt_core_clk);
- ret = clk_reset(mehci->sys_clk, CLK_RESET_ASSERT);
+ ret = clk_reset(mehci->core_clk, CLK_RESET_ASSERT);
if (ret) {
- clk_disable(mehci->fs_xcvr_clk);
+ clk_disable(mehci->alt_core_clk);
dev_err(mehci->dev, "usb phy clk assert failed\n");
return ret;
}
usleep_range(10000, 12000);
- clk_disable(mehci->fs_xcvr_clk);
+ clk_disable(mehci->alt_core_clk);
- ret = clk_reset(mehci->sys_clk, CLK_RESET_DEASSERT);
+ ret = clk_reset(mehci->core_clk, CLK_RESET_DEASSERT);
if (ret)
dev_err(mehci->dev, "usb phy clk deassert failed\n");
@@ -423,8 +423,8 @@
*/
mb();
- clk_disable(mehci->sys_clk);
- clk_disable(mehci->hsic_clk);
+ clk_disable(mehci->core_clk);
+ clk_disable(mehci->phy_clk);
clk_disable(mehci->cal_clk);
clk_disable(mehci->ahb_clk);
pdata = mehci->dev->platform_data;
@@ -477,8 +477,8 @@
pr_err("%s failed to vote for"
"TCXO D1 buffer%d\n", __func__, ret);
}
- clk_enable(mehci->sys_clk);
- clk_enable(mehci->hsic_clk);
+ clk_enable(mehci->core_clk);
+ clk_enable(mehci->phy_clk);
clk_enable(mehci->cal_clk);
clk_enable(mehci->ahb_clk);
@@ -634,71 +634,71 @@
if (!init)
goto put_clocks;
- /*sys_clk is required for LINK protocol engine,it should be at 60MHz */
- mehci->sys_clk = clk_get(mehci->dev, "usb_hsic_system_clk");
- if (IS_ERR(mehci->sys_clk)) {
- dev_err(mehci->dev, "failed to get hsic_sys_clk\n");
- ret = PTR_ERR(mehci->sys_clk);
+ /*core_clk is required for LINK protocol engine,it should be at 60MHz */
+ mehci->core_clk = clk_get(mehci->dev, "core_clk");
+ if (IS_ERR(mehci->core_clk)) {
+ dev_err(mehci->dev, "failed to get core_clk\n");
+ ret = PTR_ERR(mehci->core_clk);
return ret;
}
- clk_set_rate(mehci->sys_clk, 60000000);
+ clk_set_rate(mehci->core_clk, 60000000);
- /* 60MHz fs_xcvr_clk is for LINK to be used during PHY RESET */
- mehci->fs_xcvr_clk = clk_get(mehci->dev, "usb_hsic_xcvr_fs_clk");
- if (IS_ERR(mehci->fs_xcvr_clk)) {
- dev_err(mehci->dev, "failed to get fs_xcvr_clk\n");
- ret = PTR_ERR(mehci->fs_xcvr_clk);
- goto put_sys_clk;
+ /* 60MHz alt_core_clk is for LINK to be used during PHY RESET */
+ mehci->alt_core_clk = clk_get(mehci->dev, "alt_core_clk");
+ if (IS_ERR(mehci->alt_core_clk)) {
+ dev_err(mehci->dev, "failed to core_clk\n");
+ ret = PTR_ERR(mehci->alt_core_clk);
+ goto put_core_clk;
}
- clk_set_rate(mehci->fs_xcvr_clk, 60000000);
+ clk_set_rate(mehci->alt_core_clk, 60000000);
- /* 480MHz hsic_clk is required for HSIC PHY operation */
- mehci->hsic_clk = clk_get(mehci->dev, "usb_hsic_hsic_clk");
- if (IS_ERR(mehci->hsic_clk)) {
- dev_err(mehci->dev, "failed to get hsic_clk\n");
- ret = PTR_ERR(mehci->hsic_clk);
- goto put_fs_xcvr_clk;
+ /* 480MHz phy_clk is required for HSIC PHY operation */
+ mehci->phy_clk = clk_get(mehci->dev, "phy_clk");
+ if (IS_ERR(mehci->phy_clk)) {
+ dev_err(mehci->dev, "failed to get phy_clk\n");
+ ret = PTR_ERR(mehci->phy_clk);
+ goto put_alt_core_clk;
}
- clk_set_rate(mehci->hsic_clk, 480000000);
+ clk_set_rate(mehci->phy_clk, 480000000);
/* 10MHz cal_clk is required for calibration of I/O pads */
- mehci->cal_clk = clk_get(mehci->dev, "usb_hsic_hsio_cal_clk");
+ mehci->cal_clk = clk_get(mehci->dev, "cal_clk");
if (IS_ERR(mehci->cal_clk)) {
- dev_err(mehci->dev, "failed to get hsic_cal_clk\n");
+ dev_err(mehci->dev, "failed to get cal_clk\n");
ret = PTR_ERR(mehci->cal_clk);
- goto put_hsic_clk;
+ goto put_phy_clk;
}
clk_set_rate(mehci->cal_clk, 10000000);
/* ahb_clk is required for data transfers */
- mehci->ahb_clk = clk_get(mehci->dev, "usb_hsic_p_clk");
+ mehci->ahb_clk = clk_get(mehci->dev, "iface_clk");
if (IS_ERR(mehci->ahb_clk)) {
- dev_err(mehci->dev, "failed to get hsic_ahb_clk\n");
+ dev_err(mehci->dev, "failed to get iface_clk\n");
ret = PTR_ERR(mehci->ahb_clk);
goto put_cal_clk;
}
- clk_enable(mehci->sys_clk);
- clk_enable(mehci->hsic_clk);
+ clk_enable(mehci->core_clk);
+ clk_enable(mehci->phy_clk);
clk_enable(mehci->cal_clk);
clk_enable(mehci->ahb_clk);
return 0;
put_clocks:
- clk_disable(mehci->sys_clk);
- clk_disable(mehci->hsic_clk);
+ clk_disable(mehci->core_clk);
+ clk_disable(mehci->phy_clk);
clk_disable(mehci->cal_clk);
clk_disable(mehci->ahb_clk);
clk_put(mehci->ahb_clk);
put_cal_clk:
clk_put(mehci->cal_clk);
-put_hsic_clk:
- clk_put(mehci->hsic_clk);
-put_fs_xcvr_clk:
- clk_put(mehci->fs_xcvr_clk);
-put_sys_clk:
- clk_put(mehci->sys_clk);
+put_phy_clk:
+ clk_put(mehci->phy_clk);
+put_alt_core_clk:
+ clk_put(mehci->alt_core_clk);
+put_core_clk:
+ clk_put(mehci->core_clk);
return ret;
}
diff --git a/drivers/usb/host/ehci-msm72k.c b/drivers/usb/host/ehci-msm72k.c
index e550e2b..87c75e7 100644
--- a/drivers/usb/host/ehci-msm72k.c
+++ b/drivers/usb/host/ehci-msm72k.c
@@ -1,6 +1,6 @@
/* ehci-msm.c - HSUSB Host Controller Driver Implementation
*
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2012, Code Aurora Forum. All rights reserved.
*
* Partly derived from ehci-fsl.c and ehci-hcd.c
* Copyright (c) 2000-2004 by David Brownell
@@ -43,8 +43,8 @@
struct msmusb_hcd {
struct ehci_hcd ehci;
- struct clk *clk;
- struct clk *pclk;
+ struct clk *alt_core_clk;
+ struct clk *iface_clk;
unsigned in_lpm;
struct work_struct lpm_exit_work;
spinlock_t lock;
@@ -96,11 +96,11 @@
/* OTG driver takes care of clock management */
break;
case USB_PHY_SERIAL_PMIC:
- clk_enable(mhcd->clk);
- clk_enable(mhcd->pclk);
+ clk_enable(mhcd->alt_core_clk);
+ clk_enable(mhcd->iface_clk);
break;
default:
- pr_err("%s: undefined phy type ( %X ) \n", __func__,
+ pr_err("%s: undefined phy type ( %X )\n", __func__,
pdata->phy_info);
return;
}
@@ -119,11 +119,11 @@
/* OTG driver takes care of clock management */
break;
case USB_PHY_SERIAL_PMIC:
- clk_disable(mhcd->clk);
- clk_disable(mhcd->pclk);
+ clk_disable(mhcd->alt_core_clk);
+ clk_disable(mhcd->iface_clk);
break;
default:
- pr_err("%s: undefined phy type ( %X ) \n", __func__,
+ pr_err("%s: undefined phy type ( %X )\n", __func__,
pdata->phy_info);
return;
}
@@ -618,7 +618,8 @@
#define ehci_msm_start_hnp NULL
#endif
-static int msm_xusb_init_host(struct msmusb_hcd *mhcd)
+static int msm_xusb_init_host(struct platform_device *pdev,
+ struct msmusb_hcd *mhcd)
{
int ret = 0;
struct msm_otg *otg;
@@ -654,25 +655,25 @@
if (!hcd->regs)
return -EFAULT;
/* get usb clocks */
- mhcd->clk = clk_get(NULL, "usb_hs2_clk");
- if (IS_ERR(mhcd->clk)) {
+ mhcd->alt_core_clk = clk_get(&pdev->dev, "alt_core_clk");
+ if (IS_ERR(mhcd->alt_core_clk)) {
iounmap(hcd->regs);
- return PTR_ERR(mhcd->clk);
+ return PTR_ERR(mhcd->alt_core_clk);
}
- mhcd->pclk = clk_get(NULL, "usb_hs2_pclk");
- if (IS_ERR(mhcd->pclk)) {
+ mhcd->iface_clk = clk_get(&pdev->dev, "iface_clk");
+ if (IS_ERR(mhcd->iface_clk)) {
iounmap(hcd->regs);
- clk_put(mhcd->clk);
- return PTR_ERR(mhcd->pclk);
+ clk_put(mhcd->alt_core_clk);
+ return PTR_ERR(mhcd->iface_clk);
}
mhcd->otg_ops.request = msm_hsusb_request_host;
mhcd->otg_ops.handle = (void *) mhcd;
ret = msm_xusb_init_phy(mhcd);
if (ret < 0) {
iounmap(hcd->regs);
- clk_put(mhcd->clk);
- clk_put(mhcd->pclk);
+ clk_put(mhcd->alt_core_clk);
+ clk_put(mhcd->iface_clk);
}
break;
default:
@@ -724,13 +725,13 @@
INIT_WORK(&mhcd->lpm_exit_work, usb_lpm_exit_w);
wake_lock_init(&mhcd->wlock, WAKE_LOCK_SUSPEND, dev_name(&pdev->dev));
- pdata->ebi1_clk = clk_get(NULL, "ebi1_usb_clk");
+ pdata->ebi1_clk = clk_get(&pdev->dev, "core_clk");
if (IS_ERR(pdata->ebi1_clk))
pdata->ebi1_clk = NULL;
else
clk_set_rate(pdata->ebi1_clk, INT_MAX);
- retval = msm_xusb_init_host(mhcd);
+ retval = msm_xusb_init_host(pdev, mhcd);
if (retval < 0) {
wake_lock_destroy(&mhcd->wlock);
@@ -758,8 +759,8 @@
break;
case USB_PHY_SERIAL_PMIC:
iounmap(hcd->regs);
- clk_put(mhcd->clk);
- clk_put(mhcd->pclk);
+ clk_put(mhcd->alt_core_clk);
+ clk_put(mhcd->iface_clk);
msm_fsusb_reset_phy();
msm_fsusb_rpc_deinit();
break;
diff --git a/drivers/usb/otg/msm72k_otg.c b/drivers/usb/otg/msm72k_otg.c
index be3a279d..59d9769 100644
--- a/drivers/usb/otg/msm72k_otg.c
+++ b/drivers/usb/otg/msm72k_otg.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -369,22 +369,6 @@
PM_QOS_DEFAULT_VALUE);
}
-/* If USB Core is running its protocol engine based on PCLK,
- * PCLK must be running at >60Mhz for correct HSUSB operation and
- * USB core cannot tolerate frequency changes on PCLK. For such
- * USB cores, vote for maximum clk frequency on pclk source
- */
-static void msm_otg_vote_for_pclk_source(struct msm_otg *dev, int vote)
-{
- if (dev->pclk_src && pclk_requires_voting(&dev->otg)) {
-
- if (vote)
- clk_enable(dev->pclk_src);
- else
- clk_disable(dev->pclk_src);
- }
-}
-
/* Controller gives interrupt for every 1 mesc if 1MSIE is set in OTGSC.
* This interrupt can be used as a timer source and OTG timers can be
* implemented. But hrtimers on MSM hardware can give atleast 1/32 KHZ
@@ -578,9 +562,9 @@
if (on)
/* enable clocks */
- clk_enable(dev->hs_clk);
+ clk_enable(dev->alt_core_clk);
else
- clk_disable(dev->hs_clk);
+ clk_disable(dev->alt_core_clk);
return 0;
}
@@ -605,7 +589,7 @@
* low power mode routine
*/
if (dev->pdata->pclk_required_during_lpm)
- clk_enable(dev->hs_pclk);
+ clk_enable(dev->iface_clk);
usb_gadget_vbus_connect(xceiv->gadget);
} else {
@@ -617,7 +601,7 @@
* low power mode routine
*/
if (dev->pdata->pclk_required_during_lpm)
- clk_disable(dev->hs_pclk);
+ clk_disable(dev->iface_clk);
otg_pm_qos_update_latency(dev, 0);
if (pdata->setup_gpio)
@@ -644,9 +628,9 @@
*/
if (dev->pdata->pclk_required_during_lpm) {
if (on)
- clk_enable(dev->hs_pclk);
+ clk_enable(dev->iface_clk);
else
- clk_disable(dev->hs_pclk);
+ clk_disable(dev->iface_clk);
}
dev->start_host(xceiv->host, on);
@@ -774,10 +758,10 @@
/* Ensure that above operation is completed before turning off clocks */
mb();
- if (dev->hs_pclk)
- clk_disable(dev->hs_pclk);
- if (dev->hs_cclk)
- clk_disable(dev->hs_cclk);
+ if (dev->iface_clk)
+ clk_disable(dev->iface_clk);
+
+ clk_disable(dev->core_clk);
/* usb phy no more require TCXO clock, hence vote for TCXO disable*/
ret = msm_xo_mode_vote(dev->xo_handle, MSM_XO_MODE_OFF);
if (ret)
@@ -792,8 +776,6 @@
enable_irq_wake(dev->id_irq);
}
- msm_otg_vote_for_pclk_source(dev, 0);
-
atomic_set(&dev->in_lpm, 1);
/*
@@ -853,12 +835,10 @@
pr_err("%s failed to vote for"
"TCXO D1 buffer%d\n", __func__, ret);
- msm_otg_vote_for_pclk_source(dev, 1);
+ clk_enable(dev->core_clk);
- if (dev->hs_pclk)
- clk_enable(dev->hs_pclk);
- if (dev->hs_cclk)
- clk_enable(dev->hs_cclk);
+ if (dev->iface_clk)
+ clk_enable(dev->iface_clk);
temp = readl(USB_USBCMD);
temp &= ~ASYNC_INTR_CTRL;
@@ -1503,7 +1483,7 @@
unsigned temp;
unsigned long timeout;
- rc = clk_reset(dev->hs_clk, CLK_RESET_ASSERT);
+ rc = clk_reset(dev->alt_core_clk, CLK_RESET_ASSERT);
if (rc) {
pr_err("%s: usb hs clk assert failed\n", __func__);
return -1;
@@ -1511,7 +1491,7 @@
phy_clk_reset(dev);
- rc = clk_reset(dev->hs_clk, CLK_RESET_DEASSERT);
+ rc = clk_reset(dev->alt_core_clk, CLK_RESET_DEASSERT);
if (rc) {
pr_err("%s: usb hs clk deassert failed\n", __func__);
return -1;
@@ -1570,7 +1550,7 @@
unsigned long timeout;
u32 mode, work = 0;
- clk_enable(dev->hs_clk);
+ clk_enable(dev->alt_core_clk);
if (!phy_reset)
goto reset_link;
@@ -1616,7 +1596,7 @@
/* Ensure that RESET operation is completed before turning off clock */
mb();
- clk_disable(dev->hs_clk);
+ clk_disable(dev->alt_core_clk);
if ((xceiv->gadget && xceiv->gadget->is_a_peripheral) ||
test_bit(ID, &dev->inputs))
@@ -2518,30 +2498,26 @@
"Charger Type: %d\n"
"PMIC VBUS Support: %u\n"
"PMIC ID Support: %u\n"
- "Core Clock: %u\n"
"USB In SPS: %d\n"
"pre_emphasis_level: 0x%x\n"
"cdr_auto_reset: 0x%x\n"
"hs_drv_amplitude: 0x%x\n"
"se1_gate_state: 0x%x\n"
"swfi_latency: 0x%x\n"
- "PHY Powercollapse: 0x%x\n"
- "PCLK Voting: 0x%x\n",
+ "PHY Powercollapse: 0x%x\n",
state_string(dev->otg.state),
dev->pdata->otg_mode,
dev->inputs,
atomic_read(&dev->chg_type),
dev->pmic_vbus_notif_supp,
dev->pmic_id_notif_supp,
- dev->pdata->core_clk,
dev->pdata->usb_in_sps,
dev->pdata->pemp_level,
dev->pdata->cdr_autoreset,
dev->pdata->drv_ampl,
dev->pdata->se1_gating,
dev->pdata->swfi_latency,
- dev->pdata->phy_can_powercollapse,
- pclk_requires_voting(&dev->otg));
+ dev->pdata->phy_can_powercollapse);
ret = simple_read_from_buffer(ubuf, count, ppos, buf, temp);
@@ -2646,57 +2622,48 @@
}
}
- dev->hs_clk = clk_get(&pdev->dev, "usb_hs_clk");
- if (IS_ERR(dev->hs_clk)) {
- pr_err("%s: failed to get usb_hs_clk\n", __func__);
- ret = PTR_ERR(dev->hs_clk);
+ dev->alt_core_clk = clk_get(&pdev->dev, "alt_core_clk");
+ if (IS_ERR(dev->alt_core_clk)) {
+ pr_err("%s: failed to get alt_core_clk\n", __func__);
+ ret = PTR_ERR(dev->alt_core_clk);
goto rpc_fail;
}
- clk_set_rate(dev->hs_clk, 60000000);
+ clk_set_rate(dev->alt_core_clk, 60000000);
/* pm qos request to prevent apps idle power collapse */
pm_qos_add_request(&dev->pdata->pm_qos_req_dma, PM_QOS_CPU_DMA_LATENCY,
PM_QOS_DEFAULT_VALUE);
- /* If USB Core is running its protocol engine based on PCLK,
- * PCLK must be running at >60Mhz for correct HSUSB operation and
- * USB core cannot tolerate frequency changes on PCLK. For such
- * USB cores, vote for maximum clk frequency on pclk source
- */
- if (dev->pdata->pclk_src_name) {
- dev->pclk_src = clk_get(0, dev->pdata->pclk_src_name);
- if (IS_ERR(dev->pclk_src))
- goto put_hs_clk;
- clk_set_rate(dev->pclk_src, INT_MAX);
- msm_otg_vote_for_pclk_source(dev, 1);
+ dev->core_clk = clk_get(&pdev->dev, "core_clk");
+ if (IS_ERR(dev->core_clk)) {
+ pr_err("%s: failed to get core_clk\n", __func__);
+ ret = PTR_ERR(dev->core_clk);
+ goto put_alt_core_clk;
}
+ /* CORE clk must be running at >60Mhz for correct HSUSB operation
+ * and USB core cannot tolerate frequency changes on CORE CLK.
+ * Vote for maximum clk frequency for CORE clock.
+ */
+ clk_set_rate(dev->core_clk, INT_MAX);
+
+ clk_enable(dev->core_clk);
if (!dev->pdata->pclk_is_hw_gated) {
- dev->hs_pclk = clk_get(&pdev->dev, "usb_hs_pclk");
- if (IS_ERR(dev->hs_pclk)) {
- pr_err("%s: failed to get usb_hs_pclk\n", __func__);
- ret = PTR_ERR(dev->hs_pclk);
- goto put_pclk_src;
+ dev->iface_clk = clk_get(&pdev->dev, "iface_clk");
+ if (IS_ERR(dev->iface_clk)) {
+ pr_err("%s: failed to get abh_clk\n", __func__);
+ ret = PTR_ERR(dev->iface_clk);
+ goto put_core_clk;
}
- clk_enable(dev->hs_pclk);
- }
-
- if (dev->pdata->core_clk) {
- dev->hs_cclk = clk_get(&pdev->dev, "usb_hs_core_clk");
- if (IS_ERR(dev->hs_cclk)) {
- pr_err("%s: failed to get usb_hs_core_clk\n", __func__);
- ret = PTR_ERR(dev->hs_cclk);
- goto put_hs_pclk;
- }
- clk_enable(dev->hs_cclk);
+ clk_enable(dev->iface_clk);
}
if (!dev->pdata->phy_reset) {
- dev->phy_reset_clk = clk_get(&pdev->dev, "usb_phy_clk");
+ dev->phy_reset_clk = clk_get(&pdev->dev, "phy_clk");
if (IS_ERR(dev->phy_reset_clk)) {
- pr_err("%s: failed to get usb_phy_clk\n", __func__);
+ pr_err("%s: failed to get phy_clk\n", __func__);
ret = PTR_ERR(dev->phy_reset_clk);
- goto put_hs_cclk;
+ goto put_iface_clk;
}
}
@@ -2919,24 +2886,16 @@
put_phy_clk:
if (dev->phy_reset_clk)
clk_put(dev->phy_reset_clk);
-put_hs_cclk:
- if (dev->hs_cclk) {
- clk_disable(dev->hs_cclk);
- clk_put(dev->hs_cclk);
+put_iface_clk:
+ if (dev->iface_clk) {
+ clk_disable(dev->iface_clk);
+ clk_put(dev->iface_clk);
}
-put_hs_pclk:
- if (dev->hs_pclk) {
- clk_disable(dev->hs_pclk);
- clk_put(dev->hs_pclk);
- }
-put_pclk_src:
- if (dev->pclk_src) {
- msm_otg_vote_for_pclk_source(dev, 0);
- clk_put(dev->pclk_src);
- }
-put_hs_clk:
- if (dev->hs_clk)
- clk_put(dev->hs_clk);
+put_core_clk:
+ clk_disable(dev->core_clk);
+ clk_put(dev->core_clk);
+put_alt_core_clk:
+ clk_put(dev->alt_core_clk);
rpc_fail:
if (dev->pdata->rpc_connect)
dev->pdata->rpc_connect(0);
@@ -2983,24 +2942,18 @@
dev->pdata->chg_init(0);
free_irq(dev->irq, pdev);
iounmap(dev->regs);
- if (dev->hs_cclk) {
- clk_disable(dev->hs_cclk);
- clk_put(dev->hs_cclk);
+ clk_disable(dev->core_clk);
+ clk_put(dev->core_clk);
+ if (dev->iface_clk) {
+ clk_disable(dev->iface_clk);
+ clk_put(dev->iface_clk);
}
- if (dev->hs_pclk) {
- clk_disable(dev->hs_pclk);
- clk_put(dev->hs_pclk);
- }
- if (dev->hs_clk)
- clk_put(dev->hs_clk);
+ if (dev->alt_core_clk)
+ clk_put(dev->alt_core_clk);
if (dev->phy_reset_clk)
clk_put(dev->phy_reset_clk);
if (dev->pdata->rpc_connect)
dev->pdata->rpc_connect(0);
- if (dev->pclk_src) {
- msm_otg_vote_for_pclk_source(dev, 0);
- clk_put(dev->pclk_src);
- }
msm_xo_put(dev->xo_handle);
pm_qos_remove_request(&dev->pdata->pm_qos_req_dma);
diff --git a/drivers/usb/otg/msm_otg.c b/drivers/usb/otg/msm_otg.c
index 4932551..f2279be 100644
--- a/drivers/usb/otg/msm_otg.c
+++ b/drivers/usb/otg/msm_otg.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -702,14 +702,7 @@
/* Ensure that above operation is completed before turning off clocks */
mb();
clk_disable(motg->pclk);
- if (motg->core_clk)
- clk_disable(motg->core_clk);
-
- if (!IS_ERR(motg->system_clk))
- clk_disable(motg->system_clk);
-
- if (!IS_ERR(motg->pclk_src))
- clk_disable(motg->pclk_src);
+ clk_disable(motg->core_clk);
/* usb phy no more require TCXO clock, hence vote for TCXO disable */
ret = msm_xo_mode_vote(motg->xo_handle, MSM_XO_MODE_OFF);
@@ -764,15 +757,9 @@
dev_err(otg->dev, "%s failed to vote for "
"TCXO D0 buffer%d\n", __func__, ret);
- if (!IS_ERR(motg->pclk_src))
- clk_enable(motg->pclk_src);
-
- if (!IS_ERR(motg->system_clk))
- clk_enable(motg->system_clk);
+ clk_enable(motg->core_clk);
clk_enable(motg->pclk);
- if (motg->core_clk)
- clk_enable(motg->core_clk);
if (motg->lpm_flags & PHY_PWR_COLLAPSED) {
msm_hsusb_ldo_enable(motg, 1);
@@ -2291,8 +2278,6 @@
&pdata->phy_type);
of_property_read_u32(node, "qcom,hsusb-otg-pmic-id-irq",
&pdata->pmic_id_irq);
- of_property_read_string(node, "qcom,hsusb-otg-pclk-src-name",
- &pdata->pclk_src_name);
return pdata;
}
@@ -2349,13 +2334,13 @@
motg->reset_counter = 0;
/* Some targets don't support PHY clock. */
- motg->phy_reset_clk = clk_get(&pdev->dev, "usb_phy_clk");
+ motg->phy_reset_clk = clk_get(&pdev->dev, "phy_clk");
if (IS_ERR(motg->phy_reset_clk))
- dev_err(&pdev->dev, "failed to get usb_phy_clk\n");
+ dev_err(&pdev->dev, "failed to get phy_clk\n");
- motg->clk = clk_get(&pdev->dev, "usb_hs_clk");
+ motg->clk = clk_get(&pdev->dev, "alt_core_clk");
if (IS_ERR(motg->clk)) {
- dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
+ dev_err(&pdev->dev, "failed to get alt_core_clk\n");
ret = PTR_ERR(motg->clk);
goto put_phy_reset_clk;
}
@@ -2365,55 +2350,42 @@
if (motg->pdata->swfi_latency)
pm_qos_add_request(&motg->pm_qos_req_dma,
PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
+
/*
- * If USB Core is running its protocol engine based on CORE CLK,
+ * USB Core is running its protocol engine based on CORE CLK,
* CORE CLK must be running at >55Mhz for correct HSUSB
* operation and USB core cannot tolerate frequency changes on
* CORE CLK. For such USB cores, vote for maximum clk frequency
* on pclk source
*/
- if (motg->pdata->pclk_src_name) {
- motg->pclk_src = clk_get(&pdev->dev,
- motg->pdata->pclk_src_name);
- if (IS_ERR(motg->pclk_src))
- goto put_clk;
- clk_set_rate(motg->pclk_src, INT_MAX);
- clk_enable(motg->pclk_src);
- } else
- motg->pclk_src = ERR_PTR(-ENOENT);
-
- motg->pclk = clk_get(&pdev->dev, "usb_hs_pclk");
- if (IS_ERR(motg->pclk)) {
- dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
- ret = PTR_ERR(motg->pclk);
- goto put_pclk_src;
- }
-
- motg->system_clk = clk_get(&pdev->dev, "usb_hs_system_clk");
- if (!IS_ERR(motg->system_clk))
- clk_enable(motg->system_clk);
-
- /*
- * USB core clock is not present on all MSM chips. This
- * clock is introduced to remove the dependency on AXI
- * bus frequency.
- */
- motg->core_clk = clk_get(&pdev->dev, "usb_hs_core_clk");
- if (IS_ERR(motg->core_clk))
+ motg->core_clk = clk_get(&pdev->dev, "core_clk");
+ if (IS_ERR(motg->core_clk)) {
motg->core_clk = NULL;
+ dev_err(&pdev->dev, "failed to get core_clk\n");
+ ret = PTR_ERR(motg->clk);
+ goto put_clk;
+ }
+ clk_set_rate(motg->core_clk, INT_MAX);
+
+ motg->pclk = clk_get(&pdev->dev, "iface_clk");
+ if (IS_ERR(motg->pclk)) {
+ dev_err(&pdev->dev, "failed to get iface_clk\n");
+ ret = PTR_ERR(motg->pclk);
+ goto put_core_clk;
+ }
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "failed to get platform resource mem\n");
ret = -ENODEV;
- goto put_core_clk;
+ goto put_pclk;
}
motg->regs = ioremap(res->start, resource_size(res));
if (!motg->regs) {
dev_err(&pdev->dev, "ioremap failed\n");
ret = -ENOMEM;
- goto put_core_clk;
+ goto put_pclk;
}
dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
@@ -2464,9 +2436,7 @@
dev_err(&pdev->dev, "hsusb vreg enable failed\n");
goto free_ldo_init;
}
-
- if (motg->core_clk)
- clk_enable(motg->core_clk);
+ clk_enable(motg->core_clk);
writel(0, USB_USBINTR);
writel(0, USB_OTGSC);
@@ -2554,31 +2524,23 @@
free_irq(motg->irq, motg);
destroy_wlock:
wake_lock_destroy(&motg->wlock);
- clk_disable(motg->pclk);
+ clk_disable(motg->core_clk);
msm_hsusb_ldo_enable(motg, 0);
free_ldo_init:
msm_hsusb_ldo_init(motg, 0);
free_init_vddcx:
msm_hsusb_init_vddcx(motg, 0);
devote_xo_handle:
+ clk_disable(motg->pclk);
msm_xo_mode_vote(motg->xo_handle, MSM_XO_MODE_OFF);
free_xo_handle:
msm_xo_put(motg->xo_handle);
free_regs:
iounmap(motg->regs);
+put_pclk:
+ clk_put(motg->pclk);
put_core_clk:
- if (motg->core_clk)
- clk_put(motg->core_clk);
-
- if (!IS_ERR(motg->system_clk)) {
- clk_disable(motg->system_clk);
- clk_put(motg->system_clk);
- }
-put_pclk_src:
- if (!IS_ERR(motg->pclk_src)) {
- clk_disable(motg->pclk_src);
- clk_put(motg->pclk_src);
- }
+ clk_put(motg->core_clk);
put_clk:
clk_put(motg->clk);
put_phy_reset_clk:
@@ -2637,14 +2599,7 @@
dev_err(otg->dev, "Unable to suspend PHY\n");
clk_disable(motg->pclk);
- if (motg->core_clk)
- clk_disable(motg->core_clk);
- if (!IS_ERR(motg->system_clk))
- clk_disable(motg->system_clk);
- if (!IS_ERR(motg->pclk_src)) {
- clk_disable(motg->pclk_src);
- clk_put(motg->pclk_src);
- }
+ clk_disable(motg->core_clk);
msm_xo_put(motg->xo_handle);
msm_hsusb_ldo_enable(motg, 0);
msm_hsusb_ldo_init(motg, 0);
@@ -2657,10 +2612,7 @@
clk_put(motg->phy_reset_clk);
clk_put(motg->pclk);
clk_put(motg->clk);
- if (motg->core_clk)
- clk_put(motg->core_clk);
- if (!IS_ERR(motg->system_clk))
- clk_put(motg->system_clk);
+ clk_put(motg->core_clk);
if (motg->pdata->swfi_latency)
pm_qos_remove_request(&motg->pm_qos_req_dma);