)]}'
{
  "commit": "5296b56d1b2000b60fb966be161c1f8fb629786b",
  "tree": "18277748caa9ba43610f76a310d34a3b2155e1a5",
  "parents": [
    "ef560682a97491f62ef538931a4861b57d66c52c"
  ],
  "author": {
    "name": "Guennadi Liakhovetski",
    "email": "lg@denx.de",
    "time": "Mon Jan 19 15:36:21 2009 -0700"
  },
  "committer": {
    "name": "Dan Williams",
    "email": "dan.j.williams@intel.com",
    "time": "Mon Jan 19 15:36:21 2009 -0700"
  },
  "message": "i.MX31: Image Processing Unit DMA and IRQ drivers\n\ni.MX3x SoCs contain an Image Processing Unit, consisting of a Control\nModule (CM), Display Interface (DI), Synchronous Display Controller (SDC),\nAsynchronous Display Controller (ADC), Image Converter (IC), Post-Filter\n(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).\nCM contains, among other blocks, an Interrupt Generator (IG) and a Clock\nand Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are\nsupported over dmaengine and irq-chip APIs respectively.\n\nIDMAC is a specialised DMA controller, its DMA channels cannot be used for\ngeneral-purpose operations, even though it might be possible to configure\na memory-to-memory channel for memcpy operation. This driver will not work\nwith generic dmaengine clients, clients, wishing to use it must use\nrespective wrapper structures, they also must specify which channels they\nrequire, as channels are hard-wired to specific IPU functions.\n\nAcked-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n",
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