HAL - Fixme to be updated with latest
Signed-off-by: Liam Girdwood <lrg@ti.com>
diff --git a/sound/soc/omap/abe/Makefile b/sound/soc/omap/abe/Makefile
new file mode 100644
index 0000000..0d5649b
--- /dev/null
+++ b/sound/soc/omap/abe/Makefile
@@ -0,0 +1,14 @@
+snd-soc-abe-hal-objs += abe_main.o \
+ abe_core.o \
+ abe_gain.o \
+ abe_port.o \
+ abe_aess.o \
+ abe_dbg.o \
+ abe_dat.o \
+ abe_ini.o \
+ abe_irq.o \
+ abe_seq.o \
+ abe_asrc.o \
+ port_mgr.o \
+
+obj-$(CONFIG_SND_OMAP_SOC_ABE_DSP) += snd-soc-abe-hal.o
diff --git a/sound/soc/omap/abe/abe.h b/sound/soc/omap/abe/abe.h
new file mode 100644
index 0000000..c465764
--- /dev/null
+++ b/sound/soc/omap/abe/abe.h
@@ -0,0 +1,159 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_H_
+#define _ABE_H_
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+
+#include "abe_def.h"
+#include "abe_define.h"
+#include "abe_fw.h"
+#include "abe_ext.h"
+#include "abe_dbg.h"
+
+/*
+ * BASIC TYPES
+ */
+#define MAX_UINT8 ((((1L << 7) - 1) << 1) + 1)
+#define MAX_UINT16 ((((1L << 15) - 1) << 1) + 1)
+#define MAX_UINT32 ((((1L << 31) - 1) << 1) + 1)
+
+#define s8 char
+#define u8 unsigned char
+#define s16 short
+#define u16 unsigned short
+#define s32 int
+#define u32 unsigned int
+
+struct omap_abe_equ {
+ /* type of filter */
+ u32 equ_type;
+ /* filter length */
+ u32 equ_length;
+ union {
+ /* parameters are the direct and recursive coefficients in */
+ /* Q6.26 integer fixed-point format. */
+ s32 type1[NBEQ1];
+ struct {
+ /* center frequency of the band [Hz] */
+ s32 freq[NBEQ2];
+ /* gain of each band. [dB] */
+ s32 gain[NBEQ2];
+ /* Q factor of this band [dB] */
+ s32 q[NBEQ2];
+ } type2;
+ } coef;
+ s32 equ_param3;
+};
+
+struct omap_abe {
+ void __iomem *io_base[5];
+ u32 firmware_version_number;
+ u16 MultiFrame[PROCESSING_SLOTS][TASKS_IN_SLOT];
+ u32 compensated_mixer_gain;
+ u8 muted_gains_indicator[MAX_NBGAIN_CMEM];
+ u32 desired_gains_decibel[MAX_NBGAIN_CMEM];
+ u32 muted_gains_decibel[MAX_NBGAIN_CMEM];
+ u32 desired_gains_linear[MAX_NBGAIN_CMEM];
+ u32 desired_ramp_delay_ms[MAX_NBGAIN_CMEM];
+ struct mutex mutex;
+ u32 warm_boot;
+
+ u32 irq_dbg_read_ptr;
+
+ struct omap_abe_dbg dbg;
+};
+
+extern struct omap_abe *abe;
+
+void omap_abe_dbg_log(struct omap_abe *abe, u32 x, u32 y, u32 z, u32 t);
+void omap_abe_dbg_error(struct omap_abe *abe, int level, int error);
+int omap_abe_set_opp_processing(struct omap_abe *abe, u32 opp);
+int omap_abe_connect_debug_trace(struct omap_abe *abe,
+ struct omap_abe_dma *dma2);
+
+int omap_abe_use_compensated_gain(struct omap_abe *abe, int on_off);
+int omap_abe_write_equalizer(struct omap_abe *abe,
+ u32 id, struct omap_abe_equ *param);
+
+int omap_abe_disable_gain(struct omap_abe *abe, u32 id, u32 p);
+int omap_abe_enable_gain(struct omap_abe *abe, u32 id, u32 p);
+int omap_abe_mute_gain(struct omap_abe *abe, u32 id, u32 p);
+int omap_abe_unmute_gain(struct omap_abe *abe, u32 id, u32 p);
+
+int omap_abe_write_gain(struct omap_abe *abe,
+ u32 id, s32 f_g, u32 ramp, u32 p);
+int omap_abe_write_mixer(struct omap_abe *abe,
+ u32 id, s32 f_g, u32 f_ramp, u32 p);
+int omap_abe_read_gain(struct omap_abe *abe,
+ u32 id, u32 *f_g, u32 p);
+int omap_abe_read_mixer(struct omap_abe *abe,
+ u32 id, u32 *f_g, u32 p);
+
+/*
+ * MACROS
+ */
+#define _log(x, y, z, t) { if (x & abe->dbg.mask) omap_abe_dbg_log(abe, x, y, z, t); }
+
+#endif/* _ABE_H_ */
diff --git a/sound/soc/omap/abe/abe_aess.c b/sound/soc/omap/abe/abe_aess.c
new file mode 100644
index 0000000..eb35b58
--- /dev/null
+++ b/sound/soc/omap/abe/abe_aess.c
@@ -0,0 +1,191 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include "abe_dbg.h"
+#include "abe.h"
+#include "abe_mem.h"
+#include "abe_aess.h"
+
+/**
+ * omap_abe_hw_configuration
+ *
+ */
+void omap_abe_hw_configuration(struct omap_abe *abe)
+{
+ /* enables the DMAreq from AESS AESS_DMAENABLE_SET = 255 */
+ omap_abe_reg_writel(abe, AESS_DMAENABLE_SET, DMA_ENABLE_ALL);
+ /* enables the MCU IRQ from AESS to Cortex A9 */
+ omap_abe_reg_writel(abe, AESS_MCU_IRQENABLE_SET, INT_SET);
+}
+
+/**
+ * omap_abe_clear_irq - clear ABE interrupt
+ * @abe: Pointer on abe handle
+ *
+ * This subroutine is call to clear MCU Irq
+ */
+int omap_abe_clear_irq(struct omap_abe *abe)
+{
+ omap_abe_reg_writel(abe, ABE_MCU_IRQSTATUS, INT_CLR);
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_clear_irq);
+
+/**
+ * abe_write_event_generator - Selects event generator source
+ * @abe: Pointer on abe handle
+ * @e: Event Generation Counter, McPDM, DMIC or default.
+ *
+ * Loads the AESS event generator hardware source.
+ * Loads the firmware parameters accordingly.
+ * Indicates to the FW which data stream is the most important to preserve
+ * in case all the streams are asynchronous.
+ * If the parameter is "default", then HAL decides which Event source
+ * is the best appropriate based on the opened ports.
+ *
+ * When neither the DMIC and the McPDM are activated, the AE will have
+ * its EVENT generator programmed with the EVENT_COUNTER.
+ * The event counter will be tuned in order to deliver a pulse frequency higher
+ * than 96 kHz.
+ * The DPLL output at 100% OPP is MCLK = (32768kHz x6000) = 196.608kHz
+ * The ratio is (MCLK/96000)+(1<<1) = 2050
+ * (1<<1) in order to have the same speed at 50% and 100% OPP
+ * (only 15 MSB bits are used at OPP50%)
+ */
+int omap_abe_write_event_generator(struct omap_abe *abe, u32 e)
+{
+ u32 event, selection;
+ u32 counter = EVENT_GENERATOR_COUNTER_DEFAULT;
+
+ _log(ABE_ID_WRITE_EVENT_GENERATOR, e, 0, 0);
+
+ switch (e) {
+ case EVENT_TIMER:
+ selection = EVENT_SOURCE_COUNTER;
+ event = 0;
+ break;
+ case EVENT_44100:
+ selection = EVENT_SOURCE_COUNTER;
+ event = 0;
+ counter = EVENT_GENERATOR_COUNTER_44100;
+ break;
+ default:
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_API, ABE_BLOCK_COPY_ERR);
+ }
+ omap_abe_reg_writel(abe, EVENT_GENERATOR_COUNTER, counter);
+ omap_abe_reg_writel(abe, EVENT_SOURCE_SELECTION, selection);
+ omap_abe_reg_writel(abe, EVENT_GENERATOR_START, EVENT_GENERATOR_ON);
+ omap_abe_reg_writel(abe, AUDIO_ENGINE_SCHEDULER, event);
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_write_event_generator);
+
+/**
+ * omap_abe_start_event_generator - Starts event generator source
+ * @abe: Pointer on abe handle
+ *
+ * Start the event genrator of AESS. No more event will be send to AESS engine.
+ * Upper layer must wait 1/96kHz to be sure that engine reaches
+ * the IDLE instruction.
+ */
+int omap_abe_start_event_generator(struct omap_abe *abe)
+{
+ /* Start the event Generator */
+ omap_abe_reg_writel(abe, EVENT_GENERATOR_START, 1);
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_start_event_generator);
+
+/**
+ * omap_abe_stop_event_generator - Stops event generator source
+ * @abe: Pointer on abe handle
+ *
+ * Stop the event genrator of AESS. No more event will be send to AESS engine.
+ * Upper layer must wait 1/96kHz to be sure that engine reaches
+ * the IDLE instruction.
+ */
+int omap_abe_stop_event_generator(struct omap_abe *abe)
+{
+ /* Stop the event Generator */
+ omap_abe_reg_writel(abe, EVENT_GENERATOR_START, 0);
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_stop_event_generator);
+
+/**
+ * omap_abe_disable_irq - disable MCU/DSP ABE interrupt
+ * @abe: Pointer on abe handle
+ *
+ * This subroutine is disabling ABE MCU/DSP Irq
+ */
+int omap_abe_disable_irq(struct omap_abe *abe)
+{
+ /* disables the DMAreq from AESS AESS_DMAENABLE_CLR = 127
+ * DMA_Req7 will still be enabled as it is used for ABE trace */
+ omap_abe_reg_writel(abe, AESS_DMAENABLE_CLR, 0x7F);
+ /* disables the MCU IRQ from AESS to Cortex A9 */
+ omap_abe_reg_writel(abe, AESS_MCU_IRQENABLE_CLR, 0x01);
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_disable_irq);
diff --git a/sound/soc/omap/abe/abe_aess.h b/sound/soc/omap/abe/abe_aess.h
new file mode 100644
index 0000000..70c54f8e
--- /dev/null
+++ b/sound/soc/omap/abe/abe_aess.h
@@ -0,0 +1,113 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_AESS_H_
+#define _ABE_AESS_H_
+
+#define AESS_REVISION 0x00
+#define AESS_MCU_IRQSTATUS 0x28
+#define AESS_MCU_IRQENABLE_SET 0x3C
+#define AESS_MCU_IRQENABLE_CLR 0x40
+#define AESS_DMAENABLE_SET 0x60
+#define AESS_DMAENABLE_CLR 0x64
+#define EVENT_GENERATOR_COUNTER 0x68
+#define EVENT_GENERATOR_START 0x6C
+#define EVENT_SOURCE_SELECTION 0x70
+#define AUDIO_ENGINE_SCHEDULER 0x74
+
+/*
+ * AESS_MCU_IRQSTATUS bit field
+ */
+#define INT_CLEAR 0x01
+
+/*
+ * AESS_MCU_IRQENABLE_SET bit field
+ */
+#define INT_SET 0x01
+
+/*
+ * AESS_MCU_IRQENABLE_CLR bit field
+ */
+#define INT_CLR 0x01
+
+/*
+ * AESS_DMAENABLE_SET bit fields
+ */
+#define DMA_ENABLE_ALL 0xFF
+
+/*
+ * AESS_DMAENABLE_CLR bit fields
+ */
+#define DMA_DISABLE_ALL 0xFF
+
+/*
+ * EVENT_GENERATOR_COUNTER COUNTER_VALUE bit field
+ */
+/* PLL output/desired sampling rate = (32768 * 6000)/96000 */
+#define EVENT_GENERATOR_COUNTER_DEFAULT (2048-1)
+/* PLL output/desired sampling rate = (32768 * 6000)/88200 */
+#define EVENT_GENERATOR_COUNTER_44100 (2228-1)
+
+
+int omap_abe_start_event_generator(struct omap_abe *abe);
+int omap_abe_stop_event_generator(struct omap_abe *abe);
+int omap_abe_write_event_generator(struct omap_abe *abe, u32 e);
+
+void omap_abe_hw_configuration(struct omap_abe *abe);
+
+#endif/* _ABE_AESS_H_ */
diff --git a/sound/soc/omap/abe/abe_api.h b/sound/soc/omap/abe/abe_api.h
new file mode 100644
index 0000000..ba3f7be
--- /dev/null
+++ b/sound/soc/omap/abe/abe_api.h
@@ -0,0 +1,524 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_API_H_
+#define _ABE_API_H_
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include "abe_dm_addr.h"
+#include "abe_dbg.h"
+
+#define ABE_TASK_ID(ID) (OMAP_ABE_D_TASKSLIST_ADDR + sizeof(ABE_STask)*(ID))
+
+#define TASK_ASRC_VX_DL_SLT 1
+#define TASK_ASRC_VX_DL_IDX 2
+#define TASK_VX_DL_SLT 1
+#define TASK_VX_DL_IDX 3
+#define TASK_VX_UL_SLT 12
+#define TASK_VX_UL_IDX 5
+#define TASK_BT_DL_48_8_SLT 14
+#define TASK_BT_DL_48_8_IDX 4
+#define TASK_ASRC_BT_UL_SLT 15
+#define TASK_ASRC_BT_UL_IDX 6
+#define TASK_ASRC_VX_UL_SLT 16
+#define TASK_ASRC_VX_UL_IDX 2
+#define TASK_BT_UL_8_48_SLT 17
+#define TASK_BT_UL_8_48_IDX 2
+#define TASK_IO_MM_DL_SLT 18
+#define TASK_IO_MM_DL_IDX 0
+#define TASK_ASRC_BT_DL_SLT 18
+#define TASK_ASRC_BT_DL_IDX 6
+
+struct omap_abe {
+ void __iomem *io_base[5];
+ u32 firmware_version_number;
+ u16 MultiFrame[PROCESSING_SLOTS][TASKS_IN_SLOT];
+ u32 compensated_mixer_gain;
+ u8 muted_gains_indicator[MAX_NBGAIN_CMEM];
+ u32 desired_gains_decibel[MAX_NBGAIN_CMEM];
+ u32 muted_gains_decibel[MAX_NBGAIN_CMEM];
+ u32 desired_gains_linear[MAX_NBGAIN_CMEM];
+ u32 desired_ramp_delay_ms[MAX_NBGAIN_CMEM];
+ struct mutex mutex;
+ u32 warm_boot;
+
+ u32 irq_dbg_read_ptr;
+ u32 dbg_param;
+
+ struct omap_abe_dbg dbg;
+};
+
+/**
+ * abe_reset_hal - reset the ABE/HAL
+ * @rdev: regulator source
+ * @constraints: constraints to apply
+ *
+ * Operations : reset the HAL by reloading the static variables and
+ * default AESS registers.
+ * Called after a PRCM cold-start reset of ABE
+ */
+abehal_status abe_reset_hal(void);
+/**
+ * abe_load_fw_param - Load ABE Firmware memories
+ * @PMEM: Pointer of Program memory data
+ * @PMEM_SIZE: Size of PMEM data
+ * @CMEM: Pointer of Coeffients memory data
+ * @CMEM_SIZE: Size of CMEM data
+ * @SMEM: Pointer of Sample memory data
+ * @SMEM_SIZE: Size of SMEM data
+ * @DMEM: Pointer of Data memory data
+ * @DMEM_SIZE: Size of DMEM data
+ *
+ */
+abehal_status abe_load_fw_param(u32 *FW);
+/**
+ * abe_reload_fw - Reload ABE Firmware after OFF mode
+ */
+abehal_status abe_reload_fw(void);
+/**
+ * abe_load_fw - Load ABE Firmware and initialize memories
+ *
+ */
+abehal_status abe_load_fw(void);
+/**
+ * abe_irq_processing - Process ABE interrupt
+ *
+ * This subroutine is call upon reception of "MA_IRQ_99 ABE_MPU_IRQ" Audio
+ * back-end interrupt. This subroutine will check the ATC Hrdware, the
+ * IRQ_FIFO from the AE and act accordingly. Some IRQ source are originated
+ * for the delivery of "end of time sequenced tasks" notifications, some are
+ * originated from the Ping-Pong protocols, some are generated from
+ * the embedded debugger when the firmware stops on programmable break-points,
+ * etc ...
+ */
+abehal_status abe_irq_processing(void);
+/**
+ * abe_irq_clear - clear ABE interrupt
+ *
+ * This subroutine is call to clear MCU Irq
+ */
+abehal_status abe_clear_irq(void);
+/**
+ * abe_disable_irq - disable MCU/DSP ABE interrupt
+ *
+ * This subroutine is disabling ABE MCU/DSP Irq
+ */
+abehal_status abe_disable_irq(void);
+/*
+ * abe_check_activity - check all ports are closed
+ */
+u32 abe_check_activity(void);
+/**
+ * abe_wakeup - Wakeup ABE
+ *
+ * Wakeup ABE in case of retention
+ */
+abehal_status abe_wakeup(void);
+/**
+ * abe_start_event_generator - Stops event generator source
+ *
+ * Start the event genrator of AESS. No more event will be send to AESS engine.
+ * Upper layer must wait 1/96kHz to be sure that engine reaches
+ * the IDLE instruction.
+ */
+abehal_status abe_start_event_generator(void);
+/**
+ * abe_stop_event_generator - Stops event generator source
+ *
+ * Stop the event genrator of AESS. No more event will be send to AESS engine.
+ * Upper layer must wait 1/96kHz to be sure that engine reaches
+ * the IDLE instruction.
+ */
+abehal_status abe_stop_event_generator(void);
+
+/**
+ * abe_write_event_generator - Selects event generator source
+ * @e: Event Generation Counter, McPDM, DMIC or default.
+ *
+ * Loads the AESS event generator hardware source.
+ * Loads the firmware parameters accordingly.
+ * Indicates to the FW which data stream is the most important to preserve
+ * in case all the streams are asynchronous.
+ * If the parameter is "default", then HAL decides which Event source
+ * is the best appropriate based on the opened ports.
+ *
+ * When neither the DMIC and the McPDM are activated, the AE will have
+ * its EVENT generator programmed with the EVENT_COUNTER.
+ * The event counter will be tuned in order to deliver a pulse frequency higher
+ * than 96 kHz.
+ * The DPLL output at 100% OPP is MCLK = (32768kHz x6000) = 196.608kHz
+ * The ratio is (MCLK/96000)+(1<<1) = 2050
+ * (1<<1) in order to have the same speed at 50% and 100% OPP
+ * (only 15 MSB bits are used at OPP50%)
+ */
+abehal_status abe_write_event_generator(u32 e);
+/**
+ * abe_set_opp_processing - Set OPP mode for ABE Firmware
+ * @opp: OOPP mode
+ *
+ * New processing network and OPP:
+ * 0: Ultra Lowest power consumption audio player (no post-processing, no mixer)
+ * 1: OPP 25% (simple multimedia features, including low-power player)
+ * 2: OPP 50% (multimedia and voice calls)
+ * 3: OPP100% (EANC, multimedia complex use-cases)
+ *
+ * Rearranges the FW task network to the corresponding OPP list of features.
+ * The corresponding AE ports are supposed to be set/reset accordingly before
+ * this switch.
+ *
+ */
+abehal_status abe_set_opp_processing(u32 opp);
+/**
+ * abe_set_ping_pong_buffer
+ * @port: ABE port ID
+ * @n_bytes: Size of Ping/Pong buffer
+ *
+ * Updates the next ping-pong buffer with "size" bytes copied from the
+ * host processor. This API notifies the FW that the data transfer is done.
+ */
+abehal_status abe_set_ping_pong_buffer(u32 port, u32 n_bytes);
+/**
+ * abe_read_next_ping_pong_buffer
+ * @port: ABE portID
+ * @p: Next buffer address (pointer)
+ * @n: Next buffer size (pointer)
+ *
+ * Tell the next base address of the next ping_pong Buffer and its size
+ */
+abehal_status abe_read_next_ping_pong_buffer(u32 port, u32 *p, u32 *n);
+/**
+ * abe_init_ping_pong_buffer
+ * @id: ABE port ID
+ * @size_bytes:size of the ping pong
+ * @n_buffers:number of buffers (2 = ping/pong)
+ * @p:returned address of the ping-pong list of base address (byte offset
+ from DMEM start)
+ *
+ * Computes the base address of the ping_pong buffers
+ */
+abehal_status abe_init_ping_pong_buffer(u32 id, u32 size_bytes, u32 n_buffers,
+ u32 *p);
+/**
+ * abe_read_offset_from_ping_buffer
+ * @id: ABE port ID
+ * @n: returned address of the offset
+ * from the ping buffer start address (in samples)
+ *
+ * Computes the current firmware ping pong read pointer location,
+ * expressed in samples, as the offset from the start address of ping buffer.
+ */
+abehal_status abe_read_offset_from_ping_buffer(u32 id, u32 *n);
+/**
+ * abe_plug_subroutine
+ * @id: returned sequence index after plugging a new subroutine
+ * @f: subroutine address to be inserted
+ * @n: number of parameters of this subroutine
+ * @params: pointer on parameters
+ *
+ * register a list of subroutines for call-back purpose
+ */
+abehal_status abe_plug_subroutine(u32 *id, abe_subroutine2 f, u32 n,
+ u32 *params);
+/**
+ * abe_set_sequence_time_accuracy
+ * @fast: fast counter
+ * @slow: slow counter
+ *
+ */
+abehal_status abe_set_sequence_time_accuracy(u32 fast, u32 slow);
+/**
+ * abe_reset_port
+ * @id: ABE port ID
+ *
+ * stop the port activity and reload default parameters on the associated
+ * processing features.
+ * Clears the internal AE buffers.
+ */
+abehal_status abe_reset_port(u32 id);
+/**
+ * abe_read_remaining_data
+ * @id: ABE port_ID
+ * @n: size pointer to the remaining number of 32bits words
+ *
+ * computes the remaining amount of data in the buffer.
+ */
+abehal_status abe_read_remaining_data(u32 port, u32 *n);
+/**
+ * abe_disable_data_transfer
+ * @id: ABE port id
+ *
+ * disables the ATC descriptor and stop IO/port activities
+ * disable the IO task (@f = 0)
+ * clear ATC DMEM buffer, ATC enabled
+ */
+abehal_status abe_disable_data_transfer(u32 id);
+/**
+ * abe_enable_data_transfer
+ * @ip: ABE port id
+ *
+ * enables the ATC descriptor
+ * reset ATC pointers
+ * enable the IO task (@f <> 0)
+ */
+abehal_status abe_enable_data_transfer(u32 id);
+/**
+ * abe_set_dmic_filter
+ * @d: DMIC decimation ratio : 16/25/32/40
+ *
+ * Loads in CMEM a specific list of coefficients depending on the DMIC sampling
+ * frequency (2.4MHz or 3.84MHz). This table compensates the DMIC decimator
+ * roll-off at 20kHz.
+ * The default table is loaded with the DMIC 2.4MHz recommended configuration.
+ */
+abehal_status abe_set_dmic_filter(u32 d);
+/**
+ * abe_connect_cbpr_dmareq_port
+ * @id: port name
+ * @f: desired data format
+ * @d: desired dma_request line (0..7)
+ * @a: returned pointer to the base address of the CBPr register and number of
+ * samples to exchange during a DMA_request.
+ *
+ * enables the data echange between a DMA and the ABE through the
+ * CBPr registers of AESS.
+ */
+abehal_status abe_connect_cbpr_dmareq_port(u32 id, abe_data_format_t *f, u32 d,
+ abe_dma_t *returned_dma_t);
+/**
+ * abe_connect_irq_ping_pong_port
+ * @id: port name
+ * @f: desired data format
+ * @I: index of the call-back subroutine to call
+ * @s: half-buffer (ping) size
+ * @p: returned base address of the first (ping) buffer)
+ *
+ * enables the data echanges between a direct access to the DMEM
+ * memory of ABE using cache flush. On each IRQ activation a subroutine
+ * registered with "abe_plug_subroutine" will be called. This subroutine
+ * will generate an amount of samples, send them to DMEM memory and call
+ * "abe_set_ping_pong_buffer" to notify the new amount of samples in the
+ * pong buffer.
+ */
+abehal_status abe_connect_irq_ping_pong_port(u32 id, abe_data_format_t *f,
+ u32 subroutine_id, u32 size,
+ u32 *sink, u32 dsp_mcu_flag);
+/**
+ * abe_connect_serial_port()
+ * @id: port name
+ * @f: data format
+ * @i: peripheral ID (McBSP #1, #2, #3)
+ *
+ * Operations : enables the data echanges between a McBSP and an ATC buffer in
+ * DMEM. This API is used connect 48kHz McBSP streams to MM_DL and 8/16kHz
+ * voice streams to VX_UL, VX_DL, BT_VX_UL, BT_VX_DL. It abstracts the
+ * abe_write_port API.
+ */
+abehal_status abe_connect_serial_port(u32 id, abe_data_format_t *f,
+ u32 mcbsp_id);
+/**
+ * abe_read_port_address
+ * @dma: output pointer to the DMA iteration and data destination pointer
+ *
+ * This API returns the address of the DMA register used on this audio port.
+ * Depending on the protocol being used, adds the base address offset L3
+ * (DMA) or MPU (ARM)
+ */
+abehal_status abe_read_port_address(u32 port, abe_dma_t *dma2);
+/**
+ * abe_write_equalizer
+ * @id: name of the equalizer
+ * @param : equalizer coefficients
+ *
+ * Load the coefficients in CMEM.
+ */
+abehal_status abe_write_equalizer(u32 id, abe_equ_t *param);
+/**
+ * abe_write_asrc
+ * @id: name of the port
+ * @param: drift value to compensate [ppm]
+ *
+ * Load the drift variables to the FW memory. This API can be called only
+ * when the corresponding port has been already opened and the ASRC has
+ * been correctly initialized with API abe_init_asrc_... If this API is
+ * used such that the drift has been changed from positive to negative drift
+ * or vice versa, there will be click in the output signal. Loading the drift
+ * value with zero disables the feature.
+ */
+abehal_status abe_write_asrc(u32 port, s32 dppm);
+/**
+ * abe_write_aps
+ * @id: name of the aps filter
+ * @param: table of filter coefficients
+ *
+ * Load the filters and thresholds coefficients in FW memory. This AP
+ * can be called when the corresponding APS is not activated. After
+ * reloading the firmware the default coefficients corresponds to "no APS
+ * activated".
+ * Loading all the coefficients value with zero disables the feature.
+ */
+abehal_status abe_write_aps(u32 id, struct abe_aps_t *param);
+/**
+ * abe_write_mixer
+ * @id: name of the mixer
+ * @param: list of input gains of the mixer
+ * @p: list of port corresponding to the above gains
+ *
+ * Load the gain coefficients in FW memory. This API can be called when
+ * the corresponding MIXER is not activated. After reloading the firmware
+ * the default coefficients corresponds to "all input and output mixer's gain
+ * in mute state". A mixer is disabled with a network reconfiguration
+ * corresponding to an OPP value.
+ */
+abehal_status abe_write_gain(u32 id, s32 f_g, u32 ramp, u32 p);
+abehal_status abe_use_compensated_gain(u32 on_off);
+abehal_status abe_enable_gain(u32 id, u32 p);
+abehal_status abe_disable_gain(u32 id, u32 p);
+abehal_status abe_mute_gain(u32 id, u32 p);
+abehal_status abe_unmute_gain(u32 id, u32 p);
+/**
+ * abe_write_mixer
+ * @id: name of the mixer
+ * @param: input gains and delay ramp of the mixer
+ * @p: port corresponding to the above gains
+ *
+ * Load the gain coefficients in FW memory. This API can be called when
+ * the corresponding MIXER is not activated. After reloading the firmware
+ * the default coefficients corresponds to "all input and output mixer's
+ * gain in mute state". A mixer is disabled with a network reconfiguration
+ * corresponding to an OPP value.
+ */
+abehal_status abe_write_mixer(u32 id, s32 f_g, u32 f_ramp, u32 p);
+/**
+ * abe_read_gain
+ * @id: name of the mixer
+ * @param: list of input gains of the mixer
+ * @p: list of port corresponding to the above gains
+ *
+ */
+abehal_status abe_read_gain(u32 id, u32 *f_g, u32 p);
+/**
+ * abe_read_mixer
+ * @id: name of the mixer
+ * @param: gains of the mixer
+ * @p: port corresponding to the above gains
+ *
+ * Load the gain coefficients in FW memory. This API can be called when
+ * the corresponding MIXER is not activated. After reloading the firmware
+ * the default coefficients corresponds to "all input and output mixer's
+ * gain in mute state". A mixer is disabled with a network reconfiguration
+ * corresponding to an OPP value.
+ */
+abehal_status abe_read_mixer(u32 id, u32 *f_g, u32 p);
+/**
+ * abe_set_router_configuration
+ * @Id: name of the router
+ * @Conf: id of the configuration
+ * @param: list of output index of the route
+ *
+ * The uplink router takes its input from DMIC (6 samples), AMIC (2 samples)
+ * and PORT1/2 (2 stereo ports). Each sample will be individually stored in
+ * an intermediate table of 10 elements. The intermediate table is used to
+ * route the samples to three directions : REC1 mixer, 2 EANC DMIC source of
+ * filtering and MM recording audio path.
+ */
+abehal_status abe_set_router_configuration(u32 id, u32 k, u32 *param);
+/**
+ * ABE_READ_DEBUG_TRACE
+ *
+ * Parameters :
+ * @data: data destination pointer
+ * @n : max number of read data
+ *
+ * Operations :
+ * Reads the AE circular data pointer that holds pairs of debug data +
+ * timestamps, and stores the pairs, via linear addressing, to the parameter
+ * pointer.
+ * Stops the copy when the max parameter is reached or when the FIFO is empty.
+ *
+ * Return value :
+ * None.
+ */
+abehal_status abe_read_debug_trace(u32 *data, u32 *n);
+/**
+ * abe_connect_debug_trace
+ * @dma2:pointer to the DMEM trace buffer
+ *
+ * returns the address and size of the real-time debug trace buffer,
+ * the content of which will vary from one firmware release to an other
+ */
+abehal_status abe_connect_debug_trace(abe_dma_t *dma2);
+/**
+ * abe_set_debug_trace
+ * @debug: debug ID from a list to be defined
+ *
+ * load a mask which filters the debug trace to dedicated types of data
+ */
+abehal_status abe_set_debug_trace(abe_dbg_t debug);
+/**
+ * abe_init_mem - Allocate Kernel space memory map for ABE
+ *
+ * Memory map of ABE memory space for PMEM/DMEM/SMEM/DMEM
+ */
+void abe_init_mem(void __iomem **_io_base);
+
+#endif/* _ABE_API_H_ */
diff --git a/sound/soc/omap/abe/abe_asrc.c b/sound/soc/omap/abe/abe_asrc.c
new file mode 100644
index 0000000..bd49149
--- /dev/null
+++ b/sound/soc/omap/abe/abe_asrc.c
@@ -0,0 +1,1196 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include "abe_legacy.h"
+#include "abe_dbg.h"
+
+#include "abe_typedef.h"
+#include "abe_initxxx_labels.h"
+#include "abe_dbg.h"
+#include "abe_mem.h"
+#include "abe_sm_addr.h"
+#include "abe_cm_addr.h"
+
+/**
+ * abe_write_fifo
+ * @mem_bank: currently only ABE_DMEM supported
+ * @addr: FIFO descriptor address ( descriptor fields : READ ptr, WRITE ptr,
+ * FIFO START_ADDR, FIFO END_ADDR)
+ * @data: data to write to FIFO
+ * @number: number of 32-bit words to write to DMEM FIFO
+ *
+ * write DMEM FIFO and update FIFO descriptor,
+ * it is assumed that FIFO descriptor is located in DMEM
+ */
+void abe_write_fifo(u32 memory_bank, u32 descr_addr, u32 *data, u32 nb_data32)
+{
+ u32 fifo_addr[4];
+ u32 i;
+ /* read FIFO descriptor from DMEM */
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM, descr_addr,
+ &fifo_addr[0], 4 * sizeof(u32));
+ /* WRITE ptr < FIFO start address */
+ if (fifo_addr[1] < fifo_addr[2])
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_DBG,
+ ABE_FW_FIFO_WRITE_PTR_ERR);
+ /* WRITE ptr > FIFO end address */
+ if (fifo_addr[1] > fifo_addr[3])
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_DBG,
+ ABE_FW_FIFO_WRITE_PTR_ERR);
+ switch (memory_bank) {
+ case ABE_DMEM:
+ for (i = 0; i < nb_data32; i++) {
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ (s32) fifo_addr[1], (u32 *) (data + i),
+ 4);
+ /* increment WRITE pointer */
+ fifo_addr[1] = fifo_addr[1] + 4;
+ if (fifo_addr[1] > fifo_addr[3])
+ fifo_addr[1] = fifo_addr[2];
+ if (fifo_addr[1] == fifo_addr[0])
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_DBG,
+ ABE_FW_FIFO_WRITE_PTR_ERR);
+ }
+ /* update WRITE pointer in DMEM */
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM, descr_addr +
+ sizeof(u32), &fifo_addr[1], 4);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * abe_write_asrc
+ * @id: name of the port
+ * @param: drift value to compensate [ppm]
+ *
+ * Load the drift variables to the FW memory. This API can be called only
+ * when the corresponding port has been already opened and the ASRC has
+ * been correctly initialized with API abe_init_asrc_... If this API is
+ * used such that the drift has been changed from positive to negative drift
+ * or vice versa, there will be click in the output signal. Loading the drift
+ * value with zero disables the feature.
+ */
+abehal_status abe_write_asrc(u32 port, s32 dppm)
+{
+ s32 dtempvalue, adppm, drift_sign, drift_sign_addr, alpha_params_addr;
+ s32 alpha_params[3];
+ _log(ABE_ID_WRITE_ASRC, port, dppm, dppm >> 8);
+ /*
+ * x = ppm
+ *
+ * - 1000000/x must be multiple of 16
+ * - deltaalpha = round(2^20*x*16/1000000)=round(2^18/5^6*x) on 22 bits.
+ * then shifted by 2bits
+ * - minusdeltaalpha
+ * - oneminusepsilon = 1-deltaalpha/2.
+ *
+ * ppm = 250
+ * - 1000000/250=4000
+ * - deltaalpha = 4194.3 ~ 4195 => 0x00418c
+ */
+ /* examples for -6250 ppm */
+ /* atempvalue32[1] = -1; d_driftsign */
+ /* atempvalue32[3] = 0x00066668; d_deltaalpha */
+ /* atempvalue32[4] = 0xfff99998; d_minusdeltaalpha */
+ /* atempvalue32[5] = 0x003ccccc; d_oneminusepsilon */
+ /* example for 100 ppm */
+ /* atempvalue32[1] = 1;* d_driftsign */
+ /* atempvalue32[3] = 0x00001a38; d_deltaalpha */
+ /* atempvalue32[4] = 0xffffe5c8; d_minusdeltaalpha */
+ /* atempvalue32[5] = 0x003ccccc; d_oneminusepsilon */
+ /* compute new value for the ppm */
+ if (dppm >= 0) {
+ /* d_driftsign */
+ drift_sign = 1;
+ adppm = dppm;
+ } else {
+ /* d_driftsign */
+ drift_sign = -1;
+ adppm = (-1 * dppm);
+ }
+ if (dppm == 0) {
+ /* delta_alpha */
+ alpha_params[0] = 0;
+ /* minusdelta_alpha */
+ alpha_params[1] = 0;
+ /* one_minusepsilon */
+ alpha_params[2] = 0x003ffff0;
+ } else {
+ dtempvalue = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L);
+ /* delta_alpha */
+ alpha_params[0] = dtempvalue << 2;
+ /* minusdelta_alpha */
+ alpha_params[1] = (-dtempvalue) << 2;
+ /* one_minusepsilon */
+ alpha_params[2] = (0x00100000 - (dtempvalue / 2)) << 2;
+ }
+ switch (port) {
+ /* asynchronous sample-rate-converter for the uplink voice path */
+ case OMAP_ABE_VX_DL_PORT:
+ drift_sign_addr = OMAP_ABE_D_ASRCVARS_DL_VX_ADDR + (1 * sizeof(s32));
+ alpha_params_addr = OMAP_ABE_D_ASRCVARS_DL_VX_ADDR + (3 * sizeof(s32));
+ break;
+ /* asynchronous sample-rate-converter for the downlink voice path */
+ case OMAP_ABE_VX_UL_PORT:
+ drift_sign_addr = OMAP_ABE_D_ASRCVARS_UL_VX_ADDR + (1 * sizeof(s32));
+ alpha_params_addr = OMAP_ABE_D_ASRCVARS_UL_VX_ADDR + (3 * sizeof(s32));
+ break;
+ /* asynchronous sample-rate-converter for the BT_UL path */
+ case OMAP_ABE_BT_VX_UL_PORT:
+ drift_sign_addr = OMAP_ABE_D_ASRCVARS_BT_UL_ADDR + (1 * sizeof(s32));
+ alpha_params_addr = OMAP_ABE_D_ASRCVARS_BT_UL_ADDR + (3 * sizeof(s32));
+ break;
+ /* asynchronous sample-rate-converter for the BT_DL path */
+ case OMAP_ABE_BT_VX_DL_PORT:
+ drift_sign_addr = OMAP_ABE_D_ASRCVARS_BT_DL_ADDR + (1 * sizeof(s32));
+ alpha_params_addr = OMAP_ABE_D_ASRCVARS_BT_DL_ADDR + (3 * sizeof(s32));
+ break;
+ default:
+ /* asynchronous sample-rate-converter for the MM_EXT_IN path */
+ case OMAP_ABE_MM_EXT_IN_PORT:
+ drift_sign_addr = OMAP_ABE_D_ASRCVARS_MM_EXT_IN_ADDR + (1 * sizeof(s32));
+ alpha_params_addr =
+ OMAP_ABE_D_ASRCVARS_MM_EXT_IN_ADDR + (3 * sizeof(s32));
+ break;
+ }
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM, drift_sign_addr,
+ (u32 *) &drift_sign, 4);
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM, alpha_params_addr,
+ (u32 *) &alpha_params[0], 12);
+ return 0;
+}
+EXPORT_SYMBOL(abe_write_asrc);
+/**
+ * abe_init_asrc_vx_dl
+ *
+ * Initialize the following ASRC VX_DL parameters :
+ * 1. DriftSign = D_AsrcVars[1] = 1 or -1
+ * 2. Subblock = D_AsrcVars[2] = 0
+ * 3. DeltaAlpha = D_AsrcVars[3] =
+ * (round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2
+ * 4. MinusDeltaAlpha = D_AsrcVars[4] =
+ * (-round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2
+ * 5. OneMinusEpsilon = D_AsrcVars[5] = 1 - DeltaAlpha/2
+ * 6. AlphaCurrent = 0x000020 (CMEM), initial value of Alpha parameter
+ * 7. BetaCurrent = 0x3fffe0 (CMEM), initial value of Beta parameter
+ * AlphaCurrent + BetaCurrent = 1 (=0x400000 in CMEM = 2^20 << 2)
+ * 8. drift_ASRC = 0 & drift_io = 0
+ * 9. SMEM for ASRC_DL_VX_Coefs pointer
+ * 10. CMEM for ASRC_DL_VX_Coefs pointer
+ * ASRC_DL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/
+ * C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1
+ * 11. SMEM for XinASRC_DL_VX pointer
+ * 12. CMEM for XinASRC_DL_VX pointer
+ * XinASRC_DL_VX = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/0/1/0/0/0/0
+ * 13. SMEM for IO_VX_DL_ASRC pointer
+ * 14. CMEM for IO_VX_DL_ASRC pointer
+ * IO_VX_DL_ASRC =
+ * S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/
+ * ASRC_DL_VX_FIR_L+ASRC_margin/1/0/0/0/0
+ */
+void abe_init_asrc_vx_dl(s32 dppm)
+{
+ s32 el[45];
+ s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr;
+ u32 i = 0;
+ u32 n_fifo_el = 42;
+ temp0 = 0;
+ temp1 = 1;
+ /* 1. DriftSign = D_AsrcVars[1] = 1 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_DL_VX_ADDR + (1 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm >= 0) {
+ el[i + 1] = 1;
+ adppm = dppm;
+ } else {
+ el[i + 1] = -1;
+ adppm = (-1 * dppm);
+ }
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ dtemp = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L);
+ /* 2. Subblock = D_AsrcVars[2] = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_DL_VX_ADDR + (2 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 3. DeltaAlpha = D_AsrcVars[3] = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_DL_VX_ADDR + (3 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm == 0)
+ el[i + 1] = 0;
+ else
+ el[i + 1] = dtemp << 2;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_DL_VX_ADDR + (4 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm == 0)
+ el[i + 1] = 0;
+ else
+ el[i + 1] = (-dtemp) << 2;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /*5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_DL_VX_ADDR + (5 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm == 0)
+ el[i + 1] = 0x00400000;
+ else
+ el[i + 1] = (0x00100000 - (dtemp / 2)) << 2;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 6. AlphaCurrent = 0x000020 (CMEM) */
+ mem_tag = ABE_CMEM;
+ mem_addr = OMAP_ABE_C_ALPHACURRENT_DL_VX_ADDR;
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = 0x00000020;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 7. BetaCurrent = 0x3fffe0 (CMEM) */
+ mem_tag = ABE_CMEM;
+ mem_addr = OMAP_ABE_C_BETACURRENT_DL_VX_ADDR;
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = 0x003fffe0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 8. drift_ASRC = 0 & drift_io = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_IODESCR_ADDR + (OMAP_ABE_VX_DL_PORT * sizeof(struct ABE_SIODescriptor))
+ + drift_asrc_;
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 9. SMEM for ASRC_DL_VX_Coefs pointer */
+ /* ASRC_DL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/
+ C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
+ mem_tag = ABE_SMEM;
+ mem_addr = ASRC_DL_VX_Coefs_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_C_COEFASRC16_VX_ADDR >> 2;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_C_COEFASRC16_VX_SIZE >> 2);
+ el[i + 2] = OMAP_ABE_C_COEFASRC15_VX_ADDR >> 2;
+ el[i + 2] = (el[i + 2] << 8) + (OMAP_ABE_C_COEFASRC15_VX_SIZE >> 2);
+ i = i + 3;
+ /* 10. CMEM for ASRC_DL_VX_Coefs pointer */
+ /* ASRC_DL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/
+ C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
+ mem_tag = ABE_CMEM;
+ mem_addr = ASRC_DL_VX_Coefs_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp1;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 11. SMEM for XinASRC_DL_VX pointer */
+ /* XinASRC_DL_VX =
+ S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/0/1/0/0/0/0 */
+ mem_tag = ABE_SMEM;
+ mem_addr = XinASRC_DL_VX_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_S_XINASRC_DL_VX_ADDR >> 3;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_S_XINASRC_DL_VX_SIZE >> 3);
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 12. CMEM for XinASRC_DL_VX pointer */
+ /* XinASRC_DL_VX =
+ S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/0/1/0/0/0/0 */
+ mem_tag = ABE_CMEM;
+ mem_addr = XinASRC_DL_VX_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 13. SMEM for IO_VX_DL_ASRC pointer */
+ /* IO_VX_DL_ASRC = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/
+ ASRC_DL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
+ mem_tag = ABE_SMEM;
+ mem_addr = IO_VX_DL_ASRC_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_S_XINASRC_DL_VX_ADDR >> 3;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_S_XINASRC_DL_VX_SIZE >> 3);
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 14. CMEM for IO_VX_DL_ASRC pointer */
+ /* IO_VX_DL_ASRC = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/
+ ASRC_DL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
+ mem_tag = ABE_CMEM;
+ mem_addr = IO_VX_DL_ASRC_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = ((ASRC_DL_VX_FIR_L + ASRC_margin) << 16) + (temp1 << 12)
+ + (temp0 << 4) + temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ abe_write_fifo(ABE_DMEM, OMAP_ABE_D_FWMEMINITDESCR_ADDR, (u32 *) &el[0],
+ n_fifo_el);
+}
+/**
+ * abe_init_asrc_vx_ul
+ *
+ * Initialize the following ASRC VX_UL parameters :
+ * 1. DriftSign = D_AsrcVars[1] = 1 or -1
+ * 2. Subblock = D_AsrcVars[2] = 0
+ * 3. DeltaAlpha = D_AsrcVars[3] =
+ * (round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2
+ * 4. MinusDeltaAlpha = D_AsrcVars[4] =
+ * (-round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2
+ * 5. OneMinusEpsilon = D_AsrcVars[5] = 1 - DeltaAlpha/2
+ * 6. AlphaCurrent = 0x000020 (CMEM), initial value of Alpha parameter
+ * 7. BetaCurrent = 0x3fffe0 (CMEM), initial value of Beta parameter
+ * AlphaCurrent + BetaCurrent = 1 (=0x400000 in CMEM = 2^20 << 2)
+ * 8. drift_ASRC = 0 & drift_io = 0
+ * 9. SMEM for ASRC_UL_VX_Coefs pointer
+ * 10. CMEM for ASRC_UL_VX_Coefs pointer
+ * ASRC_UL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/
+ * C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1
+ * 11. SMEM for XinASRC_UL_VX pointer
+ * 12. CMEM for XinASRC_UL_VX pointer
+ * XinASRC_UL_VX = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/0/1/0/0/0/0
+ * 13. SMEM for UL_48_8_DEC pointer
+ * 14. CMEM for UL_48_8_DEC pointer
+ * UL_48_8_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/
+ * ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0
+ * 15. SMEM for UL_48_16_DEC pointer
+ * 16. CMEM for UL_48_16_DEC pointer
+ * UL_48_16_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/
+ * ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0
+ */
+void abe_init_asrc_vx_ul(s32 dppm)
+{
+ s32 el[51];
+ s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr;
+ u32 i = 0;
+ u32 n_fifo_el = 48;
+ temp0 = 0;
+ temp1 = 1;
+ /* 1. DriftSign = D_AsrcVars[1] = 1 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_UL_VX_ADDR + (1 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm >= 0) {
+ el[i + 1] = 1;
+ adppm = dppm;
+ } else {
+ el[i + 1] = -1;
+ adppm = (-1 * dppm);
+ }
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ dtemp = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L);
+ /* 2. Subblock = D_AsrcVars[2] = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_UL_VX_ADDR + (2 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 3. DeltaAlpha = D_AsrcVars[3] = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_UL_VX_ADDR + (3 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm == 0)
+ el[i + 1] = 0;
+ else
+ el[i + 1] = dtemp << 2;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_UL_VX_ADDR + (4 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm == 0)
+ el[i + 1] = 0;
+ else
+ el[i + 1] = (-dtemp) << 2;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_UL_VX_ADDR + (5 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm == 0)
+ el[i + 1] = 0x00400000;
+ else
+ el[i + 1] = (0x00100000 - (dtemp / 2)) << 2;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 6. AlphaCurrent = 0x000020 (CMEM) */
+ mem_tag = ABE_CMEM;
+ mem_addr = OMAP_ABE_C_ALPHACURRENT_UL_VX_ADDR;
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = 0x00000020;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 7. BetaCurrent = 0x3fffe0 (CMEM) */
+ mem_tag = ABE_CMEM;
+ mem_addr = OMAP_ABE_C_BETACURRENT_UL_VX_ADDR;
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = 0x003fffe0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 8. drift_ASRC = 0 & drift_io = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_IODESCR_ADDR + (OMAP_ABE_VX_UL_PORT * sizeof(struct ABE_SIODescriptor))
+ + drift_asrc_;
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 9. SMEM for ASRC_UL_VX_Coefs pointer */
+ /* ASRC_UL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/
+ C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
+ mem_tag = ABE_SMEM;
+ mem_addr = ASRC_UL_VX_Coefs_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_C_COEFASRC16_VX_ADDR >> 2;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_C_COEFASRC16_VX_SIZE >> 2);
+ el[i + 2] = OMAP_ABE_C_COEFASRC15_VX_ADDR >> 2;
+ el[i + 2] = (el[i + 2] << 8) + (OMAP_ABE_C_COEFASRC15_VX_SIZE >> 2);
+ i = i + 3;
+ /* 10. CMEM for ASRC_UL_VX_Coefs pointer */
+ /* ASRC_UL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/
+ C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
+ mem_tag = ABE_CMEM;
+ mem_addr = ASRC_UL_VX_Coefs_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp1;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 11. SMEM for XinASRC_UL_VX pointer */
+ /* XinASRC_UL_VX = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/0/1/
+ 0/0/0/0 */
+ mem_tag = ABE_SMEM;
+ mem_addr = XinASRC_UL_VX_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_S_XINASRC_UL_VX_ADDR >> 3;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_S_XINASRC_UL_VX_SIZE >> 3);
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 12. CMEM for XinASRC_UL_VX pointer */
+ /* XinASRC_UL_VX = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/0/1/
+ 0/0/0/0 */
+ mem_tag = ABE_CMEM;
+ mem_addr = XinASRC_UL_VX_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 13. SMEM for UL_48_8_DEC pointer */
+ /* UL_48_8_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/
+ ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
+ mem_tag = ABE_SMEM;
+ mem_addr = UL_48_8_DEC_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_S_XINASRC_UL_VX_ADDR >> 3;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_S_XINASRC_UL_VX_SIZE >> 3);
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 14. CMEM for UL_48_8_DEC pointer */
+ /* UL_48_8_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/
+ ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
+ mem_tag = ABE_CMEM;
+ mem_addr = UL_48_8_DEC_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = ((ASRC_UL_VX_FIR_L + ASRC_margin) << 16) + (temp1 << 12)
+ + (temp0 << 4) + temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 15. SMEM for UL_48_16_DEC pointer */
+ /* UL_48_16_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/
+ ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
+ mem_tag = ABE_SMEM;
+ mem_addr = UL_48_16_DEC_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_S_XINASRC_UL_VX_ADDR >> 3;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_S_XINASRC_UL_VX_SIZE >> 3);
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 16. CMEM for UL_48_16_DEC pointer */
+ /* UL_48_16_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/
+ ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
+ mem_tag = ABE_CMEM;
+ mem_addr = UL_48_16_DEC_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = ((ASRC_UL_VX_FIR_L + ASRC_margin) << 16) + (temp1 << 12)
+ + (temp0 << 4) + temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ abe_write_fifo(ABE_DMEM, OMAP_ABE_D_FWMEMINITDESCR_ADDR, (u32 *) &el[0],
+ n_fifo_el);
+}
+/**
+ * abe_init_asrc_mm_ext_in
+ *
+ * Initialize the following ASRC MM_EXT_IN parameters :
+ * 1. DriftSign = D_AsrcVars[1] = 1 or -1
+ * 2. Subblock = D_AsrcVars[2] = 0
+ * 3. DeltaAlpha = D_AsrcVars[3] =
+ * (round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2
+ * 4. MinusDeltaAlpha = D_AsrcVars[4] =
+ * (-round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2
+ * 5. OneMinusEpsilon = D_AsrcVars[5] = 1 - DeltaAlpha/2
+ * 6. AlphaCurrent = 0x000020 (CMEM), initial value of Alpha parameter
+ * 7. BetaCurrent = 0x3fffe0 (CMEM), initial value of Beta parameter
+ * AlphaCurrent + BetaCurrent = 1 (=0x400000 in CMEM = 2^20 << 2)
+ * 8. drift_ASRC = 0 & drift_io = 0
+ * 9. SMEM for ASRC_MM_EXT_IN_Coefs pointer
+ * 10. CMEM for ASRC_MM_EXT_IN_Coefs pointer
+ * ASRC_MM_EXT_IN_Coefs = C_CoefASRC16_MM_ADDR/C_CoefASRC16_MM_sizeof/0/1/
+ * C_CoefASRC15_MM_ADDR/C_CoefASRC15_MM_sizeof/0/1
+ * 11. SMEM for XinASRC_MM_EXT_IN pointer
+ * 12. CMEM for XinASRC_MM_EXT_IN pointer
+ * XinASRC_MM_EXT_IN = S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/0/1/
+ * 0/0/0/0
+ * 13. SMEM for IO_MM_EXT_IN_ASRC pointer
+ * 14. CMEM for IO_MM_EXT_IN_ASRC pointer
+ * IO_MM_EXT_IN_ASRC = S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/
+ * ASRC_MM_EXT_IN_FIR_L+ASRC_margin+ASRC_N_48k/1/0/0/0/0
+ */
+void abe_init_asrc_mm_ext_in(s32 dppm)
+{
+ s32 el[45];
+ s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr;
+ u32 i = 0;
+ u32 n_fifo_el = 42;
+ temp0 = 0;
+ temp1 = 1;
+ /* 1. DriftSign = D_AsrcVars[1] = 1 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_MM_EXT_IN_ADDR + (1 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm >= 0) {
+ el[i + 1] = 1;
+ adppm = dppm;
+ } else {
+ el[i + 1] = -1;
+ adppm = (-1 * dppm);
+ }
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ dtemp = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L);
+ /* 2. Subblock = D_AsrcVars[2] = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_MM_EXT_IN_ADDR + (2 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 3. DeltaAlpha = D_AsrcVars[3] = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_MM_EXT_IN_ADDR + (3 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm == 0)
+ el[i + 1] = 0;
+ else
+ el[i + 1] = dtemp << 2;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_MM_EXT_IN_ADDR + (4 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm == 0)
+ el[i + 1] = 0;
+ else
+ el[i + 1] = (-dtemp) << 2;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_MM_EXT_IN_ADDR + (5 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm == 0)
+ el[i + 1] = 0x00400000;
+ else
+ el[i + 1] = (0x00100000 - (dtemp / 2)) << 2;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 6. AlphaCurrent = 0x000020 (CMEM) */
+ mem_tag = ABE_CMEM;
+ mem_addr = OMAP_ABE_C_ALPHACURRENT_MM_EXT_IN_ADDR;
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = 0x00000020;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 7. BetaCurrent = 0x3fffe0 (CMEM) */
+ mem_tag = ABE_CMEM;
+ mem_addr = OMAP_ABE_C_BETACURRENT_MM_EXT_IN_ADDR;
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = 0x003fffe0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 8. drift_ASRC = 0 & drift_io = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_IODESCR_ADDR + (OMAP_ABE_MM_EXT_IN_PORT * sizeof(struct ABE_SIODescriptor))
+ + drift_asrc_;
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 9. SMEM for ASRC_MM_EXT_IN_Coefs pointer */
+ /* ASRC_MM_EXT_IN_Coefs = C_CoefASRC16_MM_ADDR/C_CoefASRC16_MM_sizeof/
+ 0/1/C_CoefASRC15_MM_ADDR/C_CoefASRC15_MM_sizeof/0/1 */
+ mem_tag = ABE_SMEM;
+ mem_addr = ASRC_MM_EXT_IN_Coefs_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_C_COEFASRC16_MM_ADDR >> 2;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_C_COEFASRC16_MM_SIZE >> 2);
+ el[i + 2] = OMAP_ABE_C_COEFASRC15_MM_ADDR >> 2;
+ el[i + 2] = (el[i + 2] << 8) + (OMAP_ABE_C_COEFASRC15_MM_SIZE >> 2);
+ i = i + 3;
+ /*10. CMEM for ASRC_MM_EXT_IN_Coefs pointer */
+ /* ASRC_MM_EXT_IN_Coefs = C_CoefASRC16_MM_ADDR/C_CoefASRC16_MM_sizeof/
+ 0/1/C_CoefASRC15_MM_ADDR/C_CoefASRC15_MM_sizeof/0/1 */
+ mem_tag = ABE_CMEM;
+ mem_addr = ASRC_MM_EXT_IN_Coefs_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp1;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 11. SMEM for XinASRC_MM_EXT_IN pointer */
+ /* XinASRC_MM_EXT_IN = S_XinASRC_MM_EXT_IN_ADDR/
+ S_XinASRC_MM_EXT_IN_sizeof/0/1/0/0/0/0 */
+ mem_tag = ABE_SMEM;
+ mem_addr = XinASRC_MM_EXT_IN_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_S_XINASRC_MM_EXT_IN_ADDR >> 3;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_S_XINASRC_MM_EXT_IN_SIZE >> 3);
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 12. CMEM for XinASRC_MM_EXT_IN pointer */
+ /* XinASRC_MM_EXT_IN = S_XinASRC_MM_EXT_IN_ADDR/
+ S_XinASRC_MM_EXT_IN_sizeof/0/1/0/0/0/0 */
+ mem_tag = ABE_CMEM;
+ mem_addr = XinASRC_MM_EXT_IN_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 13. SMEM for IO_MM_EXT_IN_ASRC pointer */
+ /* IO_MM_EXT_IN_ASRC =
+ S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/
+ ASRC_MM_EXT_IN_FIR_L+ASRC_margin+ASRC_N_48k/1/0/0/0/0 */
+ mem_tag = ABE_SMEM;
+ mem_addr = IO_MM_EXT_IN_ASRC_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_S_XINASRC_MM_EXT_IN_ADDR >> 3;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_S_XINASRC_MM_EXT_IN_SIZE >> 3);
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 14. CMEM for IO_MM_EXT_IN_ASRC pointer */
+ /* IO_MM_EXT_IN_ASRC =
+ S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/
+ ASRC_MM_EXT_IN_FIR_L+ASRC_margin+ASRC_N_48k/1/0/0/0/0 */
+ mem_tag = ABE_CMEM;
+ mem_addr = IO_MM_EXT_IN_ASRC_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = ((ASRC_MM_EXT_IN_FIR_L + ASRC_margin + ASRC_N_48k) << 16) +
+ (temp1 << 12) + (temp0 << 4) + temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ abe_write_fifo(ABE_DMEM, OMAP_ABE_D_FWMEMINITDESCR_ADDR, (u32 *) &el[0],
+ n_fifo_el);
+}
+/**
+ * abe_init_asrc_bt_ul
+ *
+ * Initialize the following ASRC BT_UL parameters :
+ * 1. DriftSign = D_AsrcVars[1] = 1 or -1
+ * 2. Subblock = D_AsrcVars[2] = 0
+ * 3. DeltaAlpha = D_AsrcVars[3] =
+ * (round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2
+ * 4. MinusDeltaAlpha = D_AsrcVars[4] =
+ * (-round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2
+ * 5. OneMinusEpsilon = D_AsrcVars[5] = 1 - DeltaAlpha/2
+ * 6. AlphaCurrent = 0x000020 (CMEM), initial value of Alpha parameter
+ * 7. BetaCurrent = 0x3fffe0 (CMEM), initial value of Beta parameter
+ * AlphaCurrent + BetaCurrent = 1 (=0x400000 in CMEM = 2^20 << 2)
+ * 8. drift_ASRC = 0 & drift_io = 0
+ * 9. SMEM for ASRC_BT_UL_Coefs pointer
+ * 10. CMEM for ASRC_BT_UL_Coefs pointer
+ * ASRC_BT_UL_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/
+ * C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1
+ * 11. SMEM for XinASRC_BT_UL pointer
+ * 12. CMEM for XinASRC_BT_UL pointer
+ * XinASRC_BT_UL = S_XinASRC_BT_UL_ADDR/S_XinASRC_BT_UL_sizeof/0/1/0/0/0/0
+ * 13. SMEM for IO_BT_UL_ASRC pointer
+ * 14. CMEM for IO_BT_UL_ASRC pointer
+ * IO_BT_UL_ASRC = S_XinASRC_BT_UL_ADDR/S_XinASRC_BT_UL_sizeof/
+ * ASRC_BT_UL_FIR_L+ASRC_margin/1/0/0/0/0
+ */
+void abe_init_asrc_bt_ul(s32 dppm)
+{
+ s32 el[45];
+ s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr;
+ u32 i = 0;
+ u32 n_fifo_el = 42;
+ temp0 = 0;
+ temp1 = 1;
+ /* 1. DriftSign = D_AsrcVars[1] = 1 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_BT_UL_ADDR + (1 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm >= 0) {
+ el[i + 1] = 1;
+ adppm = dppm;
+ } else {
+ el[i + 1] = -1;
+ adppm = (-1 * dppm);
+ }
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ dtemp = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L);
+ /* 2. Subblock = D_AsrcVars[2] = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_BT_UL_ADDR + (2 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 3. DeltaAlpha = D_AsrcVars[3] = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_BT_UL_ADDR + (3 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm == 0)
+ el[i + 1] = 0;
+ else
+ el[i + 1] = dtemp << 2;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_BT_UL_ADDR + (4 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm == 0)
+ el[i + 1] = 0;
+ else
+ el[i + 1] = (-dtemp) << 2;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /*5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_BT_UL_ADDR + (5 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm == 0)
+ el[i + 1] = 0x00400000;
+ else
+ el[i + 1] = (0x00100000 - (dtemp / 2)) << 2;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 6. AlphaCurrent = 0x000020 (CMEM) */
+ mem_tag = ABE_CMEM;
+ mem_addr = OMAP_ABE_C_ALPHACURRENT_BT_UL_ADDR;
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = 0x00000020;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 7. BetaCurrent = 0x3fffe0 (CMEM) */
+ mem_tag = ABE_CMEM;
+ mem_addr = OMAP_ABE_C_BETACURRENT_BT_UL_ADDR;
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = 0x003fffe0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 8. drift_ASRC = 0 & drift_io = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_IODESCR_ADDR + (OMAP_ABE_BT_VX_UL_PORT * sizeof(struct ABE_SIODescriptor))
+ + drift_asrc_;
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 9. SMEM for ASRC_BT_UL_Coefs pointer */
+ /* ASRC_BT_UL_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/
+ C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
+ mem_tag = ABE_SMEM;
+ mem_addr = ASRC_BT_UL_Coefs_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_C_COEFASRC16_VX_ADDR >> 2;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_C_COEFASRC16_VX_SIZE >> 2);
+ el[i + 2] = OMAP_ABE_C_COEFASRC15_VX_ADDR >> 2;
+ el[i + 2] = (el[i + 2] << 8) + (OMAP_ABE_C_COEFASRC15_VX_SIZE >> 2);
+ i = i + 3;
+ /* 10. CMEM for ASRC_BT_UL_Coefs pointer */
+ /* ASRC_BT_UL_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/
+ C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
+ mem_tag = ABE_CMEM;
+ mem_addr = ASRC_BT_UL_Coefs_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp1;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 11. SMEM for XinASRC_BT_UL pointer */
+ /* XinASRC_BT_UL = S_XinASRC_BT_UL_ADDR/S_XinASRC_BT_UL_sizeof/0/1/
+ 0/0/0/0 */
+ mem_tag = ABE_SMEM;
+ mem_addr = XinASRC_BT_UL_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_S_XINASRC_BT_UL_ADDR >> 3;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_S_XINASRC_BT_UL_SIZE >> 3);
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 12. CMEM for XinASRC_BT_UL pointer */
+ /* XinASRC_BT_UL = S_XinASRC_BT_UL_ADDR/S_XinASRC_BT_UL_sizeof/0/1/
+ 0/0/0/0 */
+ mem_tag = ABE_CMEM;
+ mem_addr = XinASRC_BT_UL_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 13. SMEM for IO_BT_UL_ASRC pointer */
+ /* IO_BT_UL_ASRC = S_XinASRC_BT_UL_ADDR/S_XinASRC_BT_UL_sizeof/
+ ASRC_BT_UL_FIR_L+ASRC_margin/1/0/0/0/0 */
+ mem_tag = ABE_SMEM;
+ mem_addr = IO_BT_UL_ASRC_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_S_XINASRC_BT_UL_ADDR >> 3;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_S_XINASRC_BT_UL_SIZE >> 3);
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 14. CMEM for IO_BT_UL_ASRC pointer */
+ /* IO_BT_UL_ASRC = S_XinASRC_BT_UL_ADDR/S_XinASRC_BT_UL_sizeof/
+ ASRC_BT_UL_FIR_L+ASRC_margin/1/0/0/0/0 */
+ mem_tag = ABE_CMEM;
+ mem_addr = IO_BT_UL_ASRC_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = ((ASRC_BT_UL_FIR_L + ASRC_margin) << 16) + (temp1 << 12)
+ + (temp0 << 4) + temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ abe_write_fifo(ABE_DMEM, OMAP_ABE_D_FWMEMINITDESCR_ADDR, (u32 *) &el[0],
+ n_fifo_el);
+}
+/**
+ * abe_init_asrc_bt_dl
+ *
+ * Initialize the following ASRC BT_DL parameters :
+ * 1. DriftSign = D_AsrcVars[1] = 1 or -1
+ * 2. Subblock = D_AsrcVars[2] = 0
+ * 3. DeltaAlpha = D_AsrcVars[3] =
+ * (round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2
+ * 4. MinusDeltaAlpha = D_AsrcVars[4] =
+ * (-round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2
+ * 5. OneMinusEpsilon = D_AsrcVars[5] = 1 - DeltaAlpha/2
+ * 6. AlphaCurrent = 0x000020 (CMEM), initial value of Alpha parameter
+ * 7. BetaCurrent = 0x3fffe0 (CMEM), initial value of Beta parameter
+ * AlphaCurrent + BetaCurrent = 1 (=0x400000 in CMEM = 2^20 << 2)
+ * 8. drift_ASRC = 0 & drift_io = 0
+ * 9. SMEM for ASRC_BT_DL_Coefs pointer
+ * 10. CMEM for ASRC_BT_DL_Coefs pointer
+ * ASRC_BT_DL_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/
+ * C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1
+ * 11. SMEM for XinASRC_BT_DL pointer
+ * 12. CMEM for XinASRC_BT_DL pointer
+ * XinASRC_BT_DL = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/0/1/0/0/0/0
+ * 13. SMEM for DL_48_8_DEC pointer
+ * 14. CMEM for DL_48_8_DEC pointer
+ * DL_48_8_DEC = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/
+ * ASRC_BT_DL_FIR_L+ASRC_margin/1/0/0/0/0
+ * 15. SMEM for DL_48_16_DEC pointer
+ * 16. CMEM for DL_48_16_DEC pointer
+ * DL_48_16_DEC = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/
+ * ASRC_BT_DL_FIR_L+ASRC_margin/1/0/0/0/0
+ */
+void abe_init_asrc_bt_dl(s32 dppm)
+{
+ s32 el[51];
+ s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr;
+ u32 i = 0;
+ u32 n_fifo_el = 48;
+ temp0 = 0;
+ temp1 = 1;
+ /* 1. DriftSign = D_AsrcVars[1] = 1 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_BT_DL_ADDR + (1 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm >= 0) {
+ el[i + 1] = 1;
+ adppm = dppm;
+ } else {
+ el[i + 1] = -1;
+ adppm = (-1 * dppm);
+ }
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ dtemp = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L);
+ /* 2. Subblock = D_AsrcVars[2] = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_BT_DL_ADDR + (2 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 3. DeltaAlpha = D_AsrcVars[3] = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_BT_DL_ADDR + (3 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm == 0)
+ el[i + 1] = 0;
+ else
+ el[i + 1] = dtemp << 2;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_BT_DL_ADDR + (4 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm == 0)
+ el[i + 1] = 0;
+ else
+ el[i + 1] = (-dtemp) << 2;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_ASRCVARS_BT_DL_ADDR + (5 * sizeof(s32));
+ el[i] = (mem_tag << 16) + mem_addr;
+ if (dppm == 0)
+ el[i + 1] = 0x00400000;
+ else
+ el[i + 1] = (0x00100000 - (dtemp / 2)) << 2;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 6. AlphaCurrent = 0x000020 (CMEM) */
+ mem_tag = ABE_CMEM;
+ mem_addr = OMAP_ABE_C_ALPHACURRENT_BT_DL_ADDR;
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = 0x00000020;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 7. BetaCurrent = 0x3fffe0 (CMEM) */
+ mem_tag = ABE_CMEM;
+ mem_addr = OMAP_ABE_C_BETACURRENT_BT_DL_ADDR;
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = 0x003fffe0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 8. drift_ASRC = 0 & drift_io = 0 */
+ mem_tag = ABE_DMEM;
+ mem_addr = OMAP_ABE_D_IODESCR_ADDR + (OMAP_ABE_BT_VX_DL_PORT * sizeof(struct ABE_SIODescriptor))
+ + drift_asrc_;
+ el[i] = (mem_tag << 16) + mem_addr;
+ el[i + 1] = temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 9. SMEM for ASRC_BT_DL_Coefs pointer */
+ /* ASRC_BT_DL_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/
+ C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
+ mem_tag = ABE_SMEM;
+ mem_addr = ASRC_BT_DL_Coefs_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_C_COEFASRC16_VX_ADDR >> 2;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_C_COEFASRC16_VX_SIZE >> 2);
+ el[i + 2] = OMAP_ABE_C_COEFASRC15_VX_ADDR >> 2;
+ el[i + 2] = (el[i + 2] << 8) + (OMAP_ABE_C_COEFASRC15_VX_SIZE >> 2);
+ i = i + 3;
+ /* 10. CMEM for ASRC_BT_DL_Coefs pointer */
+ /* ASRC_BT_DL_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/
+ C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
+ mem_tag = ABE_CMEM;
+ mem_addr = ASRC_BT_DL_Coefs_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp1;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 11. SMEM for XinASRC_BT_DL pointer */
+ /* XinASRC_BT_DL =
+ S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/0/1/0/0/0/0 */
+ mem_tag = ABE_SMEM;
+ mem_addr = XinASRC_BT_DL_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_S_XINASRC_BT_DL_ADDR >> 3;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_S_XINASRC_BT_DL_SIZE >> 3);
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 12. CMEM for XinASRC_BT_DL pointer */
+ /* XinASRC_BT_DL =
+ S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/0/1/0/0/0/0 */
+ mem_tag = ABE_CMEM;
+ mem_addr = XinASRC_BT_DL_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 13. SMEM for DL_48_8_DEC pointer */
+ /* DL_48_8_DEC = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/
+ ASRC_BT_DL_FIR_L+ASRC_margin/1/0/0/0/0 */
+ mem_tag = ABE_SMEM;
+ mem_addr = DL_48_8_DEC_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_S_XINASRC_BT_DL_ADDR >> 3;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_S_XINASRC_BT_DL_SIZE >> 3);
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 14. CMEM for DL_48_8_DEC pointer */
+ /* DL_48_8_DEC = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/
+ ASRC_BT_DL_FIR_L+ASRC_margin/1/0/0/0/0 */
+ mem_tag = ABE_CMEM;
+ mem_addr = DL_48_8_DEC_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = ((ASRC_BT_DL_FIR_L + ASRC_margin) << 16) + (temp1 << 12)
+ + (temp0 << 4) + temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 15. SMEM for DL_48_16_DEC pointer */
+ /* DL_48_16_DEC = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/
+ ASRC_BT_DL_FIR_L+ASRC_margin/1/0/0/0/0 */
+ mem_tag = ABE_SMEM;
+ mem_addr = DL_48_16_DEC_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ el[i + 1] = OMAP_ABE_S_XINASRC_BT_DL_ADDR >> 3;
+ el[i + 1] = (el[i + 1] << 8) + (OMAP_ABE_S_XINASRC_BT_DL_SIZE >> 3);
+ el[i + 2] = temp0;
+ i = i + 3;
+ /* 16. CMEM for DL_48_16_DEC pointer */
+ /* DL_48_16_DEC = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/
+ ASRC_BT_DL_FIR_L+ASRC_margin/1/0/0/0/0 */
+ mem_tag = ABE_CMEM;
+ mem_addr = DL_48_16_DEC_labelID;
+ el[i] = (mem_tag << 16) + (mem_addr << 2);
+ /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
+ el[i + 1] = ((ASRC_BT_DL_FIR_L + ASRC_margin) << 16) + (temp1 << 12)
+ + (temp0 << 4) + temp0;
+ /* dummy field */
+ el[i + 2] = temp0;
+ abe_write_fifo(ABE_DMEM, OMAP_ABE_D_FWMEMINITDESCR_ADDR, (u32 *) &el[0],
+ n_fifo_el);
+}
diff --git a/sound/soc/omap/abe/abe_cm_addr.h b/sound/soc/omap/abe/abe_cm_addr.h
new file mode 100644
index 0000000..29f7f27
--- /dev/null
+++ b/sound/soc/omap/abe/abe_cm_addr.h
@@ -0,0 +1,317 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+#define OMAP_ABE_INIT_CM_ADDR 0x0
+#define OMAP_ABE_INIT_CM_SIZE 0x4DC
+
+#define OMAP_ABE_C_DATA_LSB_2_ADDR 0x4DC
+#define OMAP_ABE_C_DATA_LSB_2_SIZE 0x4
+
+#define OMAP_ABE_C_1_ALPHA_ADDR 0x4E0
+#define OMAP_ABE_C_1_ALPHA_SIZE 0x48
+
+#define OMAP_ABE_C_ALPHA_ADDR 0x528
+#define OMAP_ABE_C_ALPHA_SIZE 0x48
+
+#define OMAP_ABE_C_GAINSWRAMP_ADDR 0x570
+#define OMAP_ABE_C_GAINSWRAMP_SIZE 0x38
+
+#define OMAP_ABE_C_GAINS_DL1M_ADDR 0x5A8
+#define OMAP_ABE_C_GAINS_DL1M_SIZE 0x10
+
+#define OMAP_ABE_C_GAINS_DL2M_ADDR 0x5B8
+#define OMAP_ABE_C_GAINS_DL2M_SIZE 0x10
+
+#define OMAP_ABE_C_GAINS_ECHOM_ADDR 0x5C8
+#define OMAP_ABE_C_GAINS_ECHOM_SIZE 0x8
+
+#define OMAP_ABE_C_GAINS_SDTM_ADDR 0x5D0
+#define OMAP_ABE_C_GAINS_SDTM_SIZE 0x8
+
+#define OMAP_ABE_C_GAINS_VXRECM_ADDR 0x5D8
+#define OMAP_ABE_C_GAINS_VXRECM_SIZE 0x10
+
+#define OMAP_ABE_C_GAINS_ULM_ADDR 0x5E8
+#define OMAP_ABE_C_GAINS_ULM_SIZE 0x10
+
+#define OMAP_ABE_C_GAINS_BTUL_ADDR 0x5F8
+#define OMAP_ABE_C_GAINS_BTUL_SIZE 0x8
+
+#define OMAP_ABE_C_SDT_COEFS_ADDR 0x600
+#define OMAP_ABE_C_SDT_COEFS_SIZE 0x24
+
+#define OMAP_ABE_C_COEFASRC1_VX_ADDR 0x624
+#define OMAP_ABE_C_COEFASRC1_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_COEFASRC2_VX_ADDR 0x670
+#define OMAP_ABE_C_COEFASRC2_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_COEFASRC3_VX_ADDR 0x6BC
+#define OMAP_ABE_C_COEFASRC3_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_COEFASRC4_VX_ADDR 0x708
+#define OMAP_ABE_C_COEFASRC4_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_COEFASRC5_VX_ADDR 0x754
+#define OMAP_ABE_C_COEFASRC5_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_COEFASRC6_VX_ADDR 0x7A0
+#define OMAP_ABE_C_COEFASRC6_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_COEFASRC7_VX_ADDR 0x7EC
+#define OMAP_ABE_C_COEFASRC7_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_COEFASRC8_VX_ADDR 0x838
+#define OMAP_ABE_C_COEFASRC8_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_COEFASRC9_VX_ADDR 0x884
+#define OMAP_ABE_C_COEFASRC9_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_COEFASRC10_VX_ADDR 0x8D0
+#define OMAP_ABE_C_COEFASRC10_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_COEFASRC11_VX_ADDR 0x91C
+#define OMAP_ABE_C_COEFASRC11_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_COEFASRC12_VX_ADDR 0x968
+#define OMAP_ABE_C_COEFASRC12_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_COEFASRC13_VX_ADDR 0x9B4
+#define OMAP_ABE_C_COEFASRC13_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_COEFASRC14_VX_ADDR 0xA00
+#define OMAP_ABE_C_COEFASRC14_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_COEFASRC15_VX_ADDR 0xA4C
+#define OMAP_ABE_C_COEFASRC15_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_COEFASRC16_VX_ADDR 0xA98
+#define OMAP_ABE_C_COEFASRC16_VX_SIZE 0x4C
+
+#define OMAP_ABE_C_ALPHACURRENT_UL_VX_ADDR 0xAE4
+#define OMAP_ABE_C_ALPHACURRENT_UL_VX_SIZE 0x4
+
+#define OMAP_ABE_C_BETACURRENT_UL_VX_ADDR 0xAE8
+#define OMAP_ABE_C_BETACURRENT_UL_VX_SIZE 0x4
+
+#define OMAP_ABE_C_ALPHACURRENT_DL_VX_ADDR 0xAEC
+#define OMAP_ABE_C_ALPHACURRENT_DL_VX_SIZE 0x4
+
+#define OMAP_ABE_C_BETACURRENT_DL_VX_ADDR 0xAF0
+#define OMAP_ABE_C_BETACURRENT_DL_VX_SIZE 0x4
+
+#define OMAP_ABE_C_COEFASRC1_MM_ADDR 0xAF4
+#define OMAP_ABE_C_COEFASRC1_MM_SIZE 0x48
+
+#define OMAP_ABE_C_COEFASRC2_MM_ADDR 0xB3C
+#define OMAP_ABE_C_COEFASRC2_MM_SIZE 0x48
+
+#define OMAP_ABE_C_COEFASRC3_MM_ADDR 0xB84
+#define OMAP_ABE_C_COEFASRC3_MM_SIZE 0x48
+
+#define OMAP_ABE_C_COEFASRC4_MM_ADDR 0xBCC
+#define OMAP_ABE_C_COEFASRC4_MM_SIZE 0x48
+
+#define OMAP_ABE_C_COEFASRC5_MM_ADDR 0xC14
+#define OMAP_ABE_C_COEFASRC5_MM_SIZE 0x48
+
+#define OMAP_ABE_C_COEFASRC6_MM_ADDR 0xC5C
+#define OMAP_ABE_C_COEFASRC6_MM_SIZE 0x48
+
+#define OMAP_ABE_C_COEFASRC7_MM_ADDR 0xCA4
+#define OMAP_ABE_C_COEFASRC7_MM_SIZE 0x48
+
+#define OMAP_ABE_C_COEFASRC8_MM_ADDR 0xCEC
+#define OMAP_ABE_C_COEFASRC8_MM_SIZE 0x48
+
+#define OMAP_ABE_C_COEFASRC9_MM_ADDR 0xD34
+#define OMAP_ABE_C_COEFASRC9_MM_SIZE 0x48
+
+#define OMAP_ABE_C_COEFASRC10_MM_ADDR 0xD7C
+#define OMAP_ABE_C_COEFASRC10_MM_SIZE 0x48
+
+#define OMAP_ABE_C_COEFASRC11_MM_ADDR 0xDC4
+#define OMAP_ABE_C_COEFASRC11_MM_SIZE 0x48
+
+#define OMAP_ABE_C_COEFASRC12_MM_ADDR 0xE0C
+#define OMAP_ABE_C_COEFASRC12_MM_SIZE 0x48
+
+#define OMAP_ABE_C_COEFASRC13_MM_ADDR 0xE54
+#define OMAP_ABE_C_COEFASRC13_MM_SIZE 0x48
+
+#define OMAP_ABE_C_COEFASRC14_MM_ADDR 0xE9C
+#define OMAP_ABE_C_COEFASRC14_MM_SIZE 0x48
+
+#define OMAP_ABE_C_COEFASRC15_MM_ADDR 0xEE4
+#define OMAP_ABE_C_COEFASRC15_MM_SIZE 0x48
+
+#define OMAP_ABE_C_COEFASRC16_MM_ADDR 0xF2C
+#define OMAP_ABE_C_COEFASRC16_MM_SIZE 0x48
+
+#define OMAP_ABE_C_ALPHACURRENT_MM_EXT_IN_ADDR 0xF74
+#define OMAP_ABE_C_ALPHACURRENT_MM_EXT_IN_SIZE 0x4
+
+#define OMAP_ABE_C_BETACURRENT_MM_EXT_IN_ADDR 0xF78
+#define OMAP_ABE_C_BETACURRENT_MM_EXT_IN_SIZE 0x4
+
+#define OMAP_ABE_C_DL2_L_COEFS_ADDR 0xF7C
+#define OMAP_ABE_C_DL2_L_COEFS_SIZE 0x64
+
+#define OMAP_ABE_C_DL2_R_COEFS_ADDR 0xFE0
+#define OMAP_ABE_C_DL2_R_COEFS_SIZE 0x64
+
+#define OMAP_ABE_C_DL1_COEFS_ADDR 0x1044
+#define OMAP_ABE_C_DL1_COEFS_SIZE 0x64
+
+#define OMAP_ABE_C_SRC_3_LP_COEFS_ADDR 0x10A8
+#define OMAP_ABE_C_SRC_3_LP_COEFS_SIZE 0x2C
+
+#define OMAP_ABE_C_SRC_3_LP_GAIN_COEFS_ADDR 0x10D4
+#define OMAP_ABE_C_SRC_3_LP_GAIN_COEFS_SIZE 0x2C
+
+#define OMAP_ABE_C_SRC_3_HP_COEFS_ADDR 0x1100
+#define OMAP_ABE_C_SRC_3_HP_COEFS_SIZE 0x14
+
+#define OMAP_ABE_C_SRC_6_LP_COEFS_ADDR 0x1114
+#define OMAP_ABE_C_SRC_6_LP_COEFS_SIZE 0x2C
+
+#define OMAP_ABE_C_SRC_6_LP_GAIN_COEFS_ADDR 0x1140
+#define OMAP_ABE_C_SRC_6_LP_GAIN_COEFS_SIZE 0x2C
+
+#define OMAP_ABE_C_SRC_6_HP_COEFS_ADDR 0x116C
+#define OMAP_ABE_C_SRC_6_HP_COEFS_SIZE 0x1C
+
+#define OMAP_ABE_C_APS_DL1_COEFFS1_ADDR 0x1188
+#define OMAP_ABE_C_APS_DL1_COEFFS1_SIZE 0x24
+
+#define OMAP_ABE_C_APS_DL1_M_COEFFS2_ADDR 0x11AC
+#define OMAP_ABE_C_APS_DL1_M_COEFFS2_SIZE 0xC
+
+#define OMAP_ABE_C_APS_DL1_C_COEFFS2_ADDR 0x11B8
+#define OMAP_ABE_C_APS_DL1_C_COEFFS2_SIZE 0xC
+
+#define OMAP_ABE_C_APS_DL2_L_COEFFS1_ADDR 0x11C4
+#define OMAP_ABE_C_APS_DL2_L_COEFFS1_SIZE 0x24
+
+#define OMAP_ABE_C_APS_DL2_R_COEFFS1_ADDR 0x11E8
+#define OMAP_ABE_C_APS_DL2_R_COEFFS1_SIZE 0x24
+
+#define OMAP_ABE_C_APS_DL2_L_M_COEFFS2_ADDR 0x120C
+#define OMAP_ABE_C_APS_DL2_L_M_COEFFS2_SIZE 0xC
+
+#define OMAP_ABE_C_APS_DL2_R_M_COEFFS2_ADDR 0x1218
+#define OMAP_ABE_C_APS_DL2_R_M_COEFFS2_SIZE 0xC
+
+#define OMAP_ABE_C_APS_DL2_L_C_COEFFS2_ADDR 0x1224
+#define OMAP_ABE_C_APS_DL2_L_C_COEFFS2_SIZE 0xC
+
+#define OMAP_ABE_C_APS_DL2_R_C_COEFFS2_ADDR 0x1230
+#define OMAP_ABE_C_APS_DL2_R_C_COEFFS2_SIZE 0xC
+
+#define OMAP_ABE_C_ALPHACURRENT_ECHO_REF_ADDR 0x123C
+#define OMAP_ABE_C_ALPHACURRENT_ECHO_REF_SIZE 0x4
+
+#define OMAP_ABE_C_BETACURRENT_ECHO_REF_ADDR 0x1240
+#define OMAP_ABE_C_BETACURRENT_ECHO_REF_SIZE 0x4
+
+#define OMAP_ABE_C_APS_DL1_EQ_ADDR 0x1244
+#define OMAP_ABE_C_APS_DL1_EQ_SIZE 0x24
+
+#define OMAP_ABE_C_APS_DL2_L_EQ_ADDR 0x1268
+#define OMAP_ABE_C_APS_DL2_L_EQ_SIZE 0x24
+
+#define OMAP_ABE_C_APS_DL2_R_EQ_ADDR 0x128C
+#define OMAP_ABE_C_APS_DL2_R_EQ_SIZE 0x24
+
+#define OMAP_ABE_C_VIBRA2_CONSTS_ADDR 0x12B0
+#define OMAP_ABE_C_VIBRA2_CONSTS_SIZE 0x10
+
+#define OMAP_ABE_C_VIBRA1_COEFFS_ADDR 0x12C0
+#define OMAP_ABE_C_VIBRA1_COEFFS_SIZE 0x2C
+
+#define OMAP_ABE_C_48_96_LP_COEFS_ADDR 0x12EC
+#define OMAP_ABE_C_48_96_LP_COEFS_SIZE 0x3C
+
+#define OMAP_ABE_C_96_48_AMIC_COEFS_ADDR 0x1328
+#define OMAP_ABE_C_96_48_AMIC_COEFS_SIZE 0x4C
+
+#define OMAP_ABE_C_96_48_DMIC_COEFS_ADDR 0x1374
+#define OMAP_ABE_C_96_48_DMIC_COEFS_SIZE 0x4C
+
+#define OMAP_ABE_C_INPUT_SCALE_ADDR 0x13C0
+#define OMAP_ABE_C_INPUT_SCALE_SIZE 0x4
+
+#define OMAP_ABE_C_OUTPUT_SCALE_ADDR 0x13C4
+#define OMAP_ABE_C_OUTPUT_SCALE_SIZE 0x4
+
+#define OMAP_ABE_C_MUTE_SCALING_ADDR 0x13C8
+#define OMAP_ABE_C_MUTE_SCALING_SIZE 0x4
+
+#define OMAP_ABE_C_GAINS_0DB_ADDR 0x13CC
+#define OMAP_ABE_C_GAINS_0DB_SIZE 0x8
+
+#define OMAP_ABE_C_ALPHACURRENT_BT_UL_ADDR 0x13D4
+#define OMAP_ABE_C_ALPHACURRENT_BT_UL_SIZE 0x4
+
+#define OMAP_ABE_C_BETACURRENT_BT_UL_ADDR 0x13D8
+#define OMAP_ABE_C_BETACURRENT_BT_UL_SIZE 0x4
+
+#define OMAP_ABE_C_ALPHACURRENT_BT_DL_ADDR 0x13DC
+#define OMAP_ABE_C_ALPHACURRENT_BT_DL_SIZE 0x4
+
+#define OMAP_ABE_C_BETACURRENT_BT_DL_ADDR 0x13E0
+#define OMAP_ABE_C_BETACURRENT_BT_DL_SIZE 0x4
diff --git a/sound/soc/omap/abe/abe_core.c b/sound/soc/omap/abe/abe_core.c
new file mode 100644
index 0000000..da24b7a
--- /dev/null
+++ b/sound/soc/omap/abe/abe_core.c
@@ -0,0 +1,574 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include "abe_dbg.h"
+#include "abe.h"
+#include "abe_gain.h"
+#include "abe_aess.h"
+#include "abe_port.h"
+#include "abe_mem.h"
+
+#define OMAP_ABE_IRQ_FIFO_MASK ((OMAP_ABE_D_MCUIRQFIFO_SIZE >> 2) - 1)
+
+void abe_init_asrc_vx_dl(s32 dppm);
+void abe_init_asrc_vx_ul(s32 dppm);
+void abe_init_asrc_mm_ext_in(s32 dppm);
+void abe_init_asrc_bt_ul(s32 dppm);
+void abe_init_asrc_bt_dl(s32 dppm);
+
+void abe_irq_aps(u32 aps_info);
+void abe_irq_ping_pong(void);
+void abe_irq_check_for_sequences(u32 seq_info);
+extern u32 abe_size_pingpong;
+extern u32 abe_base_address_pingpong[];
+
+void abe_add_subroutine(u32 *id, abe_subroutine2 f, u32 nparam, u32 *params);
+
+
+/**
+ * abe_omap_abe_reset_hal - reset the ABE/HAL
+ * @abe: Pointer on abe handle
+ *
+ * Operations : reset the ABE by reloading the static variables and
+ * default AESS registers.
+ * Called after a PRCM cold-start reset of ABE
+ */
+int omap_abe_reset_hal(struct omap_abe *abe)
+{
+ u32 i;
+
+ omap_abe_dbg_reset(&abe->dbg);
+
+ _log(ABE_ID_RESET_HAL, 0, 0, 0);
+
+ /* IRQ & DBG circular read pointer in DMEM */
+ abe->irq_dbg_read_ptr = 0;
+
+ /* default = disable the mixer's adaptive gain control */
+ omap_abe_use_compensated_gain(abe, 0);
+
+ /* reset the default gain values */
+ for (i = 0; i < MAX_NBGAIN_CMEM; i++) {
+ abe->muted_gains_indicator[i] = 0;
+ abe->desired_gains_decibel[i] = (u32) GAIN_MUTE;
+ abe->desired_gains_linear[i] = 0;
+ abe->desired_ramp_delay_ms[i] = 0;
+ abe->muted_gains_decibel[i] = (u32) GAIN_TOOLOW;
+ }
+ omap_abe_hw_configuration(abe);
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_reset_hal);
+
+/**
+ * omap_abe_wakeup - Wakeup ABE
+ * @abe: Pointer on abe handle
+ *
+ * Wakeup ABE in case of retention
+ */
+int omap_abe_wakeup(struct omap_abe *abe)
+{
+ /* Restart event generator */
+ omap_abe_write_event_generator(abe, EVENT_TIMER);
+
+ /* reconfigure DMA Req and MCU Irq visibility */
+ omap_abe_hw_configuration(abe);
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_wakeup);
+
+/**
+ * abe_monitoring
+ *
+ * checks the internal status of ABE and HAL
+ */
+void abe_monitoring(void)
+{
+}
+
+/**
+ * omap_abe_irq_processing - Process ABE interrupt
+ * @abe: Pointer on abe handle
+ *
+ * This subroutine is call upon reception of "MA_IRQ_99 ABE_MPU_IRQ" Audio
+ * back-end interrupt. This subroutine will check the ATC Hrdware, the
+ * IRQ_FIFO from the AE and act accordingly. Some IRQ source are originated
+ * for the delivery of "end of time sequenced tasks" notifications, some are
+ * originated from the Ping-Pong protocols, some are generated from
+ * the embedded debugger when the firmware stops on programmable break-points,
+ * etc ...
+ */
+int omap_abe_irq_processing(struct omap_abe *abe)
+{
+ u32 abe_irq_dbg_write_ptr, i, cmem_src, sm_cm;
+ abe_irq_data_t IRQ_data;
+
+ _log(ABE_ID_IRQ_PROCESSING, 0, 0, 0);
+
+ /* extract the write pointer index from CMEM memory (INITPTR format) */
+ /* CMEM address of the write pointer in bytes */
+ cmem_src = MCU_IRQ_FIFO_ptr_labelID << 2;
+ omap_abe_mem_read(abe, OMAP_ABE_CMEM, cmem_src,
+ &sm_cm, sizeof(abe_irq_dbg_write_ptr));
+ /* AESS left-pointer index located on MSBs */
+ abe_irq_dbg_write_ptr = sm_cm >> 16;
+ abe_irq_dbg_write_ptr &= 0xFF;
+ /* loop on the IRQ FIFO content */
+ for (i = 0; i < OMAP_ABE_D_MCUIRQFIFO_SIZE; i++) {
+ /* stop when the FIFO is empty */
+ if (abe_irq_dbg_write_ptr == abe->irq_dbg_read_ptr)
+ break;
+ /* read the IRQ/DBG FIFO */
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM,
+ (OMAP_ABE_D_MCUIRQFIFO_ADDR +
+ (abe->irq_dbg_read_ptr << 2)),
+ (u32 *) &IRQ_data, sizeof(IRQ_data));
+ abe->irq_dbg_read_ptr = (abe->irq_dbg_read_ptr + 1) & OMAP_ABE_IRQ_FIFO_MASK;
+ /* select the source of the interrupt */
+ switch (IRQ_data.tag) {
+ case IRQtag_APS:
+ _log(ABE_ID_IRQ_PROCESSING, IRQ_data.data, 0, 1);
+ abe_irq_aps(IRQ_data.data);
+ break;
+ case IRQtag_PP:
+ _log(ABE_ID_IRQ_PROCESSING, 0, 0, 2);
+ abe_irq_ping_pong();
+ break;
+ case IRQtag_COUNT:
+ _log(ABE_ID_IRQ_PROCESSING, IRQ_data.data, 0, 3);
+ abe_irq_check_for_sequences(IRQ_data.data);
+ break;
+ default:
+ break;
+ }
+ }
+ abe_monitoring();
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_irq_processing);
+
+/**
+ * oamp_abe_set_ping_pong_buffer
+ * @abe: Pointer on abe handle
+ * @port: ABE port ID
+ * @n_bytes: Size of Ping/Pong buffer
+ *
+ * Updates the next ping-pong buffer with "size" bytes copied from the
+ * host processor. This API notifies the FW that the data transfer is done.
+ */
+int omap_abe_set_ping_pong_buffer(struct omap_abe *abe, u32 port, u32 n_bytes)
+{
+ u32 sio_pp_desc_address, struct_offset, n_samples, datasize,
+ base_and_size, *src;
+ struct ABE_SPingPongDescriptor desc_pp;
+
+ _log(ABE_ID_SET_PING_PONG_BUFFER, port, n_bytes, n_bytes >> 8);
+
+ /* ping_pong is only supported on MM_DL */
+ if (port != OMAP_ABE_MM_DL_PORT) {
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_API,
+ ABE_PARAMETER_ERROR);
+ }
+ /* translates the number of bytes in samples */
+ /* data size in DMEM words */
+ datasize = omap_abe_dma_port_iter_factor((struct omap_abe_data_format *)&((abe_port[port]).format));
+ /* data size in bytes */
+ datasize = datasize << 2;
+ n_samples = n_bytes / datasize;
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM, OMAP_ABE_D_PINGPONGDESC_ADDR,
+ (u32 *) &desc_pp, sizeof(desc_pp));
+ /*
+ * read the port SIO descriptor and extract the current pointer
+ * address after reading the counter
+ */
+ if ((desc_pp.counter & 0x1) == 0) {
+ struct_offset = (u32) &(desc_pp.nextbuff0_BaseAddr) -
+ (u32) &(desc_pp);
+ base_and_size = desc_pp.nextbuff0_BaseAddr;
+ } else {
+ struct_offset = (u32) &(desc_pp.nextbuff1_BaseAddr) -
+ (u32) &(desc_pp);
+ base_and_size = desc_pp.nextbuff1_BaseAddr;
+ }
+ base_and_size = (base_and_size & 0xFFFFL) + (n_samples << 16);
+ sio_pp_desc_address = OMAP_ABE_D_PINGPONGDESC_ADDR + struct_offset;
+ src = &base_and_size;
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM, sio_pp_desc_address,
+ (u32 *) &base_and_size, sizeof(u32));
+
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_set_ping_pong_buffer);
+
+/**
+ * omap_abe_read_next_ping_pong_buffer
+ * @abe: Pointer on abe handle
+ * @port: ABE portID
+ * @p: Next buffer address (pointer)
+ * @n: Next buffer size (pointer)
+ *
+ * Tell the next base address of the next ping_pong Buffer and its size
+ */
+int omap_abe_read_next_ping_pong_buffer(struct omap_abe *abe, u32 port, u32 *p, u32 *n)
+{
+ u32 sio_pp_desc_address;
+ struct ABE_SPingPongDescriptor desc_pp;
+
+ _log(ABE_ID_READ_NEXT_PING_PONG_BUFFER, port, 0, 0);
+
+ /* ping_pong is only supported on MM_DL */
+ if (port != OMAP_ABE_MM_DL_PORT) {
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_API,
+ ABE_PARAMETER_ERROR);
+ }
+ /* read the port SIO descriptor and extract the current pointer
+ address after reading the counter */
+ sio_pp_desc_address = OMAP_ABE_D_PINGPONGDESC_ADDR;
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM, sio_pp_desc_address,
+ (u32 *) &desc_pp, sizeof(struct ABE_SPingPongDescriptor));
+ if ((desc_pp.counter & 0x1) == 0) {
+ _log(ABE_ID_READ_NEXT_PING_PONG_BUFFER, port, 0, 0);
+ *p = desc_pp.nextbuff0_BaseAddr;
+ } else {
+ _log(ABE_ID_READ_NEXT_PING_PONG_BUFFER, port, 1, 0);
+ *p = desc_pp.nextbuff1_BaseAddr;
+ }
+ /* translates the number of samples in bytes */
+ *n = abe_size_pingpong;
+
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_read_next_ping_pong_buffer);
+
+/**
+ * omap_abe_init_ping_pong_buffer
+ * @abe: Pointer on abe handle
+ * @id: ABE port ID
+ * @size_bytes:size of the ping pong
+ * @n_buffers:number of buffers (2 = ping/pong)
+ * @p:returned address of the ping-pong list of base addresses
+ * (byte offset from DMEM start)
+ *
+ * Computes the base address of the ping_pong buffers
+ */
+int omap_abe_init_ping_pong_buffer(struct omap_abe *abe,
+ u32 id, u32 size_bytes, u32 n_buffers,
+ u32 *p)
+{
+ u32 i, dmem_addr;
+
+ _log(ABE_ID_INIT_PING_PONG_BUFFER, id, size_bytes, n_buffers);
+
+ /* ping_pong is supported in 2 buffers configuration right now but FW
+ is ready for ping/pong/pung/pang... */
+ if (id != OMAP_ABE_MM_DL_PORT || n_buffers > MAX_PINGPONG_BUFFERS) {
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_API,
+ ABE_PARAMETER_ERROR);
+ }
+ for (i = 0; i < n_buffers; i++) {
+ dmem_addr = OMAP_ABE_D_PING_ADDR + (i * size_bytes);
+ /* base addresses of the ping pong buffers in U8 unit */
+ abe_base_address_pingpong[i] = dmem_addr;
+ }
+ /* global data */
+ abe_size_pingpong = size_bytes;
+ *p = (u32) OMAP_ABE_D_PING_ADDR;
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_init_ping_pong_buffer);
+
+/**
+ * omap_abe_read_offset_from_ping_buffer
+ * @abe: Pointer on abe handle
+ * @id: ABE port ID
+ * @n: returned address of the offset
+ * from the ping buffer start address (in samples)
+ *
+ * Computes the current firmware ping pong read pointer location,
+ * expressed in samples, as the offset from the start address of ping buffer.
+ */
+int omap_abe_read_offset_from_ping_buffer(struct omap_abe *abe,
+ u32 id, u32 *n)
+{
+ u32 sio_pp_desc_address;
+ struct ABE_SPingPongDescriptor desc_pp;
+
+ /* ping_pong is only supported on MM_DL */
+ if (OMAP_ABE_MM_DL_PORT != id) {
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_API,
+ ABE_PARAMETER_ERROR);
+ } else {
+ /* read the port SIO ping pong descriptor */
+ sio_pp_desc_address = OMAP_ABE_D_PINGPONGDESC_ADDR;
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM,
+ sio_pp_desc_address, (u32 *) &desc_pp,
+ sizeof(struct ABE_SPingPongDescriptor));
+ /* extract the current ping pong buffer read pointer based on
+ the value of the counter */
+ if ((desc_pp.counter & 0x1) == 0) {
+ /* the next is buffer0, hence the current is buffer1 */
+ switch (abe_port[OMAP_ABE_MM_DL_PORT].format.samp_format) {
+ case MONO_MSB:
+ case MONO_RSHIFTED_16:
+ case STEREO_16_16:
+ *n = abe_size_pingpong / 4 +
+ desc_pp.nextbuff1_Samples -
+ desc_pp.workbuff_Samples;
+ break;
+ case STEREO_MSB:
+ case STEREO_RSHIFTED_16:
+ *n = abe_size_pingpong / 8 +
+ desc_pp.nextbuff1_Samples -
+ desc_pp.workbuff_Samples;
+ break;
+ default:
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_API,
+ ABE_PARAMETER_ERROR);
+ break;
+ }
+ } else {
+ /* the next is buffer1, hence the current is buffer0 */
+ *n = desc_pp.nextbuff0_Samples -
+ desc_pp.workbuff_Samples;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_read_offset_from_ping_buffer);
+
+/**
+ * abe_set_router_configuration
+ * @Id: name of the router
+ * @Conf: id of the configuration
+ * @param: list of output index of the route
+ *
+ * The uplink router takes its input from DMIC (6 samples), AMIC (2 samples)
+ * and PORT1/2 (2 stereo ports). Each sample will be individually stored in
+ * an intermediate table of 10 elements.
+ *
+ * Example of router table parameter for voice uplink with phoenix microphones
+ *
+ * indexes 0 .. 9 = MM_UL description (digital MICs and MMEXTIN)
+ * DMIC1_L_labelID, DMIC1_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID,
+ * MM_EXT_IN_L_labelID, MM_EXT_IN_R_labelID, ZERO_labelID, ZERO_labelID,
+ * ZERO_labelID, ZERO_labelID,
+ * indexes 10 .. 11 = MM_UL2 description (recording on DMIC3)
+ * DMIC3_L_labelID, DMIC3_R_labelID,
+ * indexes 12 .. 13 = VX_UL description (VXUL based on PDMUL data)
+ * AMIC_L_labelID, AMIC_R_labelID,
+ * indexes 14 .. 15 = RESERVED (NULL)
+ * ZERO_labelID, ZERO_labelID,
+ */
+int omap_abe_set_router_configuration(struct omap_abe *abe,
+ u32 id, u32 k, u32 *param)
+{
+ _log(ABE_ID_SET_ROUTER_CONFIGURATION, id, (u32) param, (u32) param >> 8);
+
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_AUPLINKROUTING_ADDR,
+ param, OMAP_ABE_D_AUPLINKROUTING_SIZE);
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_set_router_configuration);
+
+/**
+ * abe_set_opp_processing - Set OPP mode for ABE Firmware
+ * @opp: OOPP mode
+ *
+ * New processing network and OPP:
+ * 0: Ultra Lowest power consumption audio player (no post-processing, no mixer)
+ * 1: OPP 25% (simple multimedia features, including low-power player)
+ * 2: OPP 50% (multimedia and voice calls)
+ * 3: OPP100% ( multimedia complex use-cases)
+ *
+ * Rearranges the FW task network to the corresponding OPP list of features.
+ * The corresponding AE ports are supposed to be set/reset accordingly before
+ * this switch.
+ *
+ */
+int omap_abe_set_opp_processing(struct omap_abe *abe, u32 opp)
+{
+ u32 dOppMode32, sio_desc_address;
+ struct ABE_SIODescriptor sio_desc;
+
+ _log(ABE_ID_SET_OPP_PROCESSING, opp, 0, 0);
+
+ switch (opp) {
+ case ABE_OPP25:
+ /* OPP25% */
+ dOppMode32 = DOPPMODE32_OPP25;
+ break;
+ case ABE_OPP50:
+ /* OPP50% */
+ dOppMode32 = DOPPMODE32_OPP50;
+ break;
+ default:
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_API,
+ ABE_BLOCK_COPY_ERR);
+ case ABE_OPP100:
+ /* OPP100% */
+ dOppMode32 = DOPPMODE32_OPP100;
+ break;
+ }
+ /* Write Multiframe inside DMEM */
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_MAXTASKBYTESINSLOT_ADDR, &dOppMode32, sizeof(u32));
+ sio_desc_address = OMAP_ABE_D_IODESCR_ADDR + (OMAP_ABE_MM_EXT_IN_PORT *
+ sizeof(struct ABE_SIODescriptor));
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM, sio_desc_address,
+ (u32 *) &sio_desc, sizeof(sio_desc));
+ if (dOppMode32 == DOPPMODE32_OPP100) {
+ /* ASRC input buffer, size 40 */
+ sio_desc.smem_addr1 = smem_mm_ext_in_opp100;
+ /* Init MM_EXT_IN ASRC and enable its adaptation */
+ abe_init_asrc_mm_ext_in(250);
+ } else {
+ /* at OPP 50 or without ASRC */
+ sio_desc.smem_addr1 = smem_mm_ext_in_opp50;
+ }
+
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM, sio_desc_address,
+ (u32 *) &sio_desc, sizeof(sio_desc));
+
+ sio_desc_address = OMAP_ABE_D_IODESCR_ADDR + (OMAP_ABE_BT_VX_UL_PORT *
+ sizeof(struct ABE_SIODescriptor));
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM, sio_desc_address,
+ (u32 *) &sio_desc, sizeof(sio_desc));
+ if (dOppMode32 == DOPPMODE32_OPP100) {
+ /* ASRC input buffer, size 40 */
+ sio_desc.smem_addr1 = smem_bt_vx_ul_opp100;
+ /* Init MM_EXT_IN ASRC and enable its adaptation */
+ abe_init_asrc_bt_ul(250);
+ } else {
+ /* at OPP 50 or without ASRC */
+ sio_desc.smem_addr1 = smem_bt_vx_ul_opp50;
+ }
+
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM, sio_desc_address,
+ (u32 *) &sio_desc, sizeof(sio_desc));
+
+ sio_desc_address = OMAP_ABE_D_IODESCR_ADDR + (OMAP_ABE_BT_VX_DL_PORT *
+ sizeof(struct ABE_SIODescriptor));
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM, sio_desc_address,
+ (u32 *) &sio_desc, sizeof(sio_desc));
+ if (dOppMode32 == DOPPMODE32_OPP100) {
+ /* ASRC input buffer, size 40 */
+ sio_desc.smem_addr1 = smem_bt_vx_dl_opp100;
+ /* Init MM_EXT_IN ASRC and enable its adaptation */
+ abe_init_asrc_bt_dl(250);
+ } else {
+ /* at OPP 50 or without ASRC */
+ sio_desc.smem_addr1 = smem_bt_vx_dl_opp50;
+ }
+
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM, sio_desc_address,
+ (u32 *) &sio_desc, sizeof(sio_desc));
+
+ return 0;
+
+}
+EXPORT_SYMBOL(omap_abe_set_opp_processing);
+
+/**
+ * omap_abe_check_activity - Check if some ABE activity.
+ *
+ * Check if any ABE ports are running.
+ * return 1: still activity on ABE
+ * return 0: no more activity on ABE. Event generator can be stopped
+ *
+ */
+int omap_abe_check_activity(struct omap_abe *abe)
+{
+ int i, ret = 0;
+
+ for (i = 0; i < (LAST_PORT_ID - 1); i++) {
+ if (abe_port[abe_port_priority[i]].status ==
+ OMAP_ABE_PORT_ACTIVITY_RUNNING)
+ break;
+ }
+ if (i < (LAST_PORT_ID - 1))
+ ret = 1;
+ return ret;
+}
+EXPORT_SYMBOL(omap_abe_check_activity);
+
+/**
+ * abe_plug_subroutine
+ * @id: returned sequence index after plugging a new subroutine
+ * @f: subroutine address to be inserted
+ * @n: number of parameters of this subroutine
+ * @params: pointer on parameters
+ *
+ * register a list of subroutines for call-back purpose
+ */
+abehal_status abe_plug_subroutine(u32 *id, abe_subroutine2 f, u32 n,
+ u32 *params)
+{
+ _log(ABE_ID_PLUG_SUBROUTINE, (u32) (*id), (u32) f, n);
+
+ abe_add_subroutine(id, (abe_subroutine2) f, n, (u32 *) params);
+ return 0;
+}
+EXPORT_SYMBOL(abe_plug_subroutine);
diff --git a/sound/soc/omap/abe/abe_dat.c b/sound/soc/omap/abe/abe_dat.c
new file mode 100644
index 0000000..8e42cac
--- /dev/null
+++ b/sound/soc/omap/abe/abe_dat.c
@@ -0,0 +1,457 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#include "abe_legacy.h"
+
+struct omap_abe *abe;
+
+/*
+ * HAL/FW ports status / format / sampling / protocol(call_back) / features
+ * / gain / name
+ */
+abe_port_t abe_port[LAST_PORT_ID]; /* list of ABE ports */
+const abe_port_t abe_port_init[LAST_PORT_ID] = {
+ /* Status Data Format Drift Call-Back Protocol+selector desc_addr;
+ buf_addr; buf_size; iter; irq_addr irq_data DMA_T $Features
+ reseted at start Port Name for the debug trace */
+ /* DMIC */ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {96000, SIX_MSB},
+ NODRIFT, NOCALLBACK, 0, (DMIC_ITER/6),
+ {
+ SNK_P, DMIC_PORT_PROT,
+ {{dmem_dmic, dmem_dmic_size, DMIC_ITER} }
+ },
+ {0, 0},
+ {EQDMIC, 0}, "DMIC"},
+ /* PDM_UL */ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {96000, STEREO_MSB},
+ NODRIFT, NOCALLBACK, smem_amic, (MCPDM_UL_ITER/2),
+ {
+ SNK_P, MCPDMUL_PORT_PROT,
+ {{dmem_amic, dmem_amic_size, MCPDM_UL_ITER} }
+ },
+ {0, 0},
+ {EQAMIC, 0}, "PDM_UL"},
+ /* BT_VX_UL */ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {8000, STEREO_MSB},
+ NODRIFT, NOCALLBACK, smem_bt_vx_ul_opp50, 1,
+ {
+ SNK_P, SERIAL_PORT_PROT, {{
+ (MCBSP1_DMA_TX*ATC_SIZE),
+ dmem_bt_vx_ul,
+ dmem_bt_vx_ul_size,
+ (1*SCHED_LOOP_8kHz)
+ } }
+ },
+ {0, 0}, {0}, "BT_VX_UL"},
+ /* MM_UL */ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+ NODRIFT, NOCALLBACK, smem_mm_ul, 1,
+ {
+ SRC_P, DMAREQ_PORT_PROT, {{
+ (CBPr_DMA_RTX3*ATC_SIZE),
+ dmem_mm_ul, dmem_mm_ul_size,
+ (10*SCHED_LOOP_48kHz),
+ ABE_DMASTATUS_RAW, (1 << 3)
+ } }
+ },
+ {CIRCULAR_BUFFER_PERIPHERAL_R__3, 120},
+ {UPROUTE, 0}, "MM_UL"},
+ /* MM_UL2 */ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+ NODRIFT, NOCALLBACK, smem_mm_ul2, 1,
+ {
+ SRC_P, DMAREQ_PORT_PROT, {{
+ (CBPr_DMA_RTX4*ATC_SIZE),
+ dmem_mm_ul2, dmem_mm_ul2_size,
+ (2*SCHED_LOOP_48kHz),
+ ABE_DMASTATUS_RAW, (1 << 4)
+ } }
+ },
+ {CIRCULAR_BUFFER_PERIPHERAL_R__4, 24},
+ {UPROUTE, 0}, "MM_UL2"},
+ /* VX_UL */ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {8000, MONO_MSB},
+ NODRIFT, NOCALLBACK, smem_vx_ul, 1,
+ {
+ SRC_P, DMAREQ_PORT_PROT, {{
+ (CBPr_DMA_RTX2*ATC_SIZE),
+ dmem_vx_ul, dmem_vx_ul_size,
+ (1*SCHED_LOOP_8kHz),
+ ABE_DMASTATUS_RAW, (1 << 2)
+ } }
+ }, {
+ CIRCULAR_BUFFER_PERIPHERAL_R__2, 2},
+ {ASRC2, 0}, "VX_UL"},
+ /* MM_DL */ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+ NODRIFT, NOCALLBACK, smem_mm_dl, 1,
+ {
+ SNK_P, PINGPONG_PORT_PROT, {{
+ (CBPr_DMA_RTX0*ATC_SIZE),
+ dmem_mm_dl, dmem_mm_dl_size,
+ (2*SCHED_LOOP_48kHz),
+ ABE_DMASTATUS_RAW, (1 << 0)
+ } }
+ },
+ {CIRCULAR_BUFFER_PERIPHERAL_R__0, 24},
+ {ASRC3, 0}, "MM_DL"},
+ /* VX_DL */ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {8000, MONO_MSB},
+ NODRIFT, NOCALLBACK, smem_vx_dl, 1,
+ {
+ SNK_P, DMAREQ_PORT_PROT, {{
+ (CBPr_DMA_RTX1*ATC_SIZE),
+ dmem_vx_dl, dmem_vx_dl_size,
+ (1*SCHED_LOOP_8kHz),
+ ABE_DMASTATUS_RAW, (1 << 1)
+ } }
+ },
+ {CIRCULAR_BUFFER_PERIPHERAL_R__1, 2},
+ {ASRC1, 0}, "VX_DL"},
+ /* TONES_DL */ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+ NODRIFT, NOCALLBACK, smem_tones_dl, 1,
+ {
+ SNK_P, DMAREQ_PORT_PROT, {{
+ (CBPr_DMA_RTX5*ATC_SIZE),
+ dmem_tones_dl,
+ dmem_tones_dl_size,
+ (2*SCHED_LOOP_48kHz),
+ ABE_DMASTATUS_RAW, (1 << 5)
+ } }
+ },
+ {CIRCULAR_BUFFER_PERIPHERAL_R__5, 24},
+ {0}, "TONES_DL"},
+ /* VIB_DL */ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {24000, STEREO_MSB},
+ NODRIFT, NOCALLBACK, smem_vib, 1,
+ {
+ SNK_P, DMAREQ_PORT_PROT, {{
+ (CBPr_DMA_RTX6*ATC_SIZE),
+ dmem_vib_dl, dmem_vib_dl_size,
+ (2*SCHED_LOOP_24kHz),
+ ABE_DMASTATUS_RAW, (1 << 6)
+ } }
+ },
+ {CIRCULAR_BUFFER_PERIPHERAL_R__6, 12},
+ {0}, "VIB_DL"},
+ /* BT_VX_DL */ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {8000, MONO_MSB},
+ NODRIFT, NOCALLBACK, smem_bt_vx_dl_opp50, 1,
+ {
+ SRC_P, SERIAL_PORT_PROT, {{
+ (MCBSP1_DMA_RX*ATC_SIZE),
+ dmem_bt_vx_dl,
+ dmem_bt_vx_dl_size,
+ (1*SCHED_LOOP_8kHz),
+ } }
+ },
+ {0, 0}, {0}, "BT_VX_DL"},
+ /* PDM_DL */ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {96000, SIX_MSB},
+ NODRIFT, NOCALLBACK, 0, (MCPDM_DL_ITER/6),
+ {SRC_P, MCPDMDL_PORT_PROT, {{dmem_mcpdm,
+ dmem_mcpdm_size} } },
+ {0, 0},
+ {MIXDL1, EQ1, APS1, MIXDL2, EQ2L, EQ2R, APS2L, APS2R, 0},
+ "PDM_DL"},
+ /* MM_EXT_OUT */
+ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+ NODRIFT, NOCALLBACK, smem_mm_ext_out, 1,
+ {
+ SRC_P, SERIAL_PORT_PROT, {{
+ (MCBSP1_DMA_TX*ATC_SIZE),
+ dmem_mm_ext_out, dmem_mm_ext_out_size,
+ (2*SCHED_LOOP_48kHz)
+ } }
+ }, {0, 0}, {0}, "MM_EXT_OUT"},
+ /* MM_EXT_IN */
+ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+ NODRIFT, NOCALLBACK, smem_mm_ext_in_opp100, 1,
+ {
+ SNK_P, SERIAL_PORT_PROT, {{
+ (MCBSP1_DMA_RX*ATC_SIZE),
+ dmem_mm_ext_in, dmem_mm_ext_in_size,
+ (2*SCHED_LOOP_48kHz)
+ } }
+ },
+ {0, 0}, {0}, "MM_EXT_IN"},
+ /* PCM3_TX */ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+ NODRIFT, NOCALLBACK, 0, 1,
+ {
+ SRC_P, TDM_SERIAL_PORT_PROT, {{
+ (MCBSP3_DMA_TX *
+ ATC_SIZE),
+ dmem_mm_ext_out,
+ dmem_mm_ext_out_size,
+ (2*SCHED_LOOP_48kHz)
+ } }
+ },
+ {0, 0}, {0}, "TDM_OUT"},
+ /* PCM3_RX */ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+ NODRIFT, NOCALLBACK, 0, 1,
+ {
+ SRC_P, TDM_SERIAL_PORT_PROT, {{
+ (MCBSP3_DMA_RX *
+ ATC_SIZE),
+ dmem_mm_ext_in,
+ dmem_mm_ext_in_size,
+ (2*SCHED_LOOP_48kHz)
+ } }
+ },
+ {0, 0}, {0}, "TDM_IN"},
+ /* SCHD_DBG_PORT */ {
+ OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, MONO_MSB},
+ NODRIFT, NOCALLBACK, 0, 1,
+ {
+ SRC_P, DMAREQ_PORT_PROT, {{
+ (CBPr_DMA_RTX7 *
+ ATC_SIZE),
+ dmem_mm_trace,
+ dmem_mm_trace_size,
+ (2*SCHED_LOOP_48kHz),
+ ABE_DMASTATUS_RAW,
+ (1 << 4)
+ } }
+ }, {CIRCULAR_BUFFER_PERIPHERAL_R__7, 24},
+ {FEAT_SEQ, FEAT_CTL, FEAT_GAINS, 0}, "SCHD_DBG"},
+};
+/*
+ * AESS/ATC destination and source address translation (except McASPs)
+ * from the original 64bits words address
+ */
+const u32 abe_atc_dstid[ABE_ATC_DESC_SIZE >> 3] = {
+ /* DMA_0 DMIC PDM_DL PDM_UL McB1TX McB1RX McB2TX McB2RX 0 .. 7 */
+ 0, 0, 12, 0, 1, 0, 2, 0,
+ /* McB3TX McB3RX SLIMT0 SLIMT1 SLIMT2 SLIMT3 SLIMT4 SLIMT5 8 .. 15 */
+ 3, 0, 4, 5, 6, 7, 8, 9,
+ /* SLIMT6 SLIMT7 SLIMR0 SLIMR1 SLIMR2 SLIMR3 SLIMR4 SLIMR5 16 .. 23 */
+ 10, 11, 0, 0, 0, 0, 0, 0,
+ /* SLIMR6 SLIMR7 McASP1X ----- ----- McASP1R ----- ----- 24 .. 31 */
+ 0, 0, 14, 0, 0, 0, 0, 0,
+ /* CBPrT0 CBPrT1 CBPrT2 CBPrT3 CBPrT4 CBPrT5 CBPrT6 CBPrT7 32 .. 39 */
+ 63, 63, 63, 63, 63, 63, 63, 63,
+ /* CBP_T0 CBP_T1 CBP_T2 CBP_T3 CBP_T4 CBP_T5 CBP_T6 CBP_T7 40 .. 47 */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* CBP_T8 CBP_T9 CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14
+ CBP_T15 48 .. 63 */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+};
+const u32 abe_atc_srcid[ABE_ATC_DESC_SIZE >> 3] = {
+ /* DMA_0 DMIC PDM_DL PDM_UL McB1TX McB1RX McB2TX McB2RX 0 .. 7 */
+ 0, 12, 0, 13, 0, 1, 0, 2,
+ /* McB3TX McB3RX SLIMT0 SLIMT1 SLIMT2 SLIMT3 SLIMT4 SLIMT5 8 .. 15 */
+ 0, 3, 0, 0, 0, 0, 0, 0,
+ /* SLIMT6 SLIMT7 SLIMR0 SLIMR1 SLIMR2 SLIMR3 SLIMR4 SLIMR5 16 .. 23 */
+ 0, 0, 4, 5, 6, 7, 8, 9,
+ /* SLIMR6 SLIMR7 McASP1X ----- ----- McASP1R ----- ----- 24 .. 31 */
+ 10, 11, 0, 0, 0, 14, 0, 0,
+ /* CBPrT0 CBPrT1 CBPrT2 CBPrT3 CBPrT4 CBPrT5 CBPrT6 CBPrT7 32 .. 39 */
+ 63, 63, 63, 63, 63, 63, 63, 63,
+ /* CBP_T0 CBP_T1 CBP_T2 CBP_T3 CBP_T4 CBP_T5 CBP_T6 CBP_T7 40 .. 47 */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* CBP_T8 CBP_T9 CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14
+ CBP_T15 48 .. 63 */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+};
+/*
+ * preset default routing configurations
+ * This is given as implementation EXAMPLES
+ * the programmer uses "abe_set_router_configuration" with its own tables
+ */
+const abe_router_t abe_router_ul_table_preset[NBROUTE_CONFIG][NBROUTE_UL] = {
+ /* VOICE UPLINK WITH PHOENIX MICROPHONES - UPROUTE_CONFIG_AMIC */
+ {
+ /* 0 .. 9 = MM_UL */
+ DMIC1_L_labelID, DMIC1_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID,
+ MM_EXT_IN_L_labelID, MM_EXT_IN_R_labelID, AMIC_L_labelID,
+ AMIC_L_labelID,
+ ZERO_labelID, ZERO_labelID,
+ /* 10 .. 11 = MM_UL2 */
+ AMIC_L_labelID, AMIC_L_labelID,
+ /* 12 .. 13 = VX_UL */
+ AMIC_L_labelID, AMIC_R_labelID,
+ /* 14 .. 15 = RESERVED */
+ ZERO_labelID, ZERO_labelID,
+ },
+ /* VOICE UPLINK WITH THE FIRST DMIC PAIR - UPROUTE_CONFIG_DMIC1 */
+ {
+ /* 0 .. 9 = MM_UL */
+ DMIC2_L_labelID, DMIC2_R_labelID, DMIC3_L_labelID, DMIC3_R_labelID,
+ DMIC1_L_labelID, DMIC1_R_labelID, ZERO_labelID, ZERO_labelID,
+ ZERO_labelID, ZERO_labelID,
+ /* 10 .. 11 = MM_UL2 */
+ DMIC1_L_labelID, DMIC1_R_labelID,
+ /* 12 .. 13 = VX_UL */
+ DMIC1_L_labelID, DMIC1_R_labelID,
+ /* 14 .. 15 = RESERVED */
+ ZERO_labelID, ZERO_labelID,
+ },
+ /* VOICE UPLINK WITH THE SECOND DMIC PAIR - UPROUTE_CONFIG_DMIC2 */
+ {
+ /* 0 .. 9 = MM_UL */
+ DMIC3_L_labelID, DMIC3_R_labelID, DMIC1_L_labelID, DMIC1_R_labelID,
+ DMIC2_L_labelID, DMIC2_R_labelID, ZERO_labelID, ZERO_labelID,
+ ZERO_labelID, ZERO_labelID,
+ /* 10 .. 11 = MM_UL2 */
+ DMIC2_L_labelID, DMIC2_R_labelID,
+ /* 12 .. 13 = VX_UL */
+ DMIC2_L_labelID, DMIC2_R_labelID,
+ /* 14 .. 15 = RESERVED */
+ ZERO_labelID, ZERO_labelID,
+ },
+ /* VOICE UPLINK WITH THE LAST DMIC PAIR - UPROUTE_CONFIG_DMIC3 */
+ {
+ /* 0 .. 9 = MM_UL */
+ AMIC_L_labelID, AMIC_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID,
+ DMIC3_L_labelID, DMIC3_R_labelID, ZERO_labelID, ZERO_labelID,
+ ZERO_labelID, ZERO_labelID,
+ /* 10 .. 11 = MM_UL2 */
+ DMIC3_L_labelID, DMIC3_R_labelID,
+ /* 12 .. 13 = VX_UL */
+ DMIC3_L_labelID, DMIC3_R_labelID,
+ /* 14 .. 15 = RESERVED */
+ ZERO_labelID, ZERO_labelID,
+ },
+ /* VOICE UPLINK WITH THE BT - UPROUTE_CONFIG_BT */
+ {
+ /* 0 .. 9 = MM_UL */
+ BT_UL_L_labelID, BT_UL_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID,
+ DMIC3_L_labelID, DMIC3_R_labelID, DMIC1_L_labelID, DMIC1_R_labelID,
+ ZERO_labelID, ZERO_labelID,
+ /* 10 .. 11 = MM_UL2 */
+ AMIC_L_labelID, AMIC_R_labelID,
+ /* 12 .. 13 = VX_UL */
+ BT_UL_L_labelID, BT_UL_R_labelID,
+ /* 14 .. 15 = RESERVED */
+ ZERO_labelID, ZERO_labelID,
+ },
+ /* VOICE UPLINK WITH THE BT - UPROUTE_ECHO_MMUL2 */
+ {
+ /* 0 .. 9 = MM_UL */
+ MM_EXT_IN_L_labelID, MM_EXT_IN_R_labelID, BT_UL_L_labelID,
+ BT_UL_R_labelID, AMIC_L_labelID, AMIC_R_labelID,
+ ZERO_labelID, ZERO_labelID, ZERO_labelID, ZERO_labelID,
+ /* 10 .. 11 = MM_UL2 */
+ EchoRef_L_labelID, EchoRef_R_labelID,
+ /* 12 .. 13 = VX_UL */
+ AMIC_L_labelID, AMIC_L_labelID,
+ /* 14 .. 15 = RESERVED */
+ ZERO_labelID, ZERO_labelID,
+ },
+};
+/* all default routing configurations */
+abe_router_t abe_router_ul_table[NBROUTE_CONFIG_MAX][NBROUTE_UL];
+
+const abe_sequence_t seq_null = {
+ NOMASK, {CL_M1, 0, {0, 0, 0, 0}, 0}, {CL_M1, 0, {0, 0, 0, 0}, 0}
+};
+/* table of new subroutines called in the sequence */
+abe_subroutine2 abe_all_subsubroutine[MAXNBSUBROUTINE];
+/* number of parameters per calls */
+u32 abe_all_subsubroutine_nparam[MAXNBSUBROUTINE];
+/* index of the subroutine */
+u32 abe_subroutine_id[MAXNBSUBROUTINE];
+/* paramters of the subroutine (if any) */
+u32 *abe_all_subroutine_params[MAXNBSUBROUTINE];
+u32 abe_subroutine_write_pointer;
+/* table of all sequences */
+abe_sequence_t abe_all_sequence[MAXNBSEQUENCE];
+u32 abe_sequence_write_pointer;
+/* current number of pending sequences (avoids to look in the table) */
+u32 abe_nb_pending_sequences;
+/* pending sequences due to ressource collision */
+u32 abe_pending_sequences[MAXNBSEQUENCE];
+/* mask of unsharable ressources among other sequences */
+u32 abe_global_sequence_mask;
+/* table of active sequences */
+abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE][MAXSEQUENCESTEPS];
+/* index of the plugged subroutine doing ping-pong cache-flush DMEM accesses */
+u32 abe_irq_pingpong_player_id;
+/* index of the plugged subroutine doing acoustics protection adaptation */
+u32 abe_irq_aps_adaptation_id;
+/* base addresses of the ping pong buffers in bytes addresses */
+u32 abe_base_address_pingpong[MAX_PINGPONG_BUFFERS];
+/* size of each ping/pong buffers */
+u32 abe_size_pingpong;
+/* number of ping/pong buffer being used */
+u32 abe_nb_pingpong;
+/*
+ * MAIN PORT SELECTION
+ */
+const u32 abe_port_priority[LAST_PORT_ID - 1] = {
+ OMAP_ABE_PDM_DL_PORT,
+ OMAP_ABE_PDM_UL_PORT,
+ OMAP_ABE_MM_EXT_OUT_PORT,
+ OMAP_ABE_MM_EXT_IN_PORT,
+ OMAP_ABE_DMIC_PORT,
+ OMAP_ABE_MM_UL_PORT,
+ OMAP_ABE_MM_UL2_PORT,
+ OMAP_ABE_MM_DL_PORT,
+ OMAP_ABE_TONES_DL_PORT,
+ OMAP_ABE_VX_UL_PORT,
+ OMAP_ABE_VX_DL_PORT,
+ OMAP_ABE_BT_VX_DL_PORT,
+ OMAP_ABE_BT_VX_UL_PORT,
+ OMAP_ABE_VIB_DL_PORT,
+};
diff --git a/sound/soc/omap/abe/abe_dbg.c b/sound/soc/omap/abe/abe_dbg.c
new file mode 100644
index 0000000..d1b160f
--- /dev/null
+++ b/sound/soc/omap/abe/abe_dbg.c
@@ -0,0 +1,201 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include "abe_dbg.h"
+#include "abe.h"
+#include "abe_mem.h"
+
+/**
+ * omap_abe_dbg_reset
+ * @dbg: Pointer on abe debug handle
+ *
+ * Called in order to reset Audio Back End debug global data.
+ * This ensures that ABE debug trace pointer is reset correctly.
+ */
+int omap_abe_dbg_reset(struct omap_abe_dbg *dbg)
+{
+ dbg->activity_log_write_pointer = 0;
+ dbg->mask = 0;
+
+ return 0;
+}
+
+/**
+ * omap_abe_connect_debug_trace
+ * @abe: Pointer on abe handle
+ * @dma2:pointer to the DMEM trace buffer
+ *
+ * returns the address and size of the real-time debug trace buffer,
+ * the content of which will vary from one firmware release to another
+ */
+int omap_abe_connect_debug_trace(struct omap_abe *abe,
+ struct omap_abe_dma *dma2)
+{
+ _log(ABE_ID_CONNECT_DEBUG_TRACE, 0, 0, 0);
+
+ /* return tohe base address of the ping buffer in L3 and L4 spaces */
+ (*dma2).data = (void *)(OMAP_ABE_D_DEBUG_FIFO_ADDR +
+ ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_DMEM_BASE_OFFSET_MPU);
+ (*dma2).l3_dmem = (void *)(OMAP_ABE_D_DEBUG_FIFO_ADDR +
+ ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_DMEM_BASE_OFFSET_MPU);
+ (*dma2).l4_dmem = (void *)(OMAP_ABE_D_DEBUG_FIFO_ADDR +
+ ABE_DEFAULT_BASE_ADDRESS_L4 + ABE_DMEM_BASE_OFFSET_MPU);
+ (*dma2).iter = (OMAP_ABE_D_DEBUG_FIFO_SIZE + OMAP_ABE_D_DEBUG_FIFO_HAL_SIZE)>>2;
+
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_connect_debug_trace);
+
+/**
+ * omap_abe_set_debug_trace
+ * @dbg: Pointer on abe debug handle
+ * @debug: debug log level
+ *
+ * Set the debug level for ABE trace. This level allows to manage the number
+ * of information put inside the ABE trace buffer. This buffer can contains
+ * both AESS firmware and MPU traces.
+ */
+int omap_abe_set_debug_trace(struct omap_abe_dbg *dbg, int debug)
+{
+ _log(ABE_ID_SET_DEBUG_TRACE, 0, 0, 0);
+
+ dbg->mask = debug;
+
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_set_debug_trace);
+
+/**
+ * omap_abe_dbg_log - Log ABE trace inside circular buffer
+ * @x: data to be logged
+ * @y: data to be logged
+ * @z: data to be logged
+ * @t: data to be logged
+ * Parameter :
+ *
+ * abe_dbg_activity_log : global circular buffer holding the data
+ * abe_dbg_activity_log_write_pointer : circular write pointer
+ *
+ * saves data in the log file
+ */
+void omap_abe_dbg_log(struct omap_abe *abe, u32 x, u32 y, u32 z, u32 t)
+{
+ u32 time_stamp, data;
+ struct omap_abe_dbg *dbg = &abe->dbg;
+
+ if (dbg->activity_log_write_pointer >=
+ (OMAP_ABE_D_DEBUG_HAL_TASK_SIZE - 2))
+ dbg->activity_log_write_pointer = 0;
+
+ /* copy in DMEM trace buffer and CortexA9 local buffer and a small 7
+ words circular buffer of the DMA trace ending with 0x55555555
+ (tag for last word) */
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM, OMAP_ABE_D_LOOPCOUNTER_ADDR,
+ (u32 *) &time_stamp, sizeof(time_stamp));
+ dbg->activity_log[dbg->activity_log_write_pointer] = time_stamp;
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_DEBUG_HAL_TASK_ADDR +
+ (dbg->activity_log_write_pointer << 2),
+ (u32 *) &time_stamp, sizeof(time_stamp));
+ dbg->activity_log_write_pointer++;
+
+ data = ((x & MAX_UINT8) << 24) | ((y & MAX_UINT8) << 16) |
+ ((z & MAX_UINT8) << 8)
+ | (t & MAX_UINT8);
+ dbg->activity_log[dbg->activity_log_write_pointer] = data;
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_DEBUG_HAL_TASK_ADDR +
+ (dbg->activity_log_write_pointer << 2),
+ (u32 *) &data, sizeof(data));
+
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_DEBUG_FIFO_HAL_ADDR +
+ ((dbg->activity_log_write_pointer << 2) &
+ (OMAP_ABE_D_DEBUG_FIFO_HAL_SIZE - 1)), (u32 *) &data,
+ sizeof(data));
+
+ data = ABE_DBG_MAGIC_NUMBER;
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_DEBUG_FIFO_HAL_ADDR +
+ (((dbg->activity_log_write_pointer + 1) << 2) &
+ (OMAP_ABE_D_DEBUG_FIFO_HAL_SIZE - 1)),
+ (u32 *) &data, sizeof(data));
+ dbg->activity_log_write_pointer++;
+
+ if (dbg->activity_log_write_pointer >= OMAP_ABE_D_DEBUG_HAL_TASK_SIZE)
+ dbg->activity_log_write_pointer = 0;
+}
+
+/**
+ * omap_abe_dbg_error_log - Log ABE error
+ * @abe: Pointer on abe handle
+ * @level: level of error
+ * @error: error ID to log
+ *
+ * Log the ABE errors.
+ */
+void omap_abe_dbg_error(struct omap_abe *abe, int level, int error)
+{
+ omap_abe_dbg_log(abe, error, MAX_UINT8, MAX_UINT8, MAX_UINT8);
+}
diff --git a/sound/soc/omap/abe/abe_dbg.h b/sound/soc/omap/abe/abe_dbg.h
new file mode 100644
index 0000000..2cdced9
--- /dev/null
+++ b/sound/soc/omap/abe/abe_dbg.h
@@ -0,0 +1,206 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_DBG_H_
+#define _ABE_DBG_H_
+
+#include "abe_typ.h"
+#include "abe_dm_addr.h"
+
+/*
+ * Debug trace format
+ * TIME 2 bytes from ABE : 4kHz period of the FW scheduler
+ * SUBID 1 byte : HAL API index
+ * From 0 to 16 bytes : parameters of the subroutine
+ * on every 32 dumps a tag is pushed on the debug trace : 0x55555555
+ */
+#define dbg_bitfield_offset 8
+#define dbg_api_calls 0
+#define dbg_mapi (1L << (dbg_api_calls + dbg_bitfield_offset))
+#define dbg_external_data_access 1
+#define dbg_mdata (1L << (dbg_external_data_access + dbg_bitfield_offset))
+#define dbg_err_codes 2
+#define dbg_merr (1L << (dbg_api_calls + dbg_bitfield_offset))
+#define ABE_DBG_MAGIC_NUMBER 0x55555555
+/*
+ * IDs used for traces
+ */
+#define ABE_ID_RESET_HAL (1 + dbg_mapi)
+#define ABE_ID_LOAD_FW (2 + dbg_mapi)
+#define ABE_ID_DEFAULT_CONFIGURATION (3 + dbg_mapi)
+#define ABE_ID_IRQ_PROCESSING (4 + dbg_mapi)
+#define ABE_ID_EVENT_GENERATOR_SWITCH (5 + dbg_mapi)
+#define ABE_ID_READ_HARDWARE_CONFIGURATION (6 + dbg_mapi)
+#define ABE_ID_READ_LOWEST_OPP (7 + dbg_mapi)
+#define ABE_ID_WRITE_GAIN (8 + dbg_mapi)
+#define ABE_ID_SET_ASRC_DRIFT_CONTROL (9 + dbg_mapi)
+#define ABE_ID_PLUG_SUBROUTINE (10 + dbg_mapi)
+#define ABE_ID_UNPLUG_SUBROUTINE (11 + dbg_mapi)
+#define ABE_ID_PLUG_SEQUENCE (12 + dbg_mapi)
+#define ABE_ID_LAUNCH_SEQUENCE (13 + dbg_mapi)
+#define ABE_ID_LAUNCH_SEQUENCE_param (14 + dbg_mapi)
+#define ABE_ID_CONNECT_IRQ_PING_PONG_PORT (15 + dbg_mapi)
+#define ABE_ID_READ_ANALOG_GAIN_DL (16 + dbg_mapi)
+#define ABE_ID_READ_ANALOG_GAIN_UL (17 + dbg_mapi)
+#define ABE_ID_ENABLE_DYN_UL_GAIN (18 + dbg_mapi)
+#define ABE_ID_DISABLE_DYN_UL_GAIN (19 + dbg_mapi)
+#define ABE_ID_ENABLE_DYN_EXTENSION (20 + dbg_mapi)
+#define ABE_ID_DISABLE_DYN_EXTENSION (21 + dbg_mapi)
+#define ABE_ID_NOTIFY_ANALOG_GAIN_CHANGED (22 + dbg_mapi)
+#define ABE_ID_RESET_PORT (23 + dbg_mapi)
+#define ABE_ID_READ_REMAINING_DATA (24 + dbg_mapi)
+#define ABE_ID_DISABLE_DATA_TRANSFER (25 + dbg_mapi)
+#define ABE_ID_ENABLE_DATA_TRANSFER (26 + dbg_mapi)
+#define ABE_ID_READ_GLOBAL_COUNTER (27 + dbg_mapi)
+#define ABE_ID_SET_DMIC_FILTER (28 + dbg_mapi)
+#define ABE_ID_SET_OPP_PROCESSING (29 + dbg_mapi)
+#define ABE_ID_SET_PING_PONG_BUFFER (30 + dbg_mapi)
+#define ABE_ID_READ_PORT_ADDRESS (31 + dbg_mapi)
+#define ABE_ID_LOAD_FW_param (32 + dbg_mapi)
+#define ABE_ID_WRITE_HEADSET_OFFSET (33 + dbg_mapi)
+#define ABE_ID_READ_GAIN_RANGES (34 + dbg_mapi)
+#define ABE_ID_WRITE_EQUALIZER (35 + dbg_mapi)
+#define ABE_ID_WRITE_ASRC (36 + dbg_mapi)
+#define ABE_ID_WRITE_APS (37 + dbg_mapi)
+#define ABE_ID_WRITE_MIXER (38 + dbg_mapi)
+#define ABE_ID_WRITE_EANC (39 + dbg_mapi)
+#define ABE_ID_WRITE_ROUTER (40 + dbg_mapi)
+#define ABE_ID_READ_PORT_GAIN (41 + dbg_mapi)
+#define ABE_ID_ASRC (42 + dbg_mapi)
+#define ABE_ID_READ_APS (43 + dbg_mapi)
+#define ABE_ID_READ_APS_energy (44 + dbg_mapi)
+#define ABE_ID_READ_MIXER (45 + dbg_mapi)
+#define ABE_READ_EANC (46 + dbg_mapi)
+#define ABE_ID_READ_ROUTER (47 + dbg_mapi)
+#define ABE_ID_READ_DEBUG_TRACE (48 + dbg_mapi)
+#define ABE_ID_SET_SEQUENCE_TIME_ACCURACY (49 + dbg_mapi)
+#define ABE_ID_SET_DEBUG_PINS (50 + dbg_mapi)
+#define ABE_ID_SELECT_MAIN_PORT (51 + dbg_mapi)
+#define ABE_ID_WRITE_EVENT_GENERATOR (52 + dbg_mapi)
+#define ABE_ID_READ_USE_CASE_OPP (53 + dbg_mapi)
+#define ABE_ID_SELECT_DATA_SOURCE (54 + dbg_mapi)
+#define ABE_ID_READ_NEXT_PING_PONG_BUFFER (55 + dbg_mapi)
+#define ABE_ID_INIT_PING_PONG_BUFFER (56 + dbg_mapi)
+#define ABE_ID_CONNECT_CBPR_DMAREQ_PORT (57 + dbg_mapi)
+#define ABE_ID_CONNECT_DMAREQ_PORT (58 + dbg_mapi)
+#define ABE_ID_CONNECT_DMAREQ_PING_PONG_PORT (59 + dbg_mapi)
+#define ABE_ID_CONNECT_SERIAL_PORT (60 + dbg_mapi)
+#define ABE_ID_CONNECT_SLIMBUS_PORT (61 + dbg_mapi)
+#define ABE_ID_READ_GAIN (62 + dbg_mapi)
+#define ABE_ID_SET_ROUTER_CONFIGURATION (63 + dbg_mapi)
+#define ABE_ID_CONNECT_DEBUG_TRACE (64 + dbg_mapi)
+#define ABE_ID_SET_DEBUG_TRACE (65 + dbg_mapi)
+#define ABE_ID_REMOTE_DEBUGGER_INTERFACE (66 + dbg_mapi)
+#define ABE_ID_ENABLE_TEST_PATTERN (67 + dbg_mapi)
+#define ABE_ID_CONNECT_TDM_PORT (68 + dbg_mapi)
+/*
+ * IDs used for error codes
+ */
+#define NOERR 0
+#define ABE_SET_MEMORY_CONFIG_ERR (1 + dbg_merr)
+#define ABE_BLOCK_COPY_ERR (2 + dbg_merr)
+#define ABE_SEQTOOLONG (3 + dbg_merr)
+#define ABE_BADSAMPFORMAT (4 + dbg_merr)
+#define ABE_SET_ATC_ABE_BLOCK_COPY_ERR MEMORY_CONFIG_ERR (5 + dbg_merr)
+#define ABE_PROTOCOL_ERROR (6 + dbg_merr)
+#define ABE_PARAMETER_ERROR (7 + dbg_merr)
+/* port programmed while still running */
+#define ABE_PORT_REPROGRAMMING (8 + dbg_merr)
+#define ABE_READ_USE_CASE_OPP_ERR (9 + dbg_merr)
+#define ABE_PARAMETER_OVERFLOW (10 + dbg_merr)
+#define ABE_FW_FIFO_WRITE_PTR_ERR (11 + dbg_merr)
+
+/*
+ * IDs used for error codes
+ */
+#define OMAP_ABE_ERR_LIB (1 << 1)
+#define OMAP_ABE_ERR_API (1 << 2)
+#define OMAP_ABE_ERR_INI (1 << 3)
+#define OMAP_ABE_ERR_SEQ (1 << 4)
+#define OMAP_ABE_ERR_DBG (1 << 5)
+#define OMAP_ABE_ERR_EXT (1 << 6)
+
+struct omap_abe_dbg {
+ /* Debug Data */
+ u32 activity_log[OMAP_ABE_D_DEBUG_HAL_TASK_SIZE];
+ u32 activity_log_write_pointer;
+ u32 mask;
+};
+
+struct omap_abe_dma {
+ /* OCP L3 pointer to the first address of the */
+ void *data;
+ /* destination buffer (either DMA or Ping-Pong read/write pointers). */
+ /* address L3 when addressing the DMEM buffer instead of CBPr */
+ void *l3_dmem;
+ /* address L3 translated to L4 the ARM memory space */
+ void *l4_dmem;
+ /* number of iterations for the DMA data moves. */
+ u32 iter;
+};
+
+/**
+ * omap_abe_dbg_reset
+ * @dbg: Pointer on abe debug handle
+ *
+ * Called in order to reset Audio Back End debug global data.
+ * This ensures that ABE debug trace pointer is reset correctly.
+ */
+int omap_abe_dbg_reset(struct omap_abe_dbg *dbg);
+
+#endif /* _ABE_DBG_H_ */
diff --git a/sound/soc/omap/abe/abe_def.h b/sound/soc/omap/abe/abe_def.h
new file mode 100644
index 0000000..2cce906
--- /dev/null
+++ b/sound/soc/omap/abe/abe_def.h
@@ -0,0 +1,307 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_DEF_H_
+#define _ABE_DEF_H_
+/*
+ * HARDWARE AND PERIPHERAL DEFINITIONS
+ */
+/* MM_DL */
+#define ABE_CBPR0_IDX 0
+/* VX_DL */
+#define ABE_CBPR1_IDX 1
+/* VX_UL */
+#define ABE_CBPR2_IDX 2
+/* MM_UL */
+#define ABE_CBPR3_IDX 3
+/* MM_UL2 */
+#define ABE_CBPR4_IDX 4
+/* TONES */
+#define ABE_CBPR5_IDX 5
+/* VIB */
+#define ABE_CBPR6_IDX 6
+/* DEBUG/CTL */
+#define ABE_CBPR7_IDX 7
+#define CIRCULAR_BUFFER_PERIPHERAL_R__0 (0x100 + ABE_CBPR0_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__1 (0x100 + ABE_CBPR1_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__2 (0x100 + ABE_CBPR2_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__3 (0x100 + ABE_CBPR3_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__4 (0x100 + ABE_CBPR4_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__5 (0x100 + ABE_CBPR5_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__6 (0x100 + ABE_CBPR6_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__7 (0x100 + ABE_CBPR7_IDX*4)
+#define PING_PONG_WITH_MCU_IRQ 1
+#define PING_PONG_WITH_DSP_IRQ 2
+/* ID used for LIB memory copy subroutines */
+#define COPY_FROM_ABE_TO_HOST 1
+#define COPY_FROM_HOST_TO_ABE 2
+/*
+ * INTERNAL DEFINITIONS
+ */
+#define ABE_FIRMWARE_MAX_SIZE 26629
+/* 24 Q6.26 coefficients */
+#define NBEQ1 25
+/* 2x12 Q6.26 coefficients */
+#define NBEQ2 13
+/* TBD APS first set of parameters */
+#define NBAPS1 10
+/* TBD APS second set of parameters */
+#define NBAPS2 10
+/* Mixer used for sending tones to the uplink voice path */
+#define NBMIX_AUDIO_UL 2
+/* Main downlink mixer */
+#define NBMIX_DL1 4
+/* Handsfree downlink mixer */
+#define NBMIX_DL2 4
+/* Side-tone mixer */
+#define NBMIX_SDT 2
+/* Echo reference mixer */
+#define NBMIX_ECHO 2
+/* Voice record mixer */
+#define NBMIX_VXREC 4
+/* unsigned version of (-1) */
+#define CC_M1 0xFF
+#define CS_M1 0xFFFF
+#define CL_M1 0xFFFFFFFFL
+/*
+ Mixer ID Input port ID Comments
+ DL1_MIXER 0 MMDL path
+ 1 MMUL2 path
+ 2 VXDL path
+ 3 TONES path
+ SDT_MIXER 0 Uplink path
+ 1 Downlink path
+ ECHO_MIXER 0 DL1_MIXER path
+ 1 DL2_MIXER path
+ AUDUL_MIXER 0 TONES_DL path
+ 1 Uplink path
+ 2 MM_DL path
+ VXREC_MIXER 0 TONES_DL path
+ 1 VX_DL path
+ 2 MM_DL path
+ 3 VX_UL path
+*/
+#define MIX_VXUL_INPUT_MM_DL 0
+#define MIX_VXUL_INPUT_TONES 1
+#define MIX_VXUL_INPUT_VX_UL 2
+#define MIX_VXUL_INPUT_VX_DL 3
+#define MIX_DL1_INPUT_MM_DL 0
+#define MIX_DL1_INPUT_MM_UL2 1
+#define MIX_DL1_INPUT_VX_DL 2
+#define MIX_DL1_INPUT_TONES 3
+#define MIX_DL2_INPUT_MM_DL 0
+#define MIX_DL2_INPUT_MM_UL2 1
+#define MIX_DL2_INPUT_VX_DL 2
+#define MIX_DL2_INPUT_TONES 3
+#define MIX_SDT_INPUT_UP_MIXER 0
+#define MIX_SDT_INPUT_DL1_MIXER 1
+#define MIX_AUDUL_INPUT_MM_DL 0
+#define MIX_AUDUL_INPUT_TONES 1
+#define MIX_AUDUL_INPUT_UPLINK 2
+#define MIX_AUDUL_INPUT_VX_DL 3
+#define MIX_VXREC_INPUT_MM_DL 0
+#define MIX_VXREC_INPUT_TONES 1
+#define MIX_VXREC_INPUT_VX_UL 2
+#define MIX_VXREC_INPUT_VX_DL 3
+#define MIX_ECHO_DL1 0
+#define MIX_ECHO_DL2 1
+/* nb of samples to route */
+#define NBROUTE_UL 16
+/* 10 routing tables max */
+#define NBROUTE_CONFIG_MAX 10
+/* 5 pre-computed routing tables */
+#define NBROUTE_CONFIG 6
+/* AMIC on VX_UL */
+#define UPROUTE_CONFIG_AMIC 0
+/* DMIC first pair on VX_UL */
+#define UPROUTE_CONFIG_DMIC1 1
+/* DMIC second pair on VX_UL */
+#define UPROUTE_CONFIG_DMIC2 2
+/* DMIC last pair on VX_UL */
+#define UPROUTE_CONFIG_DMIC3 3
+/* BT_UL on VX_UL */
+#define UPROUTE_CONFIG_BT 4
+/* ECHO_REF on MM_UL2 */
+#define UPROUTE_ECHO_MMUL2 5
+/* call-back indexes */
+#define MAXCALLBACK 100
+/* subroutines */
+#define MAXNBSUBROUTINE 100
+/* time controlled sequenced */
+#define MAXNBSEQUENCE 20
+/* maximum simultaneous active sequences */
+#define MAXACTIVESEQUENCE 20
+/* max number of steps in the sequences */
+#define MAXSEQUENCESTEPS 2
+/* max number of feature associated to a port */
+#define MAXFEATUREPORT 12
+#define SUB_0_PARAM 0
+/* number of parameters per sequence calls */
+#define SUB_1_PARAM 1
+#define SUB_2_PARAM 2
+#define SUB_3_PARAM 3
+#define SUB_4_PARAM 4
+/* active sequence mask = 0 means the line is free */
+#define FREE_LINE 0
+/* no ask for collision protection */
+#define NOMASK (1 << 0)
+/* do not allow a PDM OFF during the execution of this sequence */
+#define MASK_PDM_OFF (1 << 1)
+/* do not allow a PDM ON during the execution of this sequence */
+#define MASK_PDM_ON (1 << 2)
+/* explicit name of the feature */
+#define NBCHARFEATURENAME 16
+/* explicit name of the port */
+#define NBCHARPORTNAME 16
+/* sink / input port from Host point of view (or AESS for DMIC/McPDM/.. */
+#define SNK_P ABE_ATC_DIRECTION_IN
+/* source / ouptut port */
+#define SRC_P ABE_ATC_DIRECTION_OUT
+/* no ASRC applied */
+#define NODRIFT 0
+/* for abe_set_asrc_drift_control */
+#define FORCED_DRIFT_CONTROL 1
+/* for abe_set_asrc_drift_control */
+#define ADPATIVE_DRIFT_CONTROL 2
+/* number of task/slot depending on the OPP value */
+#define DOPPMODE32_OPP100 (0x00000010)
+#define DOPPMODE32_OPP50 (0x0000000C)
+#define DOPPMODE32_OPP25 (0x0000004)
+/*
+ * ABE CONST AREA FOR PARAMETERS TRANSLATION
+ */
+#define GAIN_MAXIMUM 3000L
+#define GAIN_24dB 2400L
+#define GAIN_18dB 1800L
+#define GAIN_12dB 1200L
+#define GAIN_6dB 600L
+/* default gain = 1 */
+#define GAIN_0dB 0L
+#define GAIN_M6dB -600L
+#define GAIN_M12dB -1200L
+#define GAIN_M18dB -1800L
+#define GAIN_M24dB -2400L
+#define GAIN_M30dB -3000L
+#define GAIN_M40dB -4000L
+#define GAIN_M50dB -5000L
+/* muted gain = -120 decibels */
+#define MUTE_GAIN -12000L
+#define GAIN_TOOLOW -13000L
+#define GAIN_MUTE MUTE_GAIN
+#define RAMP_MINLENGTH 3L
+/* ramp_t is in milli- seconds */
+#define RAMP_0MS 0L
+#define RAMP_1MS 1L
+#define RAMP_2MS 2L
+#define RAMP_5MS 5L
+#define RAMP_10MS 10L
+#define RAMP_20MS 20L
+#define RAMP_50MS 50L
+#define RAMP_100MS 100L
+#define RAMP_200MS 200L
+#define RAMP_500MS 500L
+#define RAMP_1000MS 1000L
+#define RAMP_MAXLENGTH 10000L
+/* for abe_translate_gain_format */
+#define LINABE_TO_DECIBELS 1
+#define DECIBELS_TO_LINABE 2
+/* for abe_translate_ramp_format */
+#define IIRABE_TO_MICROS 1
+#define MICROS_TO_IIABE 2
+/*
+ * ABE CONST AREA FOR PERIPHERAL TUNING
+ */
+/* port idled IDLE_P */
+#define OMAP_ABE_PORT_ACTIVITY_IDLE 1
+/* port initialized, ready to be activated */
+#define OMAP_ABE_PORT_INITIALIZED 3
+/* port activated RUN_P */
+#define OMAP_ABE_PORT_ACTIVITY_RUNNING 2
+#define NOCALLBACK 0
+#define NOPARAMETER 0
+/* number of ATC access upon AMIC DMArequests, all the FIFOs are enabled */
+#define MCPDM_UL_ITER 4
+/* All the McPDM FIFOs are enabled simultaneously */
+#define MCPDM_DL_ITER 24
+/* All the DMIC FIFOs are enabled simultaneously */
+#define DMIC_ITER 12
+/* TBD later if needed */
+#define MAX_PINGPONG_BUFFERS 2
+/*
+ * Indexes to the subroutines
+ */
+#define SUB_WRITE_MIXER 1
+#define SUB_WRITE_PORT_GAIN 2
+/* OLD WAY */
+#define c_feat_init_eq 1
+#define c_feat_read_eq1 2
+#define c_write_eq1 3
+#define c_feat_read_eq2 4
+#define c_write_eq2 5
+#define c_feat_read_eq3 6
+#define c_write_eq3 7
+/* max number of gain to be controlled by HAL */
+#define MAX_NBGAIN_CMEM 36
+/*
+ * MACROS
+ */
+#define maximum(a, b) (((a) < (b)) ? (b) : (a))
+#define minimum(a, b) (((a) > (b)) ? (b) : (a))
+#define absolute(a) (((a) > 0) ? (a) : ((-1)*(a)))
+#define HAL_VERSIONS 9
+#endif/* _ABE_DEF_H_ */
diff --git a/sound/soc/omap/abe/abe_define.h b/sound/soc/omap/abe/abe_define.h
new file mode 100644
index 0000000..1dfa0a3
--- /dev/null
+++ b/sound/soc/omap/abe/abe_define.h
@@ -0,0 +1,104 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_DEFINE_H_
+#define _ABE_DEFINE_H_
+
+#define ATC_DESCRIPTOR_NUMBER 64
+#define PROCESSING_SLOTS 25
+#define TASK_POOL_LENGTH 128
+#define MCU_IRQ 0x24
+#define MCU_IRQ_SHIFT2 0x90
+#define DMA_REQ_SHIFT2 0x210
+#define DSP_IRQ 0x4c
+#define IRQtag_APS 0x000a
+#define IRQtag_COUNT 0x000c
+#define IRQtag_PP 0x000d
+#define DMAreq_7 0x0080
+#define IRQ_FIFO_LENGTH 16
+#define SDT_EQ_ORDER 4
+#define DL_EQ_ORDER 12
+#define MIC_FILTER_ORDER 4
+#define GAINS_WITH_RAMP1 14
+#define GAINS_WITH_RAMP2 22
+#define GAINS_WITH_RAMP_TOTAL 36
+#define ASRC_MEMLENGTH 40
+#define ASRC_UL_VX_FIR_L 19
+#define ASRC_DL_VX_FIR_L 19
+#define ASRC_MM_EXT_IN_FIR_L 18
+#define ASRC_margin 2
+#define ASRC_N_8k 2
+#define ASRC_N_16k 4
+#define ASRC_N_48k 12
+#define VIBRA_N 5
+#define VIBRA1_IIR_MEMSIZE 11
+#define SAMP_LOOP_96K 24
+#define SAMP_LOOP_48K 12
+#define SAMP_LOOP_16K 4
+#define SAMP_LOOP_8K 2
+#define INPUT_SCALE_SHIFTM2 5056
+#define OUTPUT_SCALE_SHIFTM2 5060
+#define MUTE_SCALING 5064
+#define ABE_PMEM 1
+#define ABE_CMEM 2
+#define ABE_SMEM 3
+#define ABE_DMEM 4
+#define ABE_ATC 5
+#define ASRC_BT_UL_FIR_L 19
+#define ASRC_BT_DL_FIR_L 19
+#endif /* _ABE_DEFINE_H_ */
diff --git a/sound/soc/omap/abe/abe_dm_addr.h b/sound/soc/omap/abe/abe_dm_addr.h
new file mode 100644
index 0000000..5d10e11
--- /dev/null
+++ b/sound/soc/omap/abe/abe_dm_addr.h
@@ -0,0 +1,360 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#define OMAP_ABE_D_ATCDESCRIPTORS_ADDR 0x0
+#define OMAP_ABE_D_ATCDESCRIPTORS_SIZE 0x200
+
+#define OMAP_ABE_STACK_ADDR 0x200
+#define OMAP_ABE_STACK_SIZE 0x70
+
+#define OMAP_ABE_D_VERSION_ADDR 0x270
+#define OMAP_ABE_D_VERSION_SIZE 0x4
+
+#define OMAP_ABE_D_BT_DL_FIFO_ADDR 0x400
+#define OMAP_ABE_D_BT_DL_FIFO_SIZE 0x1E0
+
+#define OMAP_ABE_D_BT_UL_FIFO_ADDR 0x600
+#define OMAP_ABE_D_BT_UL_FIFO_SIZE 0x1E0
+
+#define OMAP_ABE_D_MM_EXT_OUT_FIFO_ADDR 0x800
+#define OMAP_ABE_D_MM_EXT_OUT_FIFO_SIZE 0x1E0
+
+#define OMAP_ABE_D_MM_EXT_IN_FIFO_ADDR 0xA00
+#define OMAP_ABE_D_MM_EXT_IN_FIFO_SIZE 0x1E0
+
+#define OMAP_ABE_D_MM_UL2_FIFO_ADDR 0xC00
+#define OMAP_ABE_D_MM_UL2_FIFO_SIZE 0x1E0
+
+#define OMAP_ABE_D_VX_UL_FIFO_ADDR 0xE00
+#define OMAP_ABE_D_VX_UL_FIFO_SIZE 0x1E0
+
+#define OMAP_ABE_D_VX_DL_FIFO_ADDR 0x1000
+#define OMAP_ABE_D_VX_DL_FIFO_SIZE 0x1E0
+
+#define OMAP_ABE_D_DMIC_UL_FIFO_ADDR 0x1200
+#define OMAP_ABE_D_DMIC_UL_FIFO_SIZE 0x1E0
+
+#define OMAP_ABE_D_MM_UL_FIFO_ADDR 0x1400
+#define OMAP_ABE_D_MM_UL_FIFO_SIZE 0x1E0
+
+#define OMAP_ABE_D_MM_DL_FIFO_ADDR 0x1600
+#define OMAP_ABE_D_MM_DL_FIFO_SIZE 0x1E0
+
+#define OMAP_ABE_D_TONES_DL_FIFO_ADDR 0x1800
+#define OMAP_ABE_D_TONES_DL_FIFO_SIZE 0x1E0
+
+#define OMAP_ABE_D_VIB_DL_FIFO_ADDR 0x1A00
+#define OMAP_ABE_D_VIB_DL_FIFO_SIZE 0x1E0
+
+#define OMAP_ABE_D_MCPDM_DL_FIFO_ADDR 0x1C00
+#define OMAP_ABE_D_MCPDM_DL_FIFO_SIZE 0x1E0
+
+#define OMAP_ABE_D_MCPDM_UL_FIFO_ADDR 0x1E00
+#define OMAP_ABE_D_MCPDM_UL_FIFO_SIZE 0x1E0
+
+#define OMAP_ABE_D_DEBUG_FIFO_ADDR 0x1FE0
+#define OMAP_ABE_D_DEBUG_FIFO_SIZE 0x60
+
+#define OMAP_ABE_D_DEBUG_FIFO_HAL_ADDR 0x2040
+#define OMAP_ABE_D_DEBUG_FIFO_HAL_SIZE 0x20
+
+#define OMAP_ABE_D_IODESCR_ADDR 0x2060
+#define OMAP_ABE_D_IODESCR_SIZE 0x280
+
+#define OMAP_ABE_D_ZERO_ADDR 0x22E0
+#define OMAP_ABE_D_ZERO_SIZE 0x4
+
+#define OMAP_ABE_DBG_TRACE1_ADDR 0x22E4
+#define OMAP_ABE_DBG_TRACE1_SIZE 0x1
+
+#define OMAP_ABE_DBG_TRACE2_ADDR 0x22E5
+#define OMAP_ABE_DBG_TRACE2_SIZE 0x1
+
+#define OMAP_ABE_DBG_TRACE3_ADDR 0x22E6
+#define OMAP_ABE_DBG_TRACE3_SIZE 0x1
+
+#define OMAP_ABE_D_MULTIFRAME_ADDR 0x22E8
+#define OMAP_ABE_D_MULTIFRAME_SIZE 0x190
+
+#define OMAP_ABE_D_TASKSLIST_ADDR 0x2478
+#define OMAP_ABE_D_TASKSLIST_SIZE 0x800
+
+#define OMAP_ABE_D_IDLETASK_ADDR 0x2C78
+#define OMAP_ABE_D_IDLETASK_SIZE 0x2
+
+#define OMAP_ABE_D_TYPELENGTHCHECK_ADDR 0x2C7A
+#define OMAP_ABE_D_TYPELENGTHCHECK_SIZE 0x2
+
+#define OMAP_ABE_D_MAXTASKBYTESINSLOT_ADDR 0x2C7C
+#define OMAP_ABE_D_MAXTASKBYTESINSLOT_SIZE 0x2
+
+#define OMAP_ABE_D_REWINDTASKBYTES_ADDR 0x2C7E
+#define OMAP_ABE_D_REWINDTASKBYTES_SIZE 0x2
+
+#define OMAP_ABE_D_PCURRENTTASK_ADDR 0x2C80
+#define OMAP_ABE_D_PCURRENTTASK_SIZE 0x2
+
+#define OMAP_ABE_D_PFASTLOOPBACK_ADDR 0x2C82
+#define OMAP_ABE_D_PFASTLOOPBACK_SIZE 0x2
+
+#define OMAP_ABE_D_PNEXTFASTLOOPBACK_ADDR 0x2C84
+#define OMAP_ABE_D_PNEXTFASTLOOPBACK_SIZE 0x4
+
+#define OMAP_ABE_D_PPCURRENTTASK_ADDR 0x2C88
+#define OMAP_ABE_D_PPCURRENTTASK_SIZE 0x2
+
+#define OMAP_ABE_D_SLOTCOUNTER_ADDR 0x2C8C
+#define OMAP_ABE_D_SLOTCOUNTER_SIZE 0x2
+
+#define OMAP_ABE_D_LOOPCOUNTER_ADDR 0x2C90
+#define OMAP_ABE_D_LOOPCOUNTER_SIZE 0x4
+
+#define OMAP_ABE_D_REWINDFLAG_ADDR 0x2C94
+#define OMAP_ABE_D_REWINDFLAG_SIZE 0x2
+
+#define OMAP_ABE_D_SLOT23_CTRL_ADDR 0x2C98
+#define OMAP_ABE_D_SLOT23_CTRL_SIZE 0x4
+
+#define OMAP_ABE_D_MCUIRQFIFO_ADDR 0x2C9C
+#define OMAP_ABE_D_MCUIRQFIFO_SIZE 0x40
+
+#define OMAP_ABE_D_PINGPONGDESC_ADDR 0x2CDC
+#define OMAP_ABE_D_PINGPONGDESC_SIZE 0x18
+
+#define OMAP_ABE_D_PP_MCU_IRQ_ADDR 0x2CF4
+#define OMAP_ABE_D_PP_MCU_IRQ_SIZE 0x2
+
+#define OMAP_ABE_D_CTRLPORTFIFO_ADDR 0x2D00
+#define OMAP_ABE_D_CTRLPORTFIFO_SIZE 0x10
+
+#define OMAP_ABE_D_IDLE_STATE_ADDR 0x2D10
+#define OMAP_ABE_D_IDLE_STATE_SIZE 0x4
+
+#define OMAP_ABE_D_STOP_REQUEST_ADDR 0x2D14
+#define OMAP_ABE_D_STOP_REQUEST_SIZE 0x4
+
+#define OMAP_ABE_D_REF0_ADDR 0x2D18
+#define OMAP_ABE_D_REF0_SIZE 0x2
+
+#define OMAP_ABE_D_DEBUGREGISTER_ADDR 0x2D1C
+#define OMAP_ABE_D_DEBUGREGISTER_SIZE 0x8C
+
+#define OMAP_ABE_D_GCOUNT_ADDR 0x2DA8
+#define OMAP_ABE_D_GCOUNT_SIZE 0x2
+
+#define OMAP_ABE_D_DCCOUNTER_ADDR 0x2DAC
+#define OMAP_ABE_D_DCCOUNTER_SIZE 0x4
+
+#define OMAP_ABE_D_DCSUM_ADDR 0x2DB0
+#define OMAP_ABE_D_DCSUM_SIZE 0x8
+
+#define OMAP_ABE_D_FASTCOUNTER_ADDR 0x2DB8
+#define OMAP_ABE_D_FASTCOUNTER_SIZE 0x4
+
+#define OMAP_ABE_D_SLOWCOUNTER_ADDR 0x2DBC
+#define OMAP_ABE_D_SLOWCOUNTER_SIZE 0x4
+
+#define OMAP_ABE_D_AUPLINKROUTING_ADDR 0x2DC0
+#define OMAP_ABE_D_AUPLINKROUTING_SIZE 0x20
+
+#define OMAP_ABE_D_VIRTAUDIOLOOP_ADDR 0x2DE0
+#define OMAP_ABE_D_VIRTAUDIOLOOP_SIZE 0x4
+
+#define OMAP_ABE_D_ASRCVARS_DL_VX_ADDR 0x2DE4
+#define OMAP_ABE_D_ASRCVARS_DL_VX_SIZE 0x20
+
+#define OMAP_ABE_D_ASRCVARS_UL_VX_ADDR 0x2E04
+#define OMAP_ABE_D_ASRCVARS_UL_VX_SIZE 0x20
+
+#define OMAP_ABE_D_COEFADDRESSES_VX_ADDR 0x2E24
+#define OMAP_ABE_D_COEFADDRESSES_VX_SIZE 0x20
+
+#define OMAP_ABE_D_ASRCVARS_MM_EXT_IN_ADDR 0x2E44
+#define OMAP_ABE_D_ASRCVARS_MM_EXT_IN_SIZE 0x20
+
+#define OMAP_ABE_D_COEFADDRESSES_MM_ADDR 0x2E64
+#define OMAP_ABE_D_COEFADDRESSES_MM_SIZE 0x20
+
+#define OMAP_ABE_D_APS_DL1_M_THRESHOLDS_ADDR 0x2E84
+#define OMAP_ABE_D_APS_DL1_M_THRESHOLDS_SIZE 0x8
+
+#define OMAP_ABE_D_APS_DL1_M_IRQ_ADDR 0x2E8C
+#define OMAP_ABE_D_APS_DL1_M_IRQ_SIZE 0x2
+
+#define OMAP_ABE_D_APS_DL1_C_IRQ_ADDR 0x2E8E
+#define OMAP_ABE_D_APS_DL1_C_IRQ_SIZE 0x2
+
+#define OMAP_ABE_D_TRACEBUFADR_ADDR 0x2E90
+#define OMAP_ABE_D_TRACEBUFADR_SIZE 0x2
+
+#define OMAP_ABE_D_TRACEBUFOFFSET_ADDR 0x2E92
+#define OMAP_ABE_D_TRACEBUFOFFSET_SIZE 0x2
+
+#define OMAP_ABE_D_TRACEBUFLENGTH_ADDR 0x2E94
+#define OMAP_ABE_D_TRACEBUFLENGTH_SIZE 0x2
+
+#define OMAP_ABE_D_ASRCVARS_ECHO_REF_ADDR 0x2E98
+#define OMAP_ABE_D_ASRCVARS_ECHO_REF_SIZE 0x20
+
+#define OMAP_ABE_D_PEMPTY_ADDR 0x2EB8
+#define OMAP_ABE_D_PEMPTY_SIZE 0x4
+
+#define OMAP_ABE_D_APS_DL2_L_M_IRQ_ADDR 0x2EBC
+#define OMAP_ABE_D_APS_DL2_L_M_IRQ_SIZE 0x2
+
+#define OMAP_ABE_D_APS_DL2_L_C_IRQ_ADDR 0x2EBE
+#define OMAP_ABE_D_APS_DL2_L_C_IRQ_SIZE 0x2
+
+#define OMAP_ABE_D_APS_DL2_R_M_IRQ_ADDR 0x2EC0
+#define OMAP_ABE_D_APS_DL2_R_M_IRQ_SIZE 0x2
+
+#define OMAP_ABE_D_APS_DL2_R_C_IRQ_ADDR 0x2EC2
+#define OMAP_ABE_D_APS_DL2_R_C_IRQ_SIZE 0x2
+
+#define OMAP_ABE_D_APS_DL1_C_THRESHOLDS_ADDR 0x2EC4
+#define OMAP_ABE_D_APS_DL1_C_THRESHOLDS_SIZE 0x8
+
+#define OMAP_ABE_D_APS_DL2_L_M_THRESHOLDS_ADDR 0x2ECC
+#define OMAP_ABE_D_APS_DL2_L_M_THRESHOLDS_SIZE 0x8
+
+#define OMAP_ABE_D_APS_DL2_L_C_THRESHOLDS_ADDR 0x2ED4
+#define OMAP_ABE_D_APS_DL2_L_C_THRESHOLDS_SIZE 0x8
+
+#define OMAP_ABE_D_APS_DL2_R_M_THRESHOLDS_ADDR 0x2EDC
+#define OMAP_ABE_D_APS_DL2_R_M_THRESHOLDS_SIZE 0x8
+
+#define OMAP_ABE_D_APS_DL2_R_C_THRESHOLDS_ADDR 0x2EE4
+#define OMAP_ABE_D_APS_DL2_R_C_THRESHOLDS_SIZE 0x8
+
+#define OMAP_ABE_D_ECHO_REF_48_16_WRAP_ADDR 0x2EEC
+#define OMAP_ABE_D_ECHO_REF_48_16_WRAP_SIZE 0x8
+
+#define OMAP_ABE_D_ECHO_REF_48_8_WRAP_ADDR 0x2EF4
+#define OMAP_ABE_D_ECHO_REF_48_8_WRAP_SIZE 0x8
+
+#define OMAP_ABE_D_BT_UL_16_48_WRAP_ADDR 0x2EFC
+#define OMAP_ABE_D_BT_UL_16_48_WRAP_SIZE 0x8
+
+#define OMAP_ABE_D_BT_UL_8_48_WRAP_ADDR 0x2F04
+#define OMAP_ABE_D_BT_UL_8_48_WRAP_SIZE 0x8
+
+#define OMAP_ABE_D_BT_DL_48_16_WRAP_ADDR 0x2F0C
+#define OMAP_ABE_D_BT_DL_48_16_WRAP_SIZE 0x8
+
+#define OMAP_ABE_D_BT_DL_48_8_WRAP_ADDR 0x2F14
+#define OMAP_ABE_D_BT_DL_48_8_WRAP_SIZE 0x8
+
+#define OMAP_ABE_D_VX_DL_16_48_WRAP_ADDR 0x2F1C
+#define OMAP_ABE_D_VX_DL_16_48_WRAP_SIZE 0x8
+
+#define OMAP_ABE_D_VX_DL_8_48_WRAP_ADDR 0x2F24
+#define OMAP_ABE_D_VX_DL_8_48_WRAP_SIZE 0x8
+
+#define OMAP_ABE_D_VX_UL_48_16_WRAP_ADDR 0x2F2C
+#define OMAP_ABE_D_VX_UL_48_16_WRAP_SIZE 0x8
+
+#define OMAP_ABE_D_VX_UL_48_8_WRAP_ADDR 0x2F34
+#define OMAP_ABE_D_VX_UL_48_8_WRAP_SIZE 0x8
+
+#define OMAP_ABE_D_APS_DL1_IRQS_WRAP_ADDR 0x2F3C
+#define OMAP_ABE_D_APS_DL1_IRQS_WRAP_SIZE 0x8
+
+#define OMAP_ABE_D_APS_DL2_L_IRQS_WRAP_ADDR 0x2F44
+#define OMAP_ABE_D_APS_DL2_L_IRQS_WRAP_SIZE 0x8
+
+#define OMAP_ABE_D_APS_DL2_R_IRQS_WRAP_ADDR 0x2F4C
+#define OMAP_ABE_D_APS_DL2_R_IRQS_WRAP_SIZE 0x8
+
+#define OMAP_ABE_D_NEXTMULTIFRAME_ADDR 0x2F54
+#define OMAP_ABE_D_NEXTMULTIFRAME_SIZE 0x8
+
+#define OMAP_ABE_D_HW_TEST_ADDR 0x2F5C
+#define OMAP_ABE_D_HW_TEST_SIZE 0x8
+
+#define OMAP_ABE_D_TRACEBUFADR_HAL_ADDR 0x2F64
+#define OMAP_ABE_D_TRACEBUFADR_HAL_SIZE 0x4
+
+#define OMAP_ABE_D_DEBUG_HAL_TASK_ADDR 0x3000
+#define OMAP_ABE_D_DEBUG_HAL_TASK_SIZE 0x800
+
+#define OMAP_ABE_D_DEBUG_FW_TASK_ADDR 0x3800
+#define OMAP_ABE_D_DEBUG_FW_TASK_SIZE 0x100
+
+#define OMAP_ABE_D_FWMEMINIT_ADDR 0x3900
+#define OMAP_ABE_D_FWMEMINIT_SIZE 0x3C0
+
+#define OMAP_ABE_D_FWMEMINITDESCR_ADDR 0x3CC0
+#define OMAP_ABE_D_FWMEMINITDESCR_SIZE 0x10
+
+#define OMAP_ABE_D_ASRCVARS_BT_UL_ADDR 0x3CD0
+#define OMAP_ABE_D_ASRCVARS_BT_UL_SIZE 0x20
+
+#define OMAP_ABE_D_ASRCVARS_BT_DL_ADDR 0x3CF0
+#define OMAP_ABE_D_ASRCVARS_BT_DL_SIZE 0x20
+
+#define OMAP_ABE_D_BT_DL_48_8_OPP100_WRAP_ADDR 0x3D10
+#define OMAP_ABE_D_BT_DL_48_8_OPP100_WRAP_SIZE 0x8
+
+#define OMAP_ABE_D_BT_DL_48_16_OPP100_WRAP_ADDR 0x3D18
+#define OMAP_ABE_D_BT_DL_48_16_OPP100_WRAP_SIZE 0x8
+
+#define OMAP_ABE_D_PING_ADDR 0x4000
+#define OMAP_ABE_D_PING_SIZE 0x6000
+
+#define OMAP_ABE_D_PONG_ADDR 0xA000
+#define OMAP_ABE_D_PONG_SIZE 0x6000
diff --git a/sound/soc/omap/abe/abe_ext.h b/sound/soc/omap/abe/abe_ext.h
new file mode 100644
index 0000000..8fb1aac
--- /dev/null
+++ b/sound/soc/omap/abe/abe_ext.h
@@ -0,0 +1,242 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_EXT_H_
+#define _ABE_EXT_H_
+
+/*
+ * OS DEPENDENT MMU CONFIGURATION
+ */
+#define ABE_PMEM_BASE_OFFSET_MPU 0xe0000
+#define ABE_CMEM_BASE_OFFSET_MPU 0xa0000
+#define ABE_SMEM_BASE_OFFSET_MPU 0xc0000
+#define ABE_DMEM_BASE_OFFSET_MPU 0x80000
+#define ABE_ATC_BASE_OFFSET_MPU 0xf1000
+/* default base address for io_base */
+#define ABE_DEFAULT_BASE_ADDRESS_L3 0x49000000L
+#define ABE_DEFAULT_BASE_ADDRESS_L4 0x40100000L
+#define ABE_DEFAULT_BASE_ADDRESS_DEFAULT ABE_DEFAULT_BASE_ADDRESS_L3
+/*
+ * HARDWARE AND PERIPHERAL DEFINITIONS
+ */
+/* PMEM SIZE in bytes (1024 words of 64 bits: : #32bits words x 4)*/
+#define ABE_PMEM_SIZE 8192
+/* CMEM SIZE in bytes (2048 coeff : #32bits words x 4)*/
+#define ABE_CMEM_SIZE 8192
+/* SMEM SIZE in bytes (3072 stereo samples : #32bits words x 4)*/
+#define ABE_SMEM_SIZE 24576
+/* DMEM SIZE in bytes */
+#define ABE_DMEM_SIZE 65536L
+/* ATC REGISTERS SIZE in bytes */
+#define ABE_ATC_DESC_SIZE 512
+/* holds the MCU Irq signal */
+#define ABE_MCU_IRQSTATUS_RAW 0x24
+/* status : clear the IRQ */
+#define ABE_MCU_IRQSTATUS 0x28
+/* holds the DSP Irq signal */
+#define ABE_DSP_IRQSTATUS_RAW 0x4C
+/* holds the DMA req lines to the sDMA */
+#define ABE_DMASTATUS_RAW 0x84
+#define EVENT_GENERATOR_COUNTER 0x68
+/* PLL output/desired sampling rate = (32768 * 6000)/96000 */
+#define EVENT_GENERATOR_COUNTER_DEFAULT (2048-1)
+/* PLL output/desired sampling rate = (32768 * 6000)/88200 */
+#define EVENT_GENERATOR_COUNTER_44100 (2228-1)
+/* start / stop the EVENT generator */
+#define EVENT_GENERATOR_START 0x6C
+#define EVENT_GENERATOR_ON 1
+#define EVENT_GENERATOR_OFF 0
+/* selection of the EVENT generator source */
+#define EVENT_SOURCE_SELECTION 0x70
+#define EVENT_SOURCE_DMA 0
+#define EVENT_SOURCE_COUNTER 1
+/* selection of the ABE DMA req line from ATC */
+#define AUDIO_ENGINE_SCHEDULER 0x74
+#define ABE_ATC_DMIC_DMA_REQ 1
+#define ABE_ATC_MCPDMDL_DMA_REQ 2
+#define ABE_ATC_MCPDMUL_DMA_REQ 3
+/* Direction=0 means input from ABE point of view */
+#define ABE_ATC_DIRECTION_IN 0
+/* Direction=1 means output from ABE point of view */
+#define ABE_ATC_DIRECTION_OUT 1
+/*
+ * DMA requests
+ */
+/*Internal connection doesn't connect at ABE boundary */
+#define External_DMA_0 0
+/*Transmit request digital microphone */
+#define DMIC_DMA_REQ 1
+/*Multichannel PDM downlink */
+#define McPDM_DMA_DL 2
+/*Multichannel PDM uplink */
+#define McPDM_DMA_UP 3
+/*MCBSP module 1 - transmit request */
+#define MCBSP1_DMA_TX 4
+/*MCBSP module 1 - receive request */
+#define MCBSP1_DMA_RX 5
+/*MCBSP module 2 - transmit request */
+#define MCBSP2_DMA_TX 6
+/*MCBSP module 2 - receive request */
+#define MCBSP2_DMA_RX 7
+/*MCBSP module 3 - transmit request */
+#define MCBSP3_DMA_TX 8
+/*MCBSP module 3 - receive request */
+#define MCBSP3_DMA_RX 9
+/*SLIMBUS module 1 - transmit request channel 0 */
+#define SLIMBUS1_DMA_TX0 10
+/*SLIMBUS module 1 - transmit request channel 1 */
+#define SLIMBUS1_DMA_TX1 11
+/*SLIMBUS module 1 - transmit request channel 2 */
+#define SLIMBUS1_DMA_TX2 12
+/*SLIMBUS module 1 - transmit request channel 3 */
+#define SLIMBUS1_DMA_TX3 13
+/*SLIMBUS module 1 - transmit request channel 4 */
+#define SLIMBUS1_DMA_TX4 14
+/*SLIMBUS module 1 - transmit request channel 5 */
+#define SLIMBUS1_DMA_TX5 15
+/*SLIMBUS module 1 - transmit request channel 6 */
+#define SLIMBUS1_DMA_TX6 16
+/*SLIMBUS module 1 - transmit request channel 7 */
+#define SLIMBUS1_DMA_TX7 17
+/*SLIMBUS module 1 - receive request channel 0 */
+#define SLIMBUS1_DMA_RX0 18
+/*SLIMBUS module 1 - receive request channel 1 */
+#define SLIMBUS1_DMA_RX1 19
+/*SLIMBUS module 1 - receive request channel 2 */
+#define SLIMBUS1_DMA_RX2 20
+/*SLIMBUS module 1 - receive request channel 3 */
+#define SLIMBUS1_DMA_RX3 21
+/*SLIMBUS module 1 - receive request channel 4 */
+#define SLIMBUS1_DMA_RX4 22
+/*SLIMBUS module 1 - receive request channel 5 */
+#define SLIMBUS1_DMA_RX5 23
+/*SLIMBUS module 1 - receive request channel 6 */
+#define SLIMBUS1_DMA_RX6 24
+/*SLIMBUS module 1 - receive request channel 7 */
+#define SLIMBUS1_DMA_RX7 25
+/*McASP - Data transmit DMA request line */
+#define McASP1_AXEVT 26
+/*McASP - Data receive DMA request line */
+#define McASP1_AREVT 29
+/*DUMMY FIFO @@@ */
+#define _DUMMY_FIFO_ 30
+/*DMA of the Circular buffer peripheral 0 */
+#define CBPr_DMA_RTX0 32
+/*DMA of the Circular buffer peripheral 1 */
+#define CBPr_DMA_RTX1 33
+/*DMA of the Circular buffer peripheral 2 */
+#define CBPr_DMA_RTX2 34
+/*DMA of the Circular buffer peripheral 3 */
+#define CBPr_DMA_RTX3 35
+/*DMA of the Circular buffer peripheral 4 */
+#define CBPr_DMA_RTX4 36
+/*DMA of the Circular buffer peripheral 5 */
+#define CBPr_DMA_RTX5 37
+/*DMA of the Circular buffer peripheral 6 */
+#define CBPr_DMA_RTX6 38
+/*DMA of the Circular buffer peripheral 7 */
+#define CBPr_DMA_RTX7 39
+/*
+ * ATC DESCRIPTORS - DESTINATIONS
+ */
+#define DEST_DMEM_access 0x00
+#define DEST_MCBSP1_ TX 0x01
+#define DEST_MCBSP2_ TX 0x02
+#define DEST_MCBSP3_TX 0x03
+#define DEST_SLIMBUS1_TX0 0x04
+#define DEST_SLIMBUS1_TX1 0x05
+#define DEST_SLIMBUS1_TX2 0x06
+#define DEST_SLIMBUS1_TX3 0x07
+#define DEST_SLIMBUS1_TX4 0x08
+#define DEST_SLIMBUS1_TX5 0x09
+#define DEST_SLIMBUS1_TX6 0x0A
+#define DEST_SLIMBUS1_TX7 0x0B
+#define DEST_MCPDM_DL 0x0C
+#define DEST_MCASP_TX0 0x0D
+#define DEST_MCASP_TX1 0x0E
+#define DEST_MCASP_TX2 0x0F
+#define DEST_MCASP_TX3 0x10
+#define DEST_EXTPORT0 0x11
+#define DEST_EXTPORT1 0x12
+#define DEST_EXTPORT2 0x13
+#define DEST_EXTPORT3 0x14
+#define DEST_MCPDM_ON 0x15
+#define DEST_CBP_CBPr 0x3F
+/*
+ * ATC DESCRIPTORS - SOURCES
+ */
+#define SRC_DMEM_access 0x0
+#define SRC_MCBSP1_ RX 0x01
+#define SRC_MCBSP2_RX 0x02
+#define SRC_MCBSP3_RX 0x03
+#define SRC_SLIMBUS1_RX0 0x04
+#define SRC_SLIMBUS1_RX1 0x05
+#define SRC_SLIMBUS1_RX2 0x06
+#define SRC_SLIMBUS1_RX3 0x07
+#define SRC_SLIMBUS1_RX4 0x08
+#define SRC_SLIMBUS1_RX5 0x09
+#define SRC_SLIMBUS1_RX6 0x0A
+#define SRC_SLIMBUS1_RX7 0x0B
+#define SRC_DMIC_UP 0x0C
+#define SRC_MCPDM_UP 0x0D
+#define SRC_MCASP_RX0 0x0E
+#define SRC_MCASP_RX1 0x0F
+#define SRC_MCASP_RX2 0x10
+#define SRC_MCASP_RX3 0x11
+#define SRC_CBP_CBPr 0x3F
+#endif/* _ABE_EXT_H_ */
diff --git a/sound/soc/omap/abe/abe_firmware.c b/sound/soc/omap/abe/abe_firmware.c
new file mode 100644
index 0000000..b6b3d4d
--- /dev/null
+++ b/sound/soc/omap/abe/abe_firmware.c
@@ -0,0 +1,24122 @@
+0x00009110, /* VERSION NUMBER */
+0x00002000, /* PMEM LENGTH IN BYTES */
+0x000013E4, /* CMEM LENGTH IN BYTES */
+0x00010000, /* DMEM LENGTH IN BYTES */
+0x000044F0, /* SMEM LENGTH IN BYTES */
+0x1600200f,
+0x0a000670,
+0x08200000,
+0x08200000,
+0x07800000,
+0x1602d1ce,
+0x014000e0,
+0x014000e1,
+0x014000e2,
+0x014000e3,
+0x014000e4,
+0x014000e5,
+0x014000e6,
+0x014000e7,
+0x014000e8,
+0x014000e9,
+0x014000ea,
+0x014000eb,
+0x014000ec,
+0x014000ed,
+0x014000ef,
+0x014000ef,
+0x144000e4,
+0x9e000000,
+0x0a200c40,
+0x9e000040,
+0x0a200c40,
+0x9e000080,
+0x0a200c40,
+0x9e0000c0,
+0x0a200c40,
+0x9e080000,
+0x0a200c40,
+0x9e080100,
+0x0a200c40,
+0x9e080200,
+0x0a200c40,
+0x9e080300,
+0x0a200c40,
+0x9e080400,
+0x0a200c40,
+0x9e080500,
+0x0a200c40,
+0x9e080600,
+0x0a200c40,
+0x9e080700,
+0x0a200c40,
+0x9c050800,
+0x0a200c40,
+0x16000010,
+0x16000001,
+0x17000102,
+0x01400042,
+0x17800103,
+0x01400043,
+0x98020000,
+0x9d0c8118,
+0x07800000,
+0x9f16001a,
+0x9f12021a,
+0x9f12031a,
+0x9f12051a,
+0x98800380,
+0x9d0c8118,
+0x08200000,
+0x9d0c8118,
+0x07800000,
+0x9f15001a,
+0x9f11041a,
+0x98800410,
+0x9d0c8118,
+0x08200000,
+0x400002c0,
+0x048002ff,
+0x000000c5,
+0x000004c6,
+0x9c028000,
+0x400006c7,
+0x12000155,
+0x013ffefe,
+0xc00008c4,
+0x1e080000,
+0x020005de,
+0x00000ac3,
+0xdc02b160,
+0x04c3ff2d,
+0xdc01ba70,
+0x128002dd,
+0xdc02a440,
+0x048fffdd,
+0x9c061830,
+0x0b200000,
+0x003ffefe,
+0x000002c4,
+0x400004c5,
+0x048ffeff,
+0x000006c6,
+0x000008c7,
+0x9d02a040,
+0x9d02a950,
+0x9d01b260,
+0x9d02bc70,
+0x08200000,
+0x1602c7c6,
+0x00000068,
+0x16003fc5,
+0x01000058,
+0x1602c88a,
+0x000000a9,
+0x16003fc6,
+0x00000068,
+0x0400089b,
+0x4000009c,
+0x1602c80e,
+0x410000ec,
+0x0600000c,
+0x1600274d,
+0x0a800870,
+0x1602e903,
+0x00000030,
+0x00000231,
+0x00000435,
+0x04800211,
+0x04400511,
+0x1602c944,
+0x0000004e,
+0x0300010e,
+0x04800211,
+0x04400511,
+0x0300010c,
+0x04800211,
+0x04400511,
+0x03000109,
+0x01000231,
+0x0a200480,
+0x04800299,
+0x410000a9,
+0x05c00b90,
+0x4ac00700,
+0x04a01085,
+0x1602c8c4,
+0x40000047,
+0x1602c94e,
+0x04200599,
+0x400000e1,
+0x04800177,
+0x010000a9,
+0x41000047,
+0x04a00111,
+0x410000e1,
+0x06000001,
+0x4aa00a50,
+0x1602c90d,
+0x400000d6,
+0x16022e89,
+0x400002d7,
+0x04800166,
+0x410000a9,
+0x04900077,
+0x010000d6,
+0x010002d7,
+0x1602c7c6,
+0x00000068,
+0x16003fc5,
+0x01000058,
+0x1600c005,
+0x1602d141,
+0x16000002,
+0x40000011,
+0x1602d100,
+0x9e0e0550,
+0xdd140530,
+0x160ffff4,
+0x41000002,
+0x06000001,
+0x08400000,
+0x01000004,
+0x9d140550,
+0x0a8006b0,
+0x0a000a50,
+0x048006ff,
+0x013ffafb,
+0x013ffcfc,
+0x413ffefe,
+0x04a0020b,
+0x004002bc,
+0x0600000c,
+0x1600274d,
+0x0a800bf0,
+0x0a200480,
+0x0a000b90,
+0x003ffefe,
+0x003ffcfc,
+0x003ffafb,
+0x048ffaff,
+0x08200000,
+0x07800000,
+0x01400040,
+0x01400041,
+0x01400042,
+0x01400043,
+0x08200000,
+0x160004a4,
+0x160004b5,
+0x160004c6,
+0x16000007,
+0x9c032040,
+0x9c032950,
+0x9c033260,
+0x9e0f0070,
+0x9e0f0170,
+0x9e0f0270,
+0x9d032040,
+0x9d032950,
+0x9d033260,
+0x08200000,
+0x9f158048,
+0x07800000,
+0x07800000,
+0x9d088118,
+0x98800d80,
+0x08200000,
+0x9f158048,
+0x9f040040,
+0x07800000,
+0x9f03fc10,
+0x07800000,
+0x07800000,
+0x07800000,
+0x9d188148,
+0x98800de0,
+0x08200000,
+0x9f158048,
+0x07800000,
+0x07800000,
+0x9d188148,
+0x9d188108,
+0x98800e80,
+0x08200000,
+0x9f158048,
+0x07800000,
+0x07800000,
+0x9d0e0040,
+0x07800000,
+0x07800000,
+0x9d1e8148,
+0x9d1e8108,
+0x98800ef0,
+0x08200000,
+0x9f158018,
+0x9f040010,
+0x07800000,
+0x9f03fc10,
+0x07800000,
+0x07800000,
+0x07800000,
+0x9d0e0010,
+0x07800000,
+0x07800000,
+0x9d1e8108,
+0x98800f90,
+0x08200000,
+0x9c080048,
+0x9f1d0010,
+0x07800000,
+0x07800000,
+0x9d0c8118,
+0x98801060,
+0x08200000,
+0x9c180028,
+0x9f1d0010,
+0x07800000,
+0x07800000,
+0x9d0c8108,
+0x988010d0,
+0x08200000,
+0x9c180068,
+0x9c180028,
+0x9f1d0010,
+0x07800000,
+0x07800000,
+0x9d0c8148,
+0x98801140,
+0x08200000,
+0x9c1e0048,
+0x9c1e0008,
+0x9f1d0010,
+0x07800000,
+0x07800000,
+0x9d0c8148,
+0x988011c0,
+0x08200000,
+0x9c1e0008,
+0x9f1d0010,
+0x07800000,
+0x07800000,
+0x9d0c8108,
+0x98801240,
+0x08200000,
+0x160004a4,
+0x160004b5,
+0x160004c6,
+0x160000bd,
+0x9c032340,
+0x9c032c50,
+0x9c033560,
+0x9c180028,
+0x9c180068,
+0x9f1d0010,
+0x9c1800a8,
+0x9c1800e8,
+0x9f1d00b0,
+0x07800000,
+0x9d0c8318,
+0x9d0c84b8,
+0x9c180028,
+0x9c180068,
+0x9f1d0010,
+0x07800000,
+0x07800000,
+0x9d0c8518,
+0x98801320,
+0x9d032340,
+0x9d032c50,
+0x9d033560,
+0x08200000,
+0x16000504,
+0x16000515,
+0x16000526,
+0x9c03a440,
+0x9c03ad50,
+0x9c03b660,
+0x160000bd,
+0x9f158418,
+0x9f1585b8,
+0x07800000,
+0x9d188108,
+0x9d188148,
+0x9d188188,
+0x9c0c0618,
+0x07800000,
+0x9d1881c8,
+0x9d188108,
+0x9d188148,
+0x988014d0,
+0x9d032440,
+0x9d032d50,
+0x9d033660,
+0x08200000,
+0x1600000d,
+0x9e0f00d0,
+0x00800e0d,
+0x9f158038,
+0x07800000,
+0x04a002dd,
+0x9d188108,
+0x9f158038,
+0x07800000,
+0x98801630,
+0x9d188108,
+0x08200000,
+0x9e088100,
+0x07800000,
+0x07800000,
+0x12800277,
+0x04c0ff77,
+0x04a00174,
+0x12800266,
+0x04c0ff66,
+0x04000645,
+0x060ffff4,
+0x17000454,
+0x12000244,
+0x9e0f0140,
+0x07800000,
+0x07800000,
+0x9c0c0118,
+0x07800000,
+0x07800000,
+0x9d0c8118,
+0x988017b0,
+0x08200000,
+0x08200000,
+0x08200000,
+0x08200000,
+0x9c038600,
+0x07800000,
+0x07800000,
+0x9c180770,
+0xdc100348,
+0x160fff05,
+0x9f000810,
+0x9f118412,
+0x9f001010,
+0x9f002810,
+0x9c0c00b8,
+0x160ffd80,
+0x9d0c8410,
+0x9f1d8012,
+0x9f001810,
+0x9f0400d0,
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diff --git a/sound/soc/omap/abe/abe_functionsid.h b/sound/soc/omap/abe/abe_functionsid.h
new file mode 100644
index 0000000..a2bf7dc
--- /dev/null
+++ b/sound/soc/omap/abe/abe_functionsid.h
@@ -0,0 +1,113 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_FUNCTIONSID_H_
+#define _ABE_FUNCTIONSID_H_
+/*
+ * TASK function ID definitions
+ */
+#define C_ABE_FW_FUNCTION_IIR 0
+#define C_ABE_FW_FUNCTION_monoToStereoPack 1
+#define C_ABE_FW_FUNCTION_stereoToMonoSplit 2
+#define C_ABE_FW_FUNCTION_decimator 3
+#define C_ABE_FW_FUNCTION_OS0Fill 4
+#define C_ABE_FW_FUNCTION_mixer2 5
+#define C_ABE_FW_FUNCTION_mixer4 6
+#define C_ABE_FW_FUNCTION_inplaceGain 7
+#define C_ABE_FW_FUNCTION_StreamRouting 8
+#define C_ABE_FW_FUNCTION_gainConverge 9
+#define C_ABE_FW_FUNCTION_dualIir 10
+#define C_ABE_FW_FUNCTION_IO_DL_pp 11
+#define C_ABE_FW_FUNCTION_IO_generic 12
+#define C_ABE_FW_FUNCTION_irq_fifo_debug 13
+#define C_ABE_FW_FUNCTION_synchronize_pointers 14
+#define C_ABE_FW_FUNCTION_VIBRA2 15
+#define C_ABE_FW_FUNCTION_VIBRA1 16
+#define C_ABE_FW_FUNCTION_APS_core 17
+#define C_ABE_FW_FUNCTION_IIR_SRC_MIC 18
+#define C_ABE_FW_FUNCTION_wrappers 19
+#define C_ABE_FW_FUNCTION_ASRC_DL_wrapper 20
+#define C_ABE_FW_FUNCTION_ASRC_UL_wrapper 21
+#define C_ABE_FW_FUNCTION_mem_init 22
+#define C_ABE_FW_FUNCTION_debug_vx_asrc 23
+#define C_ABE_FW_FUNCTION_IIR_SRC2 24
+/*
+ * COPY function ID definitions
+ */
+#define NULL_COPY_CFPID 0
+#define S2D_STEREO_16_16_CFPID 1
+#define S2D_MONO_MSB_CFPID 2
+#define S2D_STEREO_MSB_CFPID 3
+#define S2D_STEREO_RSHIFTED_16_CFPID 4
+#define S2D_MONO_RSHIFTED_16_CFPID 5
+#define D2S_STEREO_16_16_CFPID 6
+#define D2S_MONO_MSB_CFPID 7
+#define D2S_MONO_RSHIFTED_16_CFPID 8
+#define D2S_STEREO_RSHIFTED_16_CFPID 9
+#define D2S_STEREO_MSB_CFPID 10
+#define COPY_DMIC_CFPID 11
+#define COPY_MCPDM_DL_CFPID 12
+#define COPY_MM_UL_CFPID 13
+#define SPLIT_SMEM_CFPID 14
+#define MERGE_SMEM_CFPID 15
+#define SPLIT_TDM_CFPID 16
+#define MERGE_TDM_CFPID 17
+#define ROUTE_MM_UL_CFPID 18
+#define IO_IP_CFPID 19
+#define COPY_UNDERFLOW_CFPID 20
+#endif /* _ABE_FUNCTIONSID_H_ */
diff --git a/sound/soc/omap/abe/abe_fw.h b/sound/soc/omap/abe/abe_fw.h
new file mode 100644
index 0000000..a29dbb3
--- /dev/null
+++ b/sound/soc/omap/abe/abe_fw.h
@@ -0,0 +1,214 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_FW_H_
+#define _ABE_FW_H_
+
+#include "abe_cm_addr.h"
+#include "abe_sm_addr.h"
+#include "abe_dm_addr.h"
+#include "abe_typedef.h"
+/*
+ * GLOBAL DEFINITION
+ */
+/* one scheduler loop = 4kHz = 12 samples at 48kHz */
+#define FW_SCHED_LOOP_FREQ 4000
+/* one scheduler loop = 4kHz = 12 samples at 48kHz */
+#define FW_SCHED_LOOP_FREQ_DIV1000 (FW_SCHED_LOOP_FREQ/1000)
+#define EVENT_FREQUENCY 96000
+#define SLOTS_IN_SCHED_LOOP (96000/FW_SCHED_LOOP_FREQ)
+#define SCHED_LOOP_8kHz (8000/FW_SCHED_LOOP_FREQ)
+#define SCHED_LOOP_16kHz (16000/FW_SCHED_LOOP_FREQ)
+#define SCHED_LOOP_24kHz (24000/FW_SCHED_LOOP_FREQ)
+#define SCHED_LOOP_48kHz (48000/FW_SCHED_LOOP_FREQ)
+#define TASKS_IN_SLOT 8
+/*
+ * DMEM AREA - SCHEDULER
+ */
+#define dmem_mm_trace OMAP_ABE_D_DEBUG_FIFO_ADDR
+#define dmem_mm_trace_size ((OMAP_ABE_D_DEBUG_FIFO_SIZE)/4)
+#define ATC_SIZE 8 /* 8 bytes per descriptors */
+struct omap_abe_atc_desc {
+ unsigned rdpt:7; /* first 32bits word of the descriptor */
+ unsigned reserved0:1;
+ unsigned cbsize:7;
+ unsigned irqdest:1;
+ unsigned cberr:1;
+ unsigned reserved1:5;
+ unsigned cbdir:1;
+ unsigned nw:1;
+ unsigned wrpt:7;
+ unsigned reserved2:1;
+ unsigned badd:12; /* second 32bits word of the descriptor */
+ unsigned iter:7; /* iteration field overlaps 16-bit boundary */
+ unsigned srcid:6;
+ unsigned destid:6;
+ unsigned desen:1;
+};
+/*
+ * Infinite counter incremented on each sheduler periods (~250 us)
+ * uint16 dmem_debug_time_stamp
+ */
+#define dmem_debug_time_stamp OMAP_ABE_D_LOOPCOUNTER_ADDR
+/*
+ * ATC BUFFERS + IO TASKS SMEM buffers
+ */
+#define dmem_dmic OMAP_ABE_D_DMIC_UL_FIFO_ADDR
+#define dmem_dmic_size (OMAP_ABE_D_DMIC_UL_FIFO_SIZE/4)
+#define dmem_amic OMAP_ABE_D_MCPDM_UL_FIFO_ADDR
+#define dmem_amic_size (OMAP_ABE_D_MCPDM_UL_FIFO_SIZE/4)
+#define smem_amic AMIC_96_labelID
+#define dmem_mcpdm OMAP_ABE_D_MCPDM_DL_FIFO_ADDR
+#define dmem_mcpdm_size (OMAP_ABE_D_MCPDM_DL_FIFO_SIZE/4)
+#define dmem_mm_ul OMAP_ABE_D_MM_UL_FIFO_ADDR
+#define dmem_mm_ul_size (OMAP_ABE_D_MM_UL_FIFO_SIZE/4)
+/* managed directly by the router */
+#define smem_mm_ul MM_UL_labelID
+#define dmem_mm_ul2 OMAP_ABE_D_MM_UL2_FIFO_ADDR
+#define dmem_mm_ul2_size (OMAP_ABE_D_MM_UL2_FIFO_SIZE/4)
+/* managed directly by the router */
+#define smem_mm_ul2 MM_UL2_labelID
+#define dmem_mm_dl OMAP_ABE_D_MM_DL_FIFO_ADDR
+#define dmem_mm_dl_size (OMAP_ABE_D_MM_DL_FIFO_SIZE/4)
+#define smem_mm_dl MM_DL_labelID
+#define dmem_vx_dl OMAP_ABE_D_VX_DL_FIFO_ADDR
+#define dmem_vx_dl_size (OMAP_ABE_D_VX_DL_FIFO_SIZE/4)
+#define smem_vx_dl IO_VX_DL_ASRC_labelID /* Voice_16k_DL_labelID */
+#define dmem_vx_ul OMAP_ABE_D_VX_UL_FIFO_ADDR
+#define dmem_vx_ul_size (OMAP_ABE_D_VX_UL_FIFO_SIZE/4)
+#define smem_vx_ul Voice_8k_UL_labelID
+#define dmem_tones_dl OMAP_ABE_D_TONES_DL_FIFO_ADDR
+#define dmem_tones_dl_size (OMAP_ABE_D_TONES_DL_FIFO_SIZE/4)
+#define smem_tones_dl Tones_labelID
+#define dmem_vib_dl OMAP_ABE_D_VIB_DL_FIFO_ADDR
+#define dmem_vib_dl_size (OMAP_ABE_D_VIB_DL_FIFO_SIZE/4)
+#define smem_vib IO_VIBRA_DL_labelID
+#define dmem_mm_ext_out OMAP_ABE_D_MM_EXT_OUT_FIFO_ADDR
+#define dmem_mm_ext_out_size (OMAP_ABE_D_MM_EXT_OUT_FIFO_SIZE/4)
+#define smem_mm_ext_out DL1_GAIN_out_labelID
+#define dmem_mm_ext_in OMAP_ABE_D_MM_EXT_IN_FIFO_ADDR
+#define dmem_mm_ext_in_size (OMAP_ABE_D_MM_EXT_IN_FIFO_SIZE/4)
+/*IO_MM_EXT_IN_ASRC_labelID ASRC input buffer, size 40 */
+#define smem_mm_ext_in_opp100 IO_MM_EXT_IN_ASRC_labelID
+/* at OPP 50 without ASRC */
+#define smem_mm_ext_in_opp50 MM_EXT_IN_labelID
+#define dmem_bt_vx_dl OMAP_ABE_D_BT_DL_FIFO_ADDR
+#define dmem_bt_vx_dl_size (OMAP_ABE_D_BT_DL_FIFO_SIZE/4)
+#define smem_bt_vx_dl_opp50 BT_DL_8k_labelID
+/*BT_DL_8k_opp100_labelID ASRC output buffer, size 40 */
+#define smem_bt_vx_dl_opp100 BT_DL_8k_opp100_labelID
+#define dmem_bt_vx_ul OMAP_ABE_D_BT_UL_FIFO_ADDR
+#define dmem_bt_vx_ul_size (OMAP_ABE_D_BT_UL_FIFO_SIZE/4)
+#define smem_bt_vx_ul_opp50 BT_UL_8k_labelID
+/*IO_BT_UL_ASRC_labelID ASRC input buffer, size 40 */
+#define smem_bt_vx_ul_opp100 IO_BT_UL_ASRC_labelID
+/*
+ * SMEM AREA
+ */
+/*
+ * GAIN SMEM on PORT
+ * int32 smem_G0 [18] : desired gain on the ports
+ * format of G0 = 6 bits left shifted desired gain in linear 24bits format
+ * int24 stereo G0 [18] = G0
+ * int24 stereo GI [18] current value of the gain in the same format of G0
+ * List of smoothed gains :
+ * 6 DMIC 0 1 2 3 4 5
+ * 2 AMIC L R
+ * 4 PORT1/2_RX L R
+ * 2 MM_EXT L R
+ * 2 MM_VX_DL L R
+ * 2 IHF L R
+ * ---------------
+ * 18 = TOTAL
+ */
+/*
+ * COEFFICIENTS AREA
+ */
+/*
+ * delay coefficients used in the IIR-1 filters
+ * int24 cmem_gain_delay_iir1[9 x 2] (a, (1-a))
+ *
+ * 3 for 6 DMIC 0 1 2 3 4 5
+ * 1 for 2 AMIC L R
+ * 2 for 4 PORT1/2_RX L R
+ * 1 for 2 MM_EXT L R
+ * 1 for 2 MM_VX_DL L R
+ * 1 for 2 IHF L R
+ */
+/*
+ * gain controls
+ */
+#define GAIN_LEFT_OFFSET 0
+#define GAIN_RIGHT_OFFSET 1
+/* stereo gains */
+#define dmic1_gains_offset 0
+#define dmic2_gains_offset 2
+#define dmic3_gains_offset 4
+#define amic_gains_offset 6
+#define dl1_gains_offset 8
+#define dl2_gains_offset 10
+#define splitters_gains_offset 12
+#define mixer_dl1_offset 14
+#define mixer_dl2_offset 18
+#define mixer_echo_offset 22
+#define mixer_sdt_offset 24
+#define mixer_vxrec_offset 26
+#define mixer_audul_offset 30
+#define btul_gains_offset 34
+
+#endif/* _ABE_FW_H_ */
diff --git a/sound/soc/omap/abe/abe_gain.c b/sound/soc/omap/abe/abe_gain.c
new file mode 100644
index 0000000..a3d2b07
--- /dev/null
+++ b/sound/soc/omap/abe/abe_gain.c
@@ -0,0 +1,803 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include "abe_dbg.h"
+#include "abe.h"
+#include "abe_gain.h"
+#include "abe_mem.h"
+
+/*
+ * ABE CONST AREA FOR PARAMETERS TRANSLATION
+ */
+#define min_mdb (-12000)
+#define max_mdb (3000)
+#define sizeof_db2lin_table (1 + ((max_mdb - min_mdb)/100))
+
+const u32 abe_db2lin_table[sizeof_db2lin_table] = {
+ 0x00000000, /* SMEM coding of -120 dB */
+ 0x00000000, /* SMEM coding of -119 dB */
+ 0x00000000, /* SMEM coding of -118 dB */
+ 0x00000000, /* SMEM coding of -117 dB */
+ 0x00000000, /* SMEM coding of -116 dB */
+ 0x00000000, /* SMEM coding of -115 dB */
+ 0x00000000, /* SMEM coding of -114 dB */
+ 0x00000000, /* SMEM coding of -113 dB */
+ 0x00000000, /* SMEM coding of -112 dB */
+ 0x00000000, /* SMEM coding of -111 dB */
+ 0x00000000, /* SMEM coding of -110 dB */
+ 0x00000000, /* SMEM coding of -109 dB */
+ 0x00000001, /* SMEM coding of -108 dB */
+ 0x00000001, /* SMEM coding of -107 dB */
+ 0x00000001, /* SMEM coding of -106 dB */
+ 0x00000001, /* SMEM coding of -105 dB */
+ 0x00000001, /* SMEM coding of -104 dB */
+ 0x00000001, /* SMEM coding of -103 dB */
+ 0x00000002, /* SMEM coding of -102 dB */
+ 0x00000002, /* SMEM coding of -101 dB */
+ 0x00000002, /* SMEM coding of -100 dB */
+ 0x00000002, /* SMEM coding of -99 dB */
+ 0x00000003, /* SMEM coding of -98 dB */
+ 0x00000003, /* SMEM coding of -97 dB */
+ 0x00000004, /* SMEM coding of -96 dB */
+ 0x00000004, /* SMEM coding of -95 dB */
+ 0x00000005, /* SMEM coding of -94 dB */
+ 0x00000005, /* SMEM coding of -93 dB */
+ 0x00000006, /* SMEM coding of -92 dB */
+ 0x00000007, /* SMEM coding of -91 dB */
+ 0x00000008, /* SMEM coding of -90 dB */
+ 0x00000009, /* SMEM coding of -89 dB */
+ 0x0000000A, /* SMEM coding of -88 dB */
+ 0x0000000B, /* SMEM coding of -87 dB */
+ 0x0000000D, /* SMEM coding of -86 dB */
+ 0x0000000E, /* SMEM coding of -85 dB */
+ 0x00000010, /* SMEM coding of -84 dB */
+ 0x00000012, /* SMEM coding of -83 dB */
+ 0x00000014, /* SMEM coding of -82 dB */
+ 0x00000017, /* SMEM coding of -81 dB */
+ 0x0000001A, /* SMEM coding of -80 dB */
+ 0x0000001D, /* SMEM coding of -79 dB */
+ 0x00000021, /* SMEM coding of -78 dB */
+ 0x00000025, /* SMEM coding of -77 dB */
+ 0x00000029, /* SMEM coding of -76 dB */
+ 0x0000002E, /* SMEM coding of -75 dB */
+ 0x00000034, /* SMEM coding of -74 dB */
+ 0x0000003A, /* SMEM coding of -73 dB */
+ 0x00000041, /* SMEM coding of -72 dB */
+ 0x00000049, /* SMEM coding of -71 dB */
+ 0x00000052, /* SMEM coding of -70 dB */
+ 0x0000005D, /* SMEM coding of -69 dB */
+ 0x00000068, /* SMEM coding of -68 dB */
+ 0x00000075, /* SMEM coding of -67 dB */
+ 0x00000083, /* SMEM coding of -66 dB */
+ 0x00000093, /* SMEM coding of -65 dB */
+ 0x000000A5, /* SMEM coding of -64 dB */
+ 0x000000B9, /* SMEM coding of -63 dB */
+ 0x000000D0, /* SMEM coding of -62 dB */
+ 0x000000E9, /* SMEM coding of -61 dB */
+ 0x00000106, /* SMEM coding of -60 dB */
+ 0x00000126, /* SMEM coding of -59 dB */
+ 0x0000014A, /* SMEM coding of -58 dB */
+ 0x00000172, /* SMEM coding of -57 dB */
+ 0x0000019F, /* SMEM coding of -56 dB */
+ 0x000001D2, /* SMEM coding of -55 dB */
+ 0x0000020B, /* SMEM coding of -54 dB */
+ 0x0000024A, /* SMEM coding of -53 dB */
+ 0x00000292, /* SMEM coding of -52 dB */
+ 0x000002E2, /* SMEM coding of -51 dB */
+ 0x0000033C, /* SMEM coding of -50 dB */
+ 0x000003A2, /* SMEM coding of -49 dB */
+ 0x00000413, /* SMEM coding of -48 dB */
+ 0x00000492, /* SMEM coding of -47 dB */
+ 0x00000521, /* SMEM coding of -46 dB */
+ 0x000005C2, /* SMEM coding of -45 dB */
+ 0x00000676, /* SMEM coding of -44 dB */
+ 0x0000073F, /* SMEM coding of -43 dB */
+ 0x00000822, /* SMEM coding of -42 dB */
+ 0x00000920, /* SMEM coding of -41 dB */
+ 0x00000A3D, /* SMEM coding of -40 dB */
+ 0x00000B7D, /* SMEM coding of -39 dB */
+ 0x00000CE4, /* SMEM coding of -38 dB */
+ 0x00000E76, /* SMEM coding of -37 dB */
+ 0x0000103A, /* SMEM coding of -36 dB */
+ 0x00001235, /* SMEM coding of -35 dB */
+ 0x0000146E, /* SMEM coding of -34 dB */
+ 0x000016EC, /* SMEM coding of -33 dB */
+ 0x000019B8, /* SMEM coding of -32 dB */
+ 0x00001CDC, /* SMEM coding of -31 dB */
+ 0x00002061, /* SMEM coding of -30 dB */
+ 0x00002455, /* SMEM coding of -29 dB */
+ 0x000028C4, /* SMEM coding of -28 dB */
+ 0x00002DBD, /* SMEM coding of -27 dB */
+ 0x00003352, /* SMEM coding of -26 dB */
+ 0x00003995, /* SMEM coding of -25 dB */
+ 0x0000409C, /* SMEM coding of -24 dB */
+ 0x0000487E, /* SMEM coding of -23 dB */
+ 0x00005156, /* SMEM coding of -22 dB */
+ 0x00005B43, /* SMEM coding of -21 dB */
+ 0x00006666, /* SMEM coding of -20 dB */
+ 0x000072E5, /* SMEM coding of -19 dB */
+ 0x000080E9, /* SMEM coding of -18 dB */
+ 0x000090A4, /* SMEM coding of -17 dB */
+ 0x0000A24B, /* SMEM coding of -16 dB */
+ 0x0000B618, /* SMEM coding of -15 dB */
+ 0x0000CC50, /* SMEM coding of -14 dB */
+ 0x0000E53E, /* SMEM coding of -13 dB */
+ 0x00010137, /* SMEM coding of -12 dB */
+ 0x0001209A, /* SMEM coding of -11 dB */
+ 0x000143D1, /* SMEM coding of -10 dB */
+ 0x00016B54, /* SMEM coding of -9 dB */
+ 0x000197A9, /* SMEM coding of -8 dB */
+ 0x0001C967, /* SMEM coding of -7 dB */
+ 0x00020137, /* SMEM coding of -6 dB */
+ 0x00023FD6, /* SMEM coding of -5 dB */
+ 0x00028619, /* SMEM coding of -4 dB */
+ 0x0002D4EF, /* SMEM coding of -3 dB */
+ 0x00032D64, /* SMEM coding of -2 dB */
+ 0x000390A4, /* SMEM coding of -1 dB */
+ 0x00040000, /* SMEM coding of 0 dB */
+ 0x00047CF2, /* SMEM coding of 1 dB */
+ 0x00050923, /* SMEM coding of 2 dB */
+ 0x0005A670, /* SMEM coding of 3 dB */
+ 0x000656EE, /* SMEM coding of 4 dB */
+ 0x00071CF5, /* SMEM coding of 5 dB */
+ 0x0007FB26, /* SMEM coding of 6 dB */
+ 0x0008F473, /* SMEM coding of 7 dB */
+ 0x000A0C2B, /* SMEM coding of 8 dB */
+ 0x000B4606, /* SMEM coding of 9 dB */
+ 0x000CA62C, /* SMEM coding of 10 dB */
+ 0x000E314A, /* SMEM coding of 11 dB */
+ 0x000FEC9E, /* SMEM coding of 12 dB */
+ 0x0011DE0A, /* SMEM coding of 13 dB */
+ 0x00140C28, /* SMEM coding of 14 dB */
+ 0x00167E60, /* SMEM coding of 15 dB */
+ 0x00193D00, /* SMEM coding of 16 dB */
+ 0x001C515D, /* SMEM coding of 17 dB */
+ 0x001FC5EB, /* SMEM coding of 18 dB */
+ 0x0023A668, /* SMEM coding of 19 dB */
+ 0x00280000, /* SMEM coding of 20 dB */
+ 0x002CE178, /* SMEM coding of 21 dB */
+ 0x00325B65, /* SMEM coding of 22 dB */
+ 0x00388062, /* SMEM coding of 23 dB */
+ 0x003F654E, /* SMEM coding of 24 dB */
+ 0x00472194, /* SMEM coding of 25 dB */
+ 0x004FCF7C, /* SMEM coding of 26 dB */
+ 0x00598C81, /* SMEM coding of 27 dB */
+ 0x006479B7, /* SMEM coding of 28 dB */
+ 0x0070BC3D, /* SMEM coding of 29 dB */
+ 0x007E7DB9, /* SMEM coding of 30 dB */
+};
+
+const u32 abe_1_alpha_iir[64] = {
+ 0x040002, 0x040002, 0x040002, 0x040002, /* 0 */
+ 0x50E955, 0x48CA65, 0x40E321, 0x72BE78, /* 1 [ms] */
+ 0x64BA68, 0x57DF14, 0x4C3D60, 0x41D690, /* 2 */
+ 0x38A084, 0x308974, 0x297B00, 0x235C7C, /* 4 */
+ 0x1E14B0, 0x198AF0, 0x15A800, 0x125660, /* 8 */
+ 0x0F82A0, 0x0D1B5C, 0x0B113C, 0x0956CC, /* 16 */
+ 0x07E054, 0x06A3B8, 0x059844, 0x04B680, /* 32 */
+ 0x03F80C, 0x035774, 0x02D018, 0x025E0C, /* 64 */
+ 0x7F8057, 0x6B482F, 0x5A4297, 0x4BEECB, /* 128 */
+ 0x3FE00B, 0x35BAA7, 0x2D3143, 0x2602AF, /* 256 */
+ 0x1FF803, 0x1AE2FB, 0x169C9F, 0x13042B, /* 512 */
+ 0x0FFE03, 0x0D72E7, 0x0B4F4F, 0x0982CB, /* 1.024 [s] */
+ 0x07FF83, 0x06B9CF, 0x05A7E7, 0x04C193, /* 2.048 */
+ 0x03FFE3, 0x035CFF, 0x02D403, 0x0260D7, /* 4.096 */
+ 0x01FFFB, 0x01AE87, 0x016A07, 0x01306F, /* 8.192 */
+ 0x00FFFF, 0x00D743, 0x00B503, 0x009837,
+};
+
+const u32 abe_alpha_iir[64] = {
+ 0x000000, 0x000000, 0x000000, 0x000000, /* 0 */
+ 0x5E2D58, 0x6E6B3C, 0x7E39C0, 0x46A0C5, /* 1 [ms] */
+ 0x4DA2CD, 0x541079, 0x59E151, 0x5F14B9, /* 2 */
+ 0x63AFC1, 0x67BB45, 0x6B4281, 0x6E51C1, /* 4 */
+ 0x70F5A9, 0x733A89, 0x752C01, 0x76D4D1, /* 8 */
+ 0x783EB1, 0x797251, 0x7A7761, 0x7B549D, /* 16 */
+ 0x7C0FD5, 0x7CAE25, 0x7D33DD, 0x7DA4C1, /* 32 */
+ 0x7E03FD, 0x7E5449, 0x7E97F5, 0x7ED0F9, /* 64 */
+ 0x7F0101, 0x7F2971, 0x7F4B7D, 0x7F6825, /* 128 */
+ 0x7F8041, 0x7F948D, 0x7FA59D, 0x7FB3FD, /* 256 */
+ 0x7FC011, 0x7FCA3D, 0x7FD2C9, 0x7FD9F9, /* 512 */
+ 0x7FE005, 0x7FE51D, 0x7FE961, 0x7FECFD, /* 1.024 [s] */
+ 0x7FF001, 0x7FF28D, 0x7FF4B1, 0x7FF67D, /* 2.048 */
+ 0x7FF801, 0x7FF949, 0x7FFA59, 0x7FFB41, /* 4.096 */
+ 0x7FFC01, 0x7FFCA5, 0x7FFD2D, 0x7FFDA1, /* 8.192 */
+ 0x7FFE01, 0x7FFE51, 0x7FFE95, 0x7FFED1,
+};
+
+/**
+ * abe_int_2_float
+ * returns a mantissa on 16 bits and the exponent
+ * 0x4000.0000 leads to M=0x4000 X=15
+ * 0x0004.0000 leads to M=0x4000 X=4
+ * 0x0000.0001 leads to M=0x4000 X=-14
+ *
+ */
+void abe_int_2_float16(u32 data, u32 *mantissa, u32 *exp)
+{
+ u32 i;
+ *exp = 0;
+ *mantissa = 0;
+ for (i = 0; i < 32; i++) {
+ if ((1 << i) > data)
+ break;
+ }
+ *exp = i - 15;
+ *mantissa = (*exp > 0) ? data >> (*exp) : data << (*exp);
+}
+
+/**
+ * abe_use_compensated_gain
+ * @on_off:
+ *
+ * Selects the automatic Mixer's gain management
+ * on_off = 1 allows the "abe_write_gain" to adjust the overall
+ * gains of the mixer to be tuned not to create saturation
+ */
+int omap_abe_use_compensated_gain(struct omap_abe *abe, int on_off)
+{
+ abe->compensated_mixer_gain = on_off;
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_use_compensated_gain);
+
+/**
+ * omap_abe_gain_offset
+ * returns the offset to firmware data structures
+ *
+ */
+void omap_abe_gain_offset(struct omap_abe *abe, u32 id, u32 *mixer_offset)
+{
+ switch (id) {
+ default:
+ case GAINS_DMIC1:
+ *mixer_offset = dmic1_gains_offset;
+ break;
+ case GAINS_DMIC2:
+ *mixer_offset = dmic2_gains_offset;
+ break;
+ case GAINS_DMIC3:
+ *mixer_offset = dmic3_gains_offset;
+ break;
+ case GAINS_AMIC:
+ *mixer_offset = amic_gains_offset;
+ break;
+ case GAINS_DL1:
+ *mixer_offset = dl1_gains_offset;
+ break;
+ case GAINS_DL2:
+ *mixer_offset = dl2_gains_offset;
+ break;
+ case GAINS_SPLIT:
+ *mixer_offset = splitters_gains_offset;
+ break;
+ case MIXDL1:
+ *mixer_offset = mixer_dl1_offset;
+ break;
+ case MIXDL2:
+ *mixer_offset = mixer_dl2_offset;
+ break;
+ case MIXECHO:
+ *mixer_offset = mixer_echo_offset;
+ break;
+ case MIXSDT:
+ *mixer_offset = mixer_sdt_offset;
+ break;
+ case MIXVXREC:
+ *mixer_offset = mixer_vxrec_offset;
+ break;
+ case MIXAUDUL:
+ *mixer_offset = mixer_audul_offset;
+ break;
+ case GAINS_BTUL:
+ *mixer_offset = btul_gains_offset;
+ break;
+ }
+}
+
+/**
+ * oamp_abe_write_equalizer
+ * @abe: Pointer on abe handle
+ * @id: name of the equalizer
+ * @param : equalizer coefficients
+ *
+ * Load the coefficients in CMEM.
+ */
+int omap_abe_write_equalizer(struct omap_abe *abe,
+ u32 id, struct omap_abe_equ *param)
+{
+ u32 eq_offset, length, *src, eq_mem, eq_mem_len;
+ _log(ABE_ID_WRITE_EQUALIZER, id, 0, 0);
+ switch (id) {
+ default:
+ case EQ1:
+ eq_offset = OMAP_ABE_C_DL1_COEFS_ADDR;
+ eq_mem = OMAP_ABE_S_DL1_M_EQ_DATA_ADDR;
+ eq_mem_len = OMAP_ABE_S_DL1_M_EQ_DATA_SIZE;
+ break;
+ case EQ2L:
+ eq_offset = OMAP_ABE_C_DL2_L_COEFS_ADDR;
+ eq_mem = OMAP_ABE_S_DL2_M_LR_EQ_DATA_ADDR;
+ eq_mem_len = OMAP_ABE_S_DL2_M_LR_EQ_DATA_SIZE;
+ break;
+ case EQ2R:
+ eq_offset = OMAP_ABE_C_DL2_R_COEFS_ADDR;
+ eq_mem = OMAP_ABE_S_DL2_M_LR_EQ_DATA_ADDR;
+ eq_mem_len = OMAP_ABE_S_DL2_M_LR_EQ_DATA_SIZE;
+ break;
+ case EQSDT:
+ eq_offset = OMAP_ABE_C_SDT_COEFS_ADDR;
+ eq_mem = OMAP_ABE_S_SDT_F_DATA_ADDR;
+ eq_mem_len = OMAP_ABE_S_SDT_F_DATA_SIZE;
+ break;
+ case EQAMIC:
+ eq_offset = OMAP_ABE_C_96_48_AMIC_COEFS_ADDR;
+ eq_mem = OMAP_ABE_S_AMIC_96_48_DATA_ADDR;
+ eq_mem_len = OMAP_ABE_S_AMIC_96_48_DATA_SIZE;
+ break;
+ case EQDMIC:
+ eq_offset = OMAP_ABE_C_96_48_DMIC_COEFS_ADDR;
+ eq_mem = OMAP_ABE_S_DMIC0_96_48_DATA_ADDR;
+ eq_mem_len = OMAP_ABE_S_DMIC0_96_48_DATA_SIZE;
+ /* three DMIC are clear at the same time DMIC0 DMIC1 DMIC2 */
+ eq_mem_len *= 3;
+ break;
+ case APS1:
+ eq_offset = OMAP_ABE_C_APS_DL1_COEFFS1_ADDR;
+ eq_mem = OMAP_ABE_S_APS_IIRMEM1_ADDR;
+ eq_mem_len = OMAP_ABE_S_APS_IIRMEM1_SIZE;
+ break;
+ case APS2L:
+ eq_offset = OMAP_ABE_C_APS_DL2_L_COEFFS1_ADDR;
+ eq_mem = OMAP_ABE_S_APS_M_IIRMEM2_ADDR;
+ eq_mem_len = OMAP_ABE_S_APS_M_IIRMEM2_SIZE;
+ break;
+ case APS2R:
+ eq_offset = OMAP_ABE_C_APS_DL2_R_COEFFS1_ADDR;
+ eq_mem = OMAP_ABE_S_APS_M_IIRMEM2_ADDR;
+ eq_mem_len = OMAP_ABE_S_APS_M_IIRMEM2_SIZE;
+ break;
+ }
+ /* reset SMEM buffers before the coefficients are loaded */
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM, eq_mem, eq_mem_len);
+
+ length = param->equ_length;
+ src = (u32 *) ((param->coef).type1);
+ /* translate in bytes */
+ length <<= 2;
+ omap_abe_mem_write(abe, OMAP_ABE_CMEM, eq_offset, src, length);
+
+ /* reset SMEM buffers after the coefficients are loaded */
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM, eq_mem, eq_mem_len);
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_write_equalizer);
+
+/**
+ * omap_abe_disable_gain
+ * @abe: Pointer on abe handle
+ * Parameters:
+ * mixer id
+ * sub-port id
+ *
+ */
+int omap_abe_disable_gain(struct omap_abe *abe, u32 id, u32 p)
+{
+ u32 mixer_offset, f_g, ramp;
+ omap_abe_gain_offset(abe, id, &mixer_offset);
+ /* save the input parameters for mute/unmute */
+ ramp = abe->desired_ramp_delay_ms[mixer_offset + p];
+ f_g = GAIN_MUTE;
+ if (!(abe->muted_gains_indicator[mixer_offset + p] &
+ OMAP_ABE_GAIN_DISABLED)) {
+ /* Check if we are in mute */
+ if (!(abe->muted_gains_indicator[mixer_offset + p] &
+ OMAP_ABE_GAIN_MUTED)) {
+ abe->muted_gains_decibel[mixer_offset + p] =
+ abe->desired_gains_decibel[mixer_offset + p];
+ /* mute the gain */
+ omap_abe_write_gain(abe, id, f_g, ramp, p);
+ }
+ abe->muted_gains_indicator[mixer_offset + p] |=
+ OMAP_ABE_GAIN_DISABLED;
+ }
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_disable_gain);
+
+/**
+ * omap_abe_enable_gain
+ * Parameters:
+ * mixer id
+ * sub-port id
+ *
+ */
+int omap_abe_enable_gain(struct omap_abe *abe, u32 id, u32 p)
+{
+ u32 mixer_offset, f_g, ramp;
+ omap_abe_gain_offset(abe, id, &mixer_offset);
+ if ((abe->muted_gains_indicator[mixer_offset + p] &
+ OMAP_ABE_GAIN_DISABLED)) {
+ /* restore the input parameters for mute/unmute */
+ f_g = abe->muted_gains_decibel[mixer_offset + p];
+ ramp = abe->desired_ramp_delay_ms[mixer_offset + p];
+ abe->muted_gains_indicator[mixer_offset + p] &=
+ ~OMAP_ABE_GAIN_DISABLED;
+ /* unmute the gain */
+ omap_abe_write_gain(abe, id, f_g, ramp, p);
+ }
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_enable_gain);
+/**
+ * omap_abe_mute_gain
+ * Parameters:
+ * mixer id
+ * sub-port id
+ *
+ */
+int omap_abe_mute_gain(struct omap_abe *abe, u32 id, u32 p)
+{
+ u32 mixer_offset, f_g, ramp;
+ omap_abe_gain_offset(abe, id, &mixer_offset);
+ /* save the input parameters for mute/unmute */
+ ramp = abe->desired_ramp_delay_ms[mixer_offset + p];
+ f_g = GAIN_MUTE;
+ if (!abe->muted_gains_indicator[mixer_offset + p]) {
+ abe->muted_gains_decibel[mixer_offset + p] =
+ abe->desired_gains_decibel[mixer_offset + p];
+ /* mute the gain */
+ omap_abe_write_gain(abe, id, f_g, ramp, p);
+ }
+ abe->muted_gains_indicator[mixer_offset + p] |= OMAP_ABE_GAIN_MUTED;
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_mute_gain);
+/**
+ * omap_abe_unmute_gain
+ * Parameters:
+ * mixer id
+ * sub-port id
+ *
+ */
+int omap_abe_unmute_gain(struct omap_abe *abe, u32 id, u32 p)
+{
+ u32 mixer_offset, f_g, ramp;
+ omap_abe_gain_offset(abe, id, &mixer_offset);
+ if ((abe->muted_gains_indicator[mixer_offset + p] &
+ OMAP_ABE_GAIN_MUTED)) {
+ /* restore the input parameters for mute/unmute */
+ f_g = abe->muted_gains_decibel[mixer_offset + p];
+ ramp = abe->desired_ramp_delay_ms[mixer_offset + p];
+ abe->muted_gains_indicator[mixer_offset + p] &=
+ ~OMAP_ABE_GAIN_MUTED;
+ /* unmute the gain */
+ omap_abe_write_gain(abe, id, f_g, ramp, p);
+ }
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_unmute_gain);
+
+/**
+ * omap_abe_write_gain
+ * @id: gain name or mixer name
+ * @f_g: list of input gains of the mixer
+ * @ramp: gain ramp speed factor
+ * @p: list of ports corresponding to the above gains
+ *
+ * Loads the gain coefficients to FW memory. This API can be called when
+ * the corresponding MIXER is not activated. After reloading the firmware
+ * the default coefficients corresponds to "all input and output mixer's gain
+ * in mute state". A mixer is disabled with a network reconfiguration
+ * corresponding to an OPP value.
+ */
+int omap_abe_write_gain(struct omap_abe *abe,
+ u32 id, s32 f_g, u32 ramp, u32 p)
+{
+ u32 lin_g, sum_g, mixer_target, mixer_offset, i, mean_gain, mean_exp;
+ u32 new_gain_linear[4];
+ s32 gain_index;
+ u32 alpha, beta;
+ u32 ramp_index;
+
+ _log(ABE_ID_WRITE_GAIN, id, f_g, p);
+ gain_index = ((f_g - min_mdb) / 100);
+ gain_index = maximum(gain_index, 0);
+ gain_index = minimum(gain_index, sizeof_db2lin_table);
+ lin_g = abe_db2lin_table[gain_index];
+ omap_abe_gain_offset(abe, id, &mixer_offset);
+ /* save the input parameters for mute/unmute */
+ abe->desired_gains_linear[mixer_offset + p] = lin_g;
+ abe->desired_gains_decibel[mixer_offset + p] = f_g;
+ abe->desired_ramp_delay_ms[mixer_offset + p] = ramp;
+ /* SMEM address in bytes */
+ mixer_target = OMAP_ABE_S_GTARGET1_ADDR;
+ mixer_target += (mixer_offset<<2);
+ mixer_target += (p<<2);
+
+ if (abe->compensated_mixer_gain) {
+ switch (id) {
+ case MIXDL1:
+ case MIXDL2:
+ case MIXVXREC:
+ case MIXAUDUL:
+ /* compute the sum of the gain of the mixer */
+ for (sum_g = i = 0; i < 4; i++)
+ sum_g += abe->desired_gains_linear[mixer_offset +
+ i];
+ /* lets avoid a division by 0 */
+ if (sum_g == 0)
+ break;
+ /* if the sum is OK with less than 1, then
+ do not weight the gains */
+ if (sum_g < 0x00040000) { /* REMOVE HARD CONST */
+ /* recompute all gains from original
+ desired values */
+ sum_g = 0x00040000;
+ }
+ /* translate it in Q16 format for the later division */
+ abe_int_2_float16(sum_g, &mean_gain, &mean_exp);
+ mean_exp = 10 - mean_exp;
+ for (i = 0; i < 4; i++) {
+ /* new gain = desired gain divided by sum of gains */
+ new_gain_linear[i] =
+ (abe->desired_gains_linear
+ [mixer_offset + i]
+ << 8) / mean_gain;
+ new_gain_linear[i] = (mean_exp > 0) ?
+ new_gain_linear[i] << mean_exp :
+ new_gain_linear[i] >> mean_exp;
+ }
+ /* load the whole adpated S_G_Target SMEM MIXER table */
+ omap_abe_mem_write(abe, OMAP_ABE_SMEM,
+ mixer_target - (p << 2),
+ new_gain_linear, (4 * sizeof(lin_g)));
+ break;
+ default:
+ /* load the S_G_Target SMEM table */
+ omap_abe_mem_write(abe, OMAP_ABE_SMEM,
+ mixer_target,
+ (u32 *) &lin_g, sizeof(lin_g));
+ break;
+ }
+ } else {
+ if (!abe->muted_gains_indicator[mixer_offset + p])
+ /* load the S_G_Target SMEM table */
+ omap_abe_mem_write(abe, OMAP_ABE_SMEM,
+ mixer_target, (u32 *) &lin_g,
+ sizeof(lin_g));
+ else
+ /* update muted gain with new value */
+ abe->muted_gains_decibel[mixer_offset + p] = f_g;
+ }
+ ramp = maximum(minimum(RAMP_MAXLENGTH, ramp), RAMP_MINLENGTH);
+ /* ramp data should be interpolated in the table instead */
+ ramp_index = 8;
+ if ((RAMP_5MS <= ramp) && (ramp < RAMP_50MS))
+ ramp_index = 24;
+ if ((RAMP_50MS <= ramp) && (ramp < RAMP_500MS))
+ ramp_index = 36;
+ if (ramp > RAMP_500MS)
+ ramp_index = 48;
+ beta = abe_alpha_iir[ramp_index];
+ alpha = abe_1_alpha_iir[ramp_index];
+ /* CMEM bytes address */
+ mixer_target = OMAP_ABE_C_1_ALPHA_ADDR;
+ /* a pair of gains is updated once in the firmware */
+ mixer_target += (p + mixer_offset) << 1;
+ /* load the ramp delay data */
+ omap_abe_mem_write(abe, OMAP_ABE_CMEM, mixer_target,
+ (u32 *) &alpha, sizeof(alpha));
+ /* CMEM bytes address */
+ mixer_target = OMAP_ABE_C_ALPHA_ADDR;
+ /* a pair of gains is updated once in the firmware */
+ mixer_target += (p + mixer_offset) << 1;
+ omap_abe_mem_write(abe, OMAP_ABE_CMEM, mixer_target,
+ (u32 *) &beta, sizeof(beta));
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_write_gain);
+/**
+ * omap_abe_write_mixer
+ * @id: name of the mixer
+ * @param: input gains and delay ramp of the mixer
+ * @p: port corresponding to the above gains
+ *
+ * Load the gain coefficients in FW memory. This API can be called when
+ * the corresponding MIXER is not activated. After reloading the firmware
+ * the default coefficients corresponds to "all input and output mixer's
+ * gain in mute state". A mixer is disabled with a network reconfiguration
+ * corresponding to an OPP value.
+ */
+int omap_abe_write_mixer(struct omap_abe *abe,
+ u32 id, s32 f_g, u32 f_ramp, u32 p)
+{
+ _log(ABE_ID_WRITE_MIXER, id, f_ramp, p);
+ omap_abe_write_gain(abe, id, f_g, f_ramp, p);
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_write_mixer);
+
+/**
+ * omap_abe_read_gain
+ * @id: name of the mixer
+ * @param: list of input gains of the mixer
+ * @p: list of port corresponding to the above gains
+ *
+ */
+int omap_abe_read_gain(struct omap_abe *abe,
+ u32 id, u32 *f_g, u32 p)
+{
+ u32 mixer_target, mixer_offset, i;
+ _log(ABE_ID_READ_GAIN, id, (u32) f_g, p);
+ omap_abe_gain_offset(abe, id, &mixer_offset);
+ /* SMEM bytes address */
+ mixer_target = OMAP_ABE_S_GTARGET1_ADDR;
+ mixer_target += (mixer_offset<<2);
+ mixer_target += (p<<2);
+ if (!abe->muted_gains_indicator[mixer_offset + p]) {
+ /* load the S_G_Target SMEM table */
+ omap_abe_mem_read(abe, OMAP_ABE_SMEM, mixer_target,
+ (u32 *) f_g, sizeof(*f_g));
+ for (i = 0; i < sizeof_db2lin_table; i++) {
+ if (abe_db2lin_table[i] == *f_g)
+ goto found;
+ }
+ *f_g = 0;
+ return -1;
+ found:
+ *f_g = (i * 100) + min_mdb;
+ } else {
+ /* update muted gain with new value */
+ *f_g = abe->muted_gains_decibel[mixer_offset + p];
+ }
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_read_gain);
+
+/**
+ * abe_read_mixer
+ * @id: name of the mixer
+ * @param: gains of the mixer
+ * @p: port corresponding to the above gains
+ *
+ * Load the gain coefficients in FW memory. This API can be called when
+ * the corresponding MIXER is not activated. After reloading the firmware
+ * the default coefficients corresponds to "all input and output mixer's
+ * gain in mute state". A mixer is disabled with a network reconfiguration
+ * corresponding to an OPP value.
+ */
+int omap_abe_read_mixer(struct omap_abe *abe,
+ u32 id, u32 *f_g, u32 p)
+{
+ _log(ABE_ID_READ_MIXER, id, 0, p);
+ omap_abe_read_gain(abe, id, f_g, p);
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_read_mixer);
+
+/**
+ * abe_reset_gain_mixer
+ * @id: name of the mixer
+ * @p: list of port corresponding to the above gains
+ *
+ * restart the working gain value of the mixers when a port is enabled
+ */
+void omap_abe_reset_gain_mixer(struct omap_abe *abe, u32 id, u32 p)
+{
+ u32 lin_g, mixer_target, mixer_offset;
+ switch (id) {
+ default:
+ case GAINS_DMIC1:
+ mixer_offset = dmic1_gains_offset;
+ break;
+ case GAINS_DMIC2:
+ mixer_offset = dmic2_gains_offset;
+ break;
+ case GAINS_DMIC3:
+ mixer_offset = dmic3_gains_offset;
+ break;
+ case GAINS_AMIC:
+ mixer_offset = amic_gains_offset;
+ break;
+ case GAINS_DL1:
+ mixer_offset = dl1_gains_offset;
+ break;
+ case GAINS_DL2:
+ mixer_offset = dl2_gains_offset;
+ break;
+ case GAINS_SPLIT:
+ mixer_offset = splitters_gains_offset;
+ break;
+ case MIXDL1:
+ mixer_offset = mixer_dl1_offset;
+ break;
+ case MIXDL2:
+ mixer_offset = mixer_dl2_offset;
+ break;
+ case MIXECHO:
+ mixer_offset = mixer_echo_offset;
+ break;
+ case MIXSDT:
+ mixer_offset = mixer_sdt_offset;
+ break;
+ case MIXVXREC:
+ mixer_offset = mixer_vxrec_offset;
+ break;
+ case MIXAUDUL:
+ mixer_offset = mixer_audul_offset;
+ break;
+ case GAINS_BTUL:
+ mixer_offset = btul_gains_offset;
+ break;
+ }
+ /* SMEM bytes address for the CURRENT gain values */
+ mixer_target = OMAP_ABE_S_GCURRENT_ADDR;
+ mixer_target += (mixer_offset<<2);
+ mixer_target += (p<<2);
+ lin_g = 0;
+ /* load the S_G_Target SMEM table */
+ omap_abe_mem_write(abe, OMAP_ABE_SMEM, mixer_target,
+ (u32 *) &lin_g, sizeof(lin_g));
+}
diff --git a/sound/soc/omap/abe/abe_gain.h b/sound/soc/omap/abe/abe_gain.h
new file mode 100644
index 0000000..f332837
--- /dev/null
+++ b/sound/soc/omap/abe/abe_gain.h
@@ -0,0 +1,111 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_GAIN_H_
+#define _ABE_GAIN_H_
+
+#include "abe_typ.h"
+#include "abe_dm_addr.h"
+#include "abe_sm_addr.h"
+#include "abe_cm_addr.h"
+
+#define OMAP_ABE_GAIN_MUTED (0x0001<<0)
+#define OMAP_ABE_GAIN_DISABLED (0x0001<<1)
+
+#define OMAP_ABE_GAIN_DMIC1_LEFT 0
+#define OMAP_ABE_GAIN_DMIC1_RIGTH 1
+#define OMAP_ABE_GAIN_DMIC2_LEFT 2
+#define OMAP_ABE_GAIN_DMIC2_RIGTH 3
+#define OMAP_ABE_GAIN_DMIC3_LEFT 4
+#define OMAP_ABE_GAIN_DMIC3_RIGTH 5
+#define OMAP_ABE_GAIN_AMIC_LEFT 6
+#define OMAP_ABE_GAIN_AMIC_RIGTH 7
+#define OMAP_ABE_GAIN_DL1_LEFT 8
+#define OMAP_ABE_GAIN_DL1_RIGTH 9
+#define OMAP_ABE_GAIN_DL2_LEFT 10
+#define OMAP_ABE_GAIN_DL2_RIGTH 11
+#define OMAP_ABE_GAIN_SPLIT_LEFT 12
+#define OMAP_ABE_GAIN_SPLIT_RIGTH 13
+#define OMAP_ABE_MIXDL1_MM_DL 14
+#define OMAP_ABE_MIXDL1_MM_UL2 15
+#define OMAP_ABE_MIXDL1_VX_DL 16
+#define OMAP_ABE_MIXDL1_TONES 17
+#define OMAP_ABE_MIXDL2_MM_DL 18
+#define OMAP_ABE_MIXDL2_MM_UL2 19
+#define OMAP_ABE_MIXDL2_VX_DL 20
+#define OMAP_ABE_MIXDL2_TONES 21
+#define OMAP_ABE_MIXECHO_DL1 22
+#define OMAP_ABE_MIXECHO_DL2 23
+#define OMAP_ABE_MIXSDT_UL 24
+#define OMAP_ABE_MIXECHO_DL 25
+#define OMAP_ABE_MIXVXREC_MM_DL 26
+#define OMAP_ABE_MIXVXREC_TONES 27
+#define OMAP_ABE_MIXVXREC_VX_UL 28
+#define OMAP_ABE_MIXVXREC_VX_DL 29
+#define OMAP_ABE_MIXAUDUL_MM_DL 30
+#define OMAP_ABE_MIXAUDUL_TONES 31
+#define OMAP_ABE_MIXAUDUL_UPLINK 32
+#define OMAP_ABE_MIXAUDUL_VX_DL 33
+#define OMAP_ABE_GAIN_BTUL_LEFT 34
+#define OMAP_ABE_GAIN_BTUL_RIGTH 35
+
+void omap_abe_reset_gain_mixer(struct omap_abe *abe, u32 id, u32 p);
+
+void abe_int_2_float16(u32 data, u32 *mantissa, u32 *exp);
+
+#endif /* _ABE_GAIN_H_ */
diff --git a/sound/soc/omap/abe/abe_ini.c b/sound/soc/omap/abe/abe_ini.c
new file mode 100644
index 0000000..5a2bf08
--- /dev/null
+++ b/sound/soc/omap/abe/abe_ini.c
@@ -0,0 +1,547 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include "abe_dbg.h"
+#include "abe.h"
+#include "abe_aess.h"
+#include "abe_gain.h"
+#include "abe_mem.h"
+#include "abe_port.h"
+#include "abe_seq.h"
+
+#include "abe_taskid.h"
+
+
+#define ABE_TASK_ID(ID) (OMAP_ABE_D_TASKSLIST_ADDR + sizeof(ABE_STask)*(ID))
+void omap_abe_build_scheduler_table(struct omap_abe *abe);
+void omap_abe_reset_all_ports(struct omap_abe *abe);
+
+const u32 abe_firmware_array[ABE_FIRMWARE_MAX_SIZE] = {
+#include "abe_firmware.c"
+};
+
+
+/*
+ * initialize the default values for call-backs to subroutines
+ * - FIFO IRQ call-backs for sequenced tasks
+ * - FIFO IRQ call-backs for audio player/recorders (ping-pong protocols)
+ * - Remote debugger interface
+ * - Error monitoring
+ * - Activity Tracing
+ */
+
+/**
+ * abe_init_mem - Allocate Kernel space memory map for ABE
+ *
+ * Memory map of ABE memory space for PMEM/DMEM/SMEM/DMEM
+ */
+void abe_init_mem(void __iomem **_io_base)
+{
+ int i;
+
+ abe = kzalloc(sizeof(struct omap_abe), GFP_KERNEL);
+ if (abe == NULL)
+ printk(KERN_ERR "ABE Allocation ERROR ");
+
+ for (i = 0; i < 5; i++)
+ abe->io_base[i] = _io_base[i];
+
+ mutex_init(&abe->mutex);
+
+}
+EXPORT_SYMBOL(abe_init_mem);
+
+/**
+ * abe_load_fw_param - Load ABE Firmware memories
+ * @PMEM: Pointer of Program memory data
+ * @PMEM_SIZE: Size of PMEM data
+ * @CMEM: Pointer of Coeffients memory data
+ * @CMEM_SIZE: Size of CMEM data
+ * @SMEM: Pointer of Sample memory data
+ * @SMEM_SIZE: Size of SMEM data
+ * @DMEM: Pointer of Data memory data
+ * @DMEM_SIZE: Size of DMEM data
+ *
+ */
+int abe_load_fw_param(u32 *ABE_FW)
+{
+ u32 pmem_size, dmem_size, smem_size, cmem_size;
+ u32 *pmem_ptr, *dmem_ptr, *smem_ptr, *cmem_ptr, *fw_ptr;
+ _log(ABE_ID_LOAD_FW_param, 0, 0, 0);
+#define ABE_FW_OFFSET 5
+ fw_ptr = ABE_FW;
+ abe->firmware_version_number = *fw_ptr++;
+ pmem_size = *fw_ptr++;
+ cmem_size = *fw_ptr++;
+ dmem_size = *fw_ptr++;
+ smem_size = *fw_ptr++;
+ pmem_ptr = fw_ptr;
+ cmem_ptr = pmem_ptr + (pmem_size >> 2);
+ dmem_ptr = cmem_ptr + (cmem_size >> 2);
+ smem_ptr = dmem_ptr + (dmem_size >> 2);
+ /* do not load PMEM */
+ if (abe->warm_boot) {
+ /* Stop the event Generator */
+ omap_abe_stop_event_generator(abe);
+
+ /* Now we are sure the firmware is stalled */
+ omap_abe_mem_write(abe, OMAP_ABE_CMEM, 0, cmem_ptr,
+ cmem_size);
+ omap_abe_mem_write(abe, OMAP_ABE_SMEM, 0, smem_ptr,
+ smem_size);
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM, 0, dmem_ptr,
+ dmem_size);
+ /* Restore the event Generator status */
+ omap_abe_start_event_generator(abe);
+ } else {
+ omap_abe_mem_write(abe, OMAP_ABE_PMEM, 0, pmem_ptr,
+ pmem_size);
+ omap_abe_mem_write(abe, OMAP_ABE_CMEM, 0, cmem_ptr,
+ cmem_size);
+ omap_abe_mem_write(abe, OMAP_ABE_SMEM, 0, smem_ptr,
+ smem_size);
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM, 0, dmem_ptr,
+ dmem_size);
+ }
+ abe->warm_boot = 1;
+ return 0;
+}
+EXPORT_SYMBOL(abe_load_fw_param);
+
+/**
+ * omap_abe_load_fw - Load ABE Firmware and initialize memories
+ * @abe: Pointer on abe handle
+ *
+ */
+int omap_abe_load_fw(struct omap_abe *abe)
+{
+ _log(ABE_ID_LOAD_FW, 0, 0, 0);
+ abe_load_fw_param((u32 *) abe_firmware_array);
+ omap_abe_reset_all_ports(abe);
+ omap_abe_build_scheduler_table(abe);
+ omap_abe_reset_all_sequence(abe);
+ omap_abe_select_main_port(OMAP_ABE_PDM_DL_PORT);
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_load_fw);
+
+/**
+ * abe_reload_fw - Reload ABE Firmware after OFF mode
+ */
+int abe_reload_fw(void)
+{
+ abe->warm_boot = 0;
+ abe_load_fw_param((u32 *) abe_firmware_array);
+ omap_abe_build_scheduler_table(abe);
+ omap_abe_dbg_reset(&abe->dbg);
+ /* IRQ circular read pointer in DMEM */
+ abe->irq_dbg_read_ptr = 0;
+ /* Restore Gains not managed by the drivers */
+ omap_abe_write_gain(abe, GAINS_SPLIT, GAIN_0dB,
+ RAMP_100MS, GAIN_LEFT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_SPLIT, GAIN_0dB,
+ RAMP_100MS, GAIN_RIGHT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_DL1, GAIN_0dB,
+ RAMP_100MS, GAIN_LEFT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_DL1, GAIN_0dB,
+ RAMP_100MS, GAIN_RIGHT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_DL2, GAIN_0dB,
+ RAMP_100MS, GAIN_LEFT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_DL2, GAIN_0dB,
+ RAMP_100MS, GAIN_RIGHT_OFFSET);
+ return 0;
+}
+EXPORT_SYMBOL(abe_reload_fw);
+
+/**
+ * abe_build_scheduler_table
+ *
+ */
+void omap_abe_build_scheduler_table(struct omap_abe *abe)
+{
+ u16 i, n;
+ u8 *ptr;
+ u16 aUplinkMuxing[NBROUTE_UL];
+
+ /* LOAD OF THE TASKS' MULTIFRAME */
+ /* WARNING ON THE LOCATION OF IO_MM_DL WHICH IS PATCHED
+ IN "abe_init_io_tasks" */
+ for (ptr = (u8 *) &(abe->MultiFrame[0][0]), i = 0;
+ i < sizeof(abe->MultiFrame); i++)
+ *ptr++ = 0;
+
+ /* MultiFrame[0][0] = 0; */
+ /* MultiFrame[0][1] = 0; */
+ abe->MultiFrame[0][2] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_VX_DL)*/;
+ /* MultiFrame[0][3] = 0; */
+ /* MultiFrame[0][4] = 0; */
+ /* MultiFrame[0][5] = 0; */
+ /* MultiFrame[0][6] = 0; */
+ /* MultiFrame[0][7] = 0; */
+ /* MultiFrame[1][0] = 0; */
+ /* MultiFrame[1][1] = 0; */
+ abe->MultiFrame[1][2] = ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_DL_8);
+ abe->MultiFrame[1][3] = ABE_TASK_ID(C_ABE_FW_TASK_VX_DL_8_48);
+ /* MultiFrame[1][4] = 0; */
+ /* MultiFrame[1][5] = 0; */
+ abe->MultiFrame[1][6] = ABE_TASK_ID(C_ABE_FW_TASK_DL2Mixer);
+ abe->MultiFrame[1][7] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_VIB_DL)*/;
+ abe->MultiFrame[2][0] = ABE_TASK_ID(C_ABE_FW_TASK_DL1Mixer);
+ abe->MultiFrame[2][1] = ABE_TASK_ID(C_ABE_FW_TASK_SDTMixer);
+ /* MultiFrame[2][2] = 0; */
+ /* MultiFrame[2][3] = 0; */
+ /* MultiFrame[2][4] = 0; */
+ abe->MultiFrame[2][5] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_DMIC)*/;
+ /* MultiFrame[2][6] = 0; */
+ /* MultiFrame[2][7] = 0; */
+ abe->MultiFrame[3][0] = ABE_TASK_ID(C_ABE_FW_TASK_DL1_GAIN);
+ /* MultiFrame[3][1] = 0; */
+ /* MultiFrame[3][2] = 0; */
+ /* MultiFrame[3][3] = 0; */
+ /* MultiFrame[3][4] = 0; */
+ /* MultiFrame[3][5] = 0; */
+ abe->MultiFrame[3][6] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_GAIN);
+ abe->MultiFrame[3][7] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_EQ);
+ abe->MultiFrame[4][0] = ABE_TASK_ID(C_ABE_FW_TASK_DL1_EQ);
+ /* MultiFrame[4][1] = 0; */
+ abe->MultiFrame[4][2] = ABE_TASK_ID(C_ABE_FW_TASK_VXRECMixer);
+ abe->MultiFrame[4][3] = ABE_TASK_ID(C_ABE_FW_TASK_VXREC_SPLIT);
+ /* MultiFrame[4][4] = 0; */
+ /* MultiFrame[4][5] = 0; */
+ abe->MultiFrame[4][6] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA1);
+ abe->MultiFrame[4][7] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA2);
+ abe->MultiFrame[5][0] = 0;
+ abe->MultiFrame[5][1] = ABE_TASK_ID(C_ABE_FW_TASK_EARP_48_96_LP);
+ abe->MultiFrame[5][2] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_PDM_UL)*/;
+ /* MultiFrame[5][3] = 0; */
+ /* MultiFrame[5][4] = 0; */
+ /* MultiFrame[5][5] = 0; */
+ /* MultiFrame[5][6] = 0; */
+ abe->MultiFrame[5][7] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA_SPLIT);
+ abe->MultiFrame[6][0] = ABE_TASK_ID(C_ABE_FW_TASK_EARP_48_96_LP);
+ /* MultiFrame[6][1] = 0; */
+ /* MultiFrame[6][2] = 0; */
+ /* MultiFrame[6][3] = 0; */
+ /* MultiFrame[6][4] = 0; */
+ abe->MultiFrame[6][5] = ABE_TASK_ID(C_ABE_FW_TASK_EchoMixer);
+ /* MultiFrame[6][6] = 0; */
+ /* MultiFrame[6][7] = 0; */
+ abe->MultiFrame[7][0] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_PDM_DL)*/;
+ /* MultiFrame[7][1] = 0; */
+ abe->MultiFrame[7][2] = ABE_TASK_ID(C_ABE_FW_TASK_BT_UL_SPLIT);
+ abe->MultiFrame[7][3] = ABE_TASK_ID(C_ABE_FW_TASK_DBG_SYNC);
+ /* MultiFrame[7][4] = 0; */
+ abe->MultiFrame[7][5] = ABE_TASK_ID(C_ABE_FW_TASK_ECHO_REF_SPLIT);
+ /* MultiFrame[7][6] = 0; */
+ /* MultiFrame[7][7] = 0; */
+ /* MultiFrame[8][0] = 0; */
+ /* MultiFrame[8][1] = 0; */
+ abe->MultiFrame[8][2] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC1_96_48_LP);
+ /* MultiFrame[8][3] = 0; */
+ abe->MultiFrame[8][4] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC1_SPLIT);
+ /* MultiFrame[8][5] = 0; */
+ /* MultiFrame[8][6] = 0; */
+ /* MultiFrame[8][7] = 0; */
+ /* MultiFrame[9][0] = 0; */
+ /* MultiFrame[9][1] = 0; */
+ abe->MultiFrame[9][2] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC2_96_48_LP);
+ /* MultiFrame[9][3] = 0; */
+ abe->MultiFrame[9][4] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC2_SPLIT);
+ /* MultiFrame[9][5] = 0; */
+ abe->MultiFrame[9][6] = 0;
+ abe->MultiFrame[9][7] = ABE_TASK_ID(C_ABE_FW_TASK_IHF_48_96_LP);
+ /* MultiFrame[10][0] = 0; */
+ /* MultiFrame[10][1] = 0; */
+ abe->MultiFrame[10][2] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC3_96_48_LP);
+ /* MultiFrame[10][3] = 0; */
+ abe->MultiFrame[10][4] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC3_SPLIT);
+ /* MultiFrame[10][5] = 0; */
+ /* MultiFrame[10][6] = 0; */
+ abe->MultiFrame[10][7] = ABE_TASK_ID(C_ABE_FW_TASK_IHF_48_96_LP);
+ /* MultiFrame[11][0] = 0; */
+ /* MultiFrame[11][1] = 0; */
+ abe->MultiFrame[11][2] = ABE_TASK_ID(C_ABE_FW_TASK_AMIC_96_48_LP);
+ /* MultiFrame[11][3] = 0; */
+ abe->MultiFrame[11][4] = ABE_TASK_ID(C_ABE_FW_TASK_AMIC_SPLIT);
+ /* MultiFrame[11][5] = 0; */
+ /* MultiFrame[11][6] = 0; */
+ abe->MultiFrame[11][7] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA_PACK);
+ /* MultiFrame[12][0] = 0; */
+ /* MultiFrame[12][1] = 0; */
+ /* MultiFrame[12][2] = 0; */
+ abe->MultiFrame[12][3] = ABE_TASK_ID(C_ABE_FW_TASK_VX_UL_ROUTING);
+ abe->MultiFrame[12][4] = ABE_TASK_ID(C_ABE_FW_TASK_ULMixer);
+ abe->MultiFrame[12][5] = ABE_TASK_ID(C_ABE_FW_TASK_VX_UL_48_8);
+ /* MultiFrame[12][6] = 0; */
+ /* MultiFrame[12][7] = 0; */
+ /* MultiFrame[13][0] = 0; */
+ /* MultiFrame[13][1] = 0; */
+ abe->MultiFrame[13][2] = ABE_TASK_ID(C_ABE_FW_TASK_MM_UL2_ROUTING);
+ abe->MultiFrame[13][3] = ABE_TASK_ID(C_ABE_FW_TASK_SideTone);
+ /* MultiFrame[13][4] = 0; */
+ abe->MultiFrame[13][5] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_BT_VX_DL)*/;
+ /* MultiFrame[13][6] = 0; */
+ /* MultiFrame[13][7] = 0; */
+ /* MultiFrame[14][0] = 0; */
+ /* MultiFrame[14][1] = 0; */
+ /* MultiFrame[14][2] = 0; */
+ abe->MultiFrame[14][3] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_DMIC)*/;
+ abe->MultiFrame[14][4] = ABE_TASK_ID(C_ABE_FW_TASK_BT_DL_48_8);
+ /* MultiFrame[14][5] = 0; */
+ /* MultiFrame[14][6] = 0; */
+ /* MultiFrame[14][7] = 0; */
+ abe->MultiFrame[15][0] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_EXT_OUT)*/;
+ /* MultiFrame[15][1] = 0; */
+ /* MultiFrame[15][2] = 0; */
+ abe->MultiFrame[15][3] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_BT_VX_UL)*/;
+ /* MultiFrame[15][4] = 0; */
+ /* MultiFrame[15][5] = 0; */
+ abe->MultiFrame[15][6] = ABE_TASK_ID(C_ABE_FW_TASK_ASRC_BT_UL_8);
+ /* MultiFrame[15][7] = 0; */
+ /* MultiFrame[16][0] = 0; */
+ /* MultiFrame[16][1] = 0; */
+ abe->MultiFrame[16][2] = ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_UL_8);
+ abe->MultiFrame[16][3] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_VX_UL)*/;
+ /* MultiFrame[16][4] = 0; */
+ /* MultiFrame[16][5] = 0; */
+ /* MultiFrame[16][6] = 0; */
+ /* MultiFrame[16][7] = 0; */
+ /* MultiFrame[17][0] = 0; */
+ /* MultiFrame[17][1] = 0; */
+ abe->MultiFrame[17][2] = ABE_TASK_ID(C_ABE_FW_TASK_BT_UL_8_48);
+ abe->MultiFrame[17][3] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_UL2)*/;
+ /* MultiFrame[17][4] = 0; */
+ /* MultiFrame[17][5] = 0; */
+ /* MultiFrame[17][6] = 0; */
+ /* MultiFrame[17][7] = 0; */
+ abe->MultiFrame[18][0] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_DL)*/;
+ /* MultiFrame[18][1] = 0; */
+ /* MultiFrame[18][2] = 0; */
+ /* MultiFrame[18][3] = 0; */
+ /* MultiFrame[18][4] = 0; */
+ /* MultiFrame[18][5] = 0; */
+ abe->MultiFrame[18][6] = ABE_TASK_ID(C_ABE_FW_TASK_ASRC_BT_DL_8);
+ /* MultiFrame[18][7] = 0; */
+ abe->MultiFrame[19][0] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_PDM_DL)*/;
+ /* MultiFrame[19][1] = 0 */
+ /* MultiFrame[19][2] = 0; */
+ /* MultiFrame[19][3] = 0; */
+ /* MultiFrame[19][4] = 0; */
+ /* MultiFrame[19][5] = 0; */
+ /* MM_UL is moved to OPP 100% */
+ abe->MultiFrame[19][6] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_UL)*/;
+ /* MultiFrame[19][7] = 0; */
+ abe->MultiFrame[20][0] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_TONES_DL)*/;
+ /* MultiFrame[20][1] = 0; */
+ /* MultiFrame[20][2] = 0; */
+ /* MultiFrame[20][3] = 0; */
+ /* MultiFrame[20][4] = 0; */
+ /* MultiFrame[20][5] = 0; */
+ abe->MultiFrame[20][6] = ABE_TASK_ID(C_ABE_FW_TASK_ASRC_MM_EXT_IN);
+ /* MultiFrame[20][7] = 0; */
+ /* MultiFrame[21][0] = 0; */
+ abe->MultiFrame[21][1] = ABE_TASK_ID(C_ABE_FW_TASK_DEBUGTRACE_VX_ASRCs);
+ /* MultiFrame[21][2] = 0; */
+ abe->MultiFrame[21][3] = 0/*ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_EXT_IN)*/;
+ /* MultiFrame[21][4] = 0; */
+ /* MultiFrame[21][5] = 0; */
+ /* MultiFrame[21][6] = 0; */
+ /* MultiFrame[21][7] = 0; */
+ /* MUST STAY ON SLOT 22 */
+ abe->MultiFrame[22][0] = ABE_TASK_ID(C_ABE_FW_TASK_DEBUG_IRQFIFO);
+ abe->MultiFrame[22][1] = ABE_TASK_ID(C_ABE_FW_TASK_INIT_FW_MEMORY);
+ abe->MultiFrame[22][2] = 0;
+ /* MultiFrame[22][3] = 0; */
+ /* MM_EXT_IN_SPLIT task must be after IO_MM_EXT_IN and before
+ ASRC_MM_EXT_IN in order to manage OPP50 <-> transitions */
+ abe->MultiFrame[22][4] = ABE_TASK_ID(C_ABE_FW_TASK_MM_EXT_IN_SPLIT);
+ /* MultiFrame[22][5] = 0; */
+ /* MultiFrame[22][6] = 0; */
+ /* MultiFrame[22][7] = 0; */
+ abe->MultiFrame[23][0] = ABE_TASK_ID(C_ABE_FW_TASK_GAIN_UPDATE);
+ /* MultiFrame[23][1] = 0; */
+ /* MultiFrame[23][2] = 0; */
+ /* MultiFrame[23][3] = 0; */
+ /* MultiFrame[23][4] = 0; */
+ /* MultiFrame[23][5] = 0; */
+ /* MultiFrame[23][6] = 0; */
+ /* MultiFrame[23][7] = 0; */
+ /* MultiFrame[24][0] = 0; */
+ /* MultiFrame[24][1] = 0; */
+ /* MultiFrame[24][2] = 0; */
+ /* MultiFrame[24][3] = 0; */
+ /* MultiFrame[24][4] = 0; */
+ /* MultiFrame[24][5] = 0; */
+ /* MultiFrame[24][6] = 0; */
+ /* MultiFrame[24][7] = 0; */
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM, OMAP_ABE_D_MULTIFRAME_ADDR,
+ (u32 *) abe->MultiFrame, sizeof(abe->MultiFrame));
+ /* reset the uplink router */
+ n = (OMAP_ABE_D_AUPLINKROUTING_SIZE) >> 1;
+ for (i = 0; i < n; i++)
+ aUplinkMuxing[i] = ZERO_labelID;
+
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM, OMAP_ABE_D_AUPLINKROUTING_ADDR,
+ (u32 *) aUplinkMuxing, sizeof(aUplinkMuxing));
+}
+
+/**
+ * omap_abe_reset_port
+ * @id: ABE port ID
+ *
+ * stop the port activity and reload default parameters on the associated
+ * processing features.
+ * Clears the internal AE buffers.
+ */
+int omap_abe_reset_port(u32 id)
+{
+ _log(ABE_ID_RESET_PORT, id, 0, 0);
+ abe_port[id] = ((abe_port_t *) abe_port_init)[id];
+ return 0;
+}
+
+/**
+ * abe_reset_all_ports
+ *
+ * load default configuration for all features
+ */
+void omap_abe_reset_all_ports(struct omap_abe *abe)
+{
+ u16 i;
+ for (i = 0; i < LAST_PORT_ID; i++)
+ omap_abe_reset_port(i);
+ /* mixers' configuration */
+ omap_abe_write_mixer(abe, MIXDL1, MUTE_GAIN,
+ RAMP_100MS, MIX_DL1_INPUT_MM_DL);
+ omap_abe_write_mixer(abe, MIXDL1, MUTE_GAIN,
+ RAMP_100MS, MIX_DL1_INPUT_MM_UL2);
+ omap_abe_write_mixer(abe, MIXDL1, MUTE_GAIN,
+ RAMP_100MS, MIX_DL1_INPUT_VX_DL);
+ omap_abe_write_mixer(abe, MIXDL1, MUTE_GAIN,
+ RAMP_100MS, MIX_DL1_INPUT_TONES);
+ omap_abe_write_mixer(abe, MIXDL2, MUTE_GAIN,
+ RAMP_100MS, MIX_DL2_INPUT_TONES);
+ omap_abe_write_mixer(abe, MIXDL2, MUTE_GAIN,
+ RAMP_100MS, MIX_DL2_INPUT_VX_DL);
+ omap_abe_write_mixer(abe, MIXDL2, MUTE_GAIN,
+ RAMP_100MS, MIX_DL2_INPUT_MM_DL);
+ omap_abe_write_mixer(abe, MIXDL2, MUTE_GAIN,
+ RAMP_100MS, MIX_DL2_INPUT_MM_UL2);
+ omap_abe_write_mixer(abe, MIXSDT, MUTE_GAIN,
+ RAMP_100MS, MIX_SDT_INPUT_UP_MIXER);
+ omap_abe_write_mixer(abe, MIXSDT, GAIN_0dB,
+ RAMP_100MS, MIX_SDT_INPUT_DL1_MIXER);
+ omap_abe_write_mixer(abe, MIXECHO, MUTE_GAIN,
+ RAMP_100MS, MIX_ECHO_DL1);
+ omap_abe_write_mixer(abe, MIXECHO, MUTE_GAIN,
+ RAMP_100MS, MIX_ECHO_DL2);
+ omap_abe_write_mixer(abe, MIXAUDUL, MUTE_GAIN,
+ RAMP_100MS, MIX_AUDUL_INPUT_MM_DL);
+ omap_abe_write_mixer(abe, MIXAUDUL, MUTE_GAIN,
+ RAMP_100MS, MIX_AUDUL_INPUT_TONES);
+ omap_abe_write_mixer(abe, MIXAUDUL, GAIN_0dB,
+ RAMP_100MS, MIX_AUDUL_INPUT_UPLINK);
+ omap_abe_write_mixer(abe, MIXAUDUL, MUTE_GAIN,
+ RAMP_100MS, MIX_AUDUL_INPUT_VX_DL);
+ omap_abe_write_mixer(abe, MIXVXREC, MUTE_GAIN,
+ RAMP_100MS, MIX_VXREC_INPUT_TONES);
+ omap_abe_write_mixer(abe, MIXVXREC, MUTE_GAIN,
+ RAMP_100MS, MIX_VXREC_INPUT_VX_DL);
+ omap_abe_write_mixer(abe, MIXVXREC, MUTE_GAIN,
+ RAMP_100MS, MIX_VXREC_INPUT_MM_DL);
+ omap_abe_write_mixer(abe, MIXVXREC, MUTE_GAIN,
+ RAMP_100MS, MIX_VXREC_INPUT_VX_UL);
+ omap_abe_write_gain(abe, GAINS_DMIC1, GAIN_0dB,
+ RAMP_100MS, GAIN_LEFT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_DMIC1, GAIN_0dB,
+ RAMP_100MS, GAIN_RIGHT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_DMIC2, GAIN_0dB,
+ RAMP_100MS, GAIN_LEFT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_DMIC2, GAIN_0dB,
+ RAMP_100MS, GAIN_RIGHT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_DMIC3, GAIN_0dB,
+ RAMP_100MS, GAIN_LEFT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_DMIC3, GAIN_0dB,
+ RAMP_100MS, GAIN_RIGHT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_AMIC, GAIN_0dB,
+ RAMP_100MS, GAIN_LEFT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_AMIC, GAIN_0dB,
+ RAMP_100MS, GAIN_RIGHT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_SPLIT, GAIN_0dB,
+ RAMP_100MS, GAIN_LEFT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_SPLIT, GAIN_0dB,
+ RAMP_100MS, GAIN_RIGHT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_DL1, GAIN_0dB,
+ RAMP_100MS, GAIN_LEFT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_DL1, GAIN_0dB,
+ RAMP_100MS, GAIN_RIGHT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_DL2, GAIN_0dB,
+ RAMP_100MS, GAIN_LEFT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_DL2, GAIN_0dB,
+ RAMP_100MS, GAIN_RIGHT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_BTUL, GAIN_0dB,
+ RAMP_100MS, GAIN_LEFT_OFFSET);
+ omap_abe_write_gain(abe, GAINS_BTUL, GAIN_0dB,
+ RAMP_100MS, GAIN_RIGHT_OFFSET);
+}
diff --git a/sound/soc/omap/abe/abe_initxxx_labels.h b/sound/soc/omap/abe/abe_initxxx_labels.h
new file mode 100644
index 0000000..2331dfb
--- /dev/null
+++ b/sound/soc/omap/abe/abe_initxxx_labels.h
@@ -0,0 +1,372 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_INITXXX_LABELS_H_
+#define _ABE_INITXXX_LABELS_H_
+
+#define Dummy_Regs_labelID 0
+#define Dummy_AM_labelID 1
+#define Voice_8k_UL_labelID 2
+#define Voice_8k_DL_labelID 3
+#define ECHO_REF_8K_labelID 4
+#define Voice_16k_UL_labelID 5
+#define Voice_16k_DL_labelID 6
+#define ECHO_REF_16K_labelID 7
+#define MM_DL_labelID 8
+#define IO_VX_DL_ASRC_labelID 9
+#define IO_MM_EXT_IN_ASRC_labelID 10
+#define IO_VIBRA_DL_labelID 11
+#define ZERO_labelID 12
+#define GTarget_labelID 13
+#define GCurrent_labelID 14
+#define Gr_1_labelID 15
+#define Gr_2_labelID 16
+#define Gr_Regs_labelID 17
+#define DMIC0_Gain_labelID 18
+#define DMIC1_Gain_labelID 19
+#define DMIC2_Gain_labelID 20
+#define DMIC3_Gain_labelID 21
+#define AMIC_Gain_labelID 22
+#define MIXDL1_Gain_labelID 23
+#define MIXDL2_Gain_labelID 24
+#define DEFAULT_Gain_labelID 25
+#define DL1_M_G_Tones_labelID 26
+#define DL2_M_G_Tones_labelID 27
+#define Echo_M_G_labelID 28
+#define SDT_M_G_labelID 29
+#define VXREC_M_G_VX_DL_labelID 30
+#define UL_M_G_VX_DL_labelID 31
+#define BTUL_Gain_labelID 32
+#define DL1_M_labelID 33
+#define DL2_M_labelID 34
+#define MM_UL2_labelID 35
+#define VX_DL_labelID 36
+#define Tones_labelID 37
+#define DL_M_MM_UL2_VX_DL_labelID 38
+#define Echo_M_labelID 39
+#define VX_UL_labelID 40
+#define VX_UL_M_labelID 41
+#define SDT_F_labelID 42
+#define SDT_F_data_labelID 43
+#define SDT_Coef_labelID 44
+#define SDT_Regs_labelID 45
+#define SDT_M_labelID 46
+#define DL1_EQ_labelID 47
+#define DL2_EQ_labelID 48
+#define DL1_GAIN_out_labelID 49
+#define DL2_GAIN_out_labelID 50
+#define DMIC1_labelID 51
+#define DMIC1_L_labelID 52
+#define DMIC1_R_labelID 53
+#define DMIC2_labelID 54
+#define DMIC2_L_labelID 55
+#define DMIC2_R_labelID 56
+#define DMIC3_labelID 57
+#define DMIC3_L_labelID 58
+#define DMIC3_R_labelID 59
+#define MIC4_labelID 60
+#define MIC4_L_labelID 61
+#define MIC4_R_labelID 62
+#define BT_UL_L_labelID 63
+#define BT_UL_R_labelID 64
+#define AMIC_labelID 65
+#define AMIC_L_labelID 66
+#define AMIC_R_labelID 67
+#define EchoRef_L_labelID 68
+#define EchoRef_R_labelID 69
+#define MM_DL_L_labelID 70
+#define MM_DL_R_labelID 71
+#define MM_UL_labelID 72
+#define AMIC_96_labelID 73
+#define DMIC0_96_labelID 74
+#define DMIC1_96_labelID 75
+#define DMIC2_96_labelID 76
+#define UL_MIC_48K_labelID 77
+#define EQ_DL_48K_labelID 78
+#define EQ_48K_labelID 79
+#define McPDM_Out1_labelID 80
+#define McPDM_Out2_labelID 81
+#define McPDM_Out3_labelID 82
+#define VX_UL_MUX_labelID 83
+#define MM_UL2_MUX_labelID 84
+#define MM_UL_MUX_labelID 85
+#define XinASRC_DL_VX_labelID 86
+#define ASRC_DL_VX_Coefs_labelID 87
+#define ASRC_DL_VX_Alpha_labelID 88
+#define ASRC_DL_VX_VarsBeta_labelID 89
+#define ASRC_DL_VX_8k_Regs_labelID 90
+#define XinASRC_UL_VX_labelID 91
+#define ASRC_UL_VX_Coefs_labelID 92
+#define ASRC_UL_VX_Alpha_labelID 93
+#define ASRC_UL_VX_VarsBeta_labelID 94
+#define ASRC_UL_VX_8k_Regs_labelID 95
+#define UL_48_8_DEC_labelID 96
+#define ASRC_DL_VX_16k_Regs_labelID 97
+#define ASRC_UL_VX_16k_Regs_labelID 98
+#define UL_48_16_DEC_labelID 99
+#define XinASRC_MM_EXT_IN_labelID 100
+#define ASRC_MM_EXT_IN_Coefs_labelID 101
+#define ASRC_MM_EXT_IN_Alpha_labelID 102
+#define ASRC_MM_EXT_IN_VarsBeta_labelID 103
+#define ASRC_MM_EXT_IN_Regs_labelID 104
+#define VX_REC_labelID 105
+#define VXREC_UL_M_Tones_VX_UL_labelID 106
+#define VX_REC_L_labelID 107
+#define VX_REC_R_labelID 108
+#define DL2_M_L_labelID 109
+#define DL2_M_R_labelID 110
+#define DL1_M_data_labelID 111
+#define DL1_M_Coefs_labelID 112
+#define DL2_M_LR_data_labelID 113
+#define DL2_M_LR_Coefs_labelID 114
+#define SRC_6_LP_COEFS_labelID 115
+#define SRC_6_LP_GAIN_COEFS_labelID 116
+#define SRC_6_HP_COEFS_labelID 117
+#define SRC_3_LP_COEFS_labelID 118
+#define SRC_3_LP_GAIN_COEFS_labelID 119
+#define SRC_3_HP_COEFS_labelID 120
+#define VX_DL_8_48_LP_DATA_labelID 121
+#define VX_DL_8_48_HP_DATA_labelID 122
+#define VX_DL_16_48_LP_DATA_labelID 123
+#define VX_DL_16_48_HP_DATA_labelID 124
+#define VX_UL_48_8_LP_DATA_labelID 125
+#define VX_UL_48_8_HP_DATA_labelID 126
+#define VX_UL_48_16_LP_DATA_labelID 127
+#define VX_UL_48_16_HP_DATA_labelID 128
+#define BT_UL_8_48_LP_DATA_labelID 129
+#define BT_UL_8_48_HP_DATA_labelID 130
+#define BT_UL_16_48_LP_DATA_labelID 131
+#define BT_UL_16_48_HP_DATA_labelID 132
+#define BT_DL_48_8_LP_DATA_labelID 133
+#define BT_DL_48_8_HP_DATA_labelID 134
+#define BT_DL_48_16_LP_DATA_labelID 135
+#define BT_DL_48_16_HP_DATA_labelID 136
+#define ECHO_REF_48_16_LP_DATA_labelID 137
+#define ECHO_REF_48_16_HP_DATA_labelID 138
+#define ECHO_REF_48_8_LP_DATA_labelID 139
+#define ECHO_REF_48_8_HP_DATA_labelID 140
+#define ECHO_REF_DEC_labelID 141
+#define VX_UL_8_TEMP_labelID 142
+#define VX_UL_16_TEMP_labelID 143
+#define UP_DOWN_8_48_labelID 144
+#define UP_DOWN_16_48_labelID 145
+#define SRC_6_LP_48k_labelID 146
+#define SRC_6_HP_labelID 147
+#define SRC_3_LP_48k_labelID 148
+#define SRC_3_HP_labelID 149
+#define EARP_48_96_LP_DATA_labelID 150
+#define SRC_48_96_LP_labelID 151
+#define IHF_48_96_LP_DATA_labelID 152
+#define EQ_VX_UL_16K_labelID 153
+#define pAPS_iir1_p23_labelID 154
+#define pAPS_iir1_p45_labelID 155
+#define APS_IIR_Regs_labelID 156
+#define pAPS_core_DL1_p1_labelID 157
+#define pAPS_core_DL1_p23_labelID 158
+#define pAPS_core_DL1_p45_labelID 159
+#define pAPS_core_DL1_r_labelID 160
+#define pAPS_DL2L_core_r_labelID 161
+#define pAPS_DL2R_core_r_labelID 162
+#define pAPS_COIL_core_DL1_p1_labelID 163
+#define pAPS_COIL_core_DL1_p23_labelID 164
+#define pAPS_COIL_core_DL1_p45_labelID 165
+#define pAPS_COIL_core_DL1_r_labelID 166
+#define DL2_L_APS_IIR_p23_labelID 167
+#define DL2_R_APS_IIR_p23_labelID 168
+#define DL2_L_APS_IIR_p45_labelID 169
+#define DL2_R_APS_IIR_p45_labelID 170
+#define DL2_L_APS_CORE_p1_labelID 171
+#define DL2_L_APS_CORE_p23_labelID 172
+#define DL2_L_APS_CORE_p45_labelID 173
+#define DL2_R_APS_CORE_p1_labelID 174
+#define DL2_R_APS_CORE_p23_labelID 175
+#define DL2_R_APS_CORE_p45_labelID 176
+#define DL2_L_APS_COIL_CORE_p1_labelID 177
+#define DL2_L_APS_COIL_CORE_p23_labelID 178
+#define DL2_L_APS_COIL_CORE_p45_labelID 179
+#define pAPS_COIL_DL2L_core_r_labelID 180
+#define DL2_R_APS_COIL_CORE_p1_labelID 181
+#define DL2_R_APS_COIL_CORE_p23_labelID 182
+#define DL2_R_APS_COIL_CORE_p45_labelID 183
+#define pAPS_COIL_DL2R_core_r_labelID 184
+#define DL1_APS_labelID 185
+#define DL2_L_APS_labelID 186
+#define DL2_R_APS_labelID 187
+#define DL1_APS_EQ_p23_labelID 188
+#define DL1_APS_EQ_p45_labelID 189
+#define DL2_APS_EQ_p23_labelID 190
+#define DL2_APS_EQ_p45_labelID 191
+#define pVIBRA1_p0_labelID 192
+#define pVIBRA1_p1_labelID 193
+#define pVIBRA1_p23_labelID 194
+#define pVIBRA1_p45_labelID 195
+#define pVibra1_pR1_labelID 196
+#define pVibra1_pR2_labelID 197
+#define pVibra1_pR3_labelID 198
+#define pVIBRA1_r_labelID 199
+#define pVIBRA2_p0_labelID 200
+#define pVIBRA2_p1_labelID 201
+#define pVIBRA2_p23_labelID 202
+#define pVIBRA2_p45_labelID 203
+#define pCtrl_p67_labelID 204
+#define pVIBRA2_r_labelID 205
+#define VIBRA_labelID 206
+#define PING_labelID 207
+#define PING_Regs_labelID 208
+#define UP_48_96_LP_COEFS_labelID 209
+#define AMIC_96_48_data_labelID 210
+#define DOWN_96_48_AMIC_Coefs_labelID 211
+#define DOWN_96_48_DMIC_Coefs_labelID 212
+#define DOWN_96_48_AMIC_Regs_labelID 213
+#define DOWN_96_48_DMIC_Regs_labelID 214
+#define DMIC0_96_48_data_labelID 215
+#define DMIC1_96_48_data_labelID 216
+#define DMIC2_96_48_data_labelID 217
+#define SIO_DMIC_labelID 218
+#define SIO_PDM_UL_labelID 219
+#define SIO_BT_VX_UL_labelID 220
+#define SIO_MM_UL_labelID 221
+#define SIO_MM_UL2_labelID 222
+#define SIO_VX_UL_labelID 223
+#define SIO_MM_DL_labelID 224
+#define SIO_VX_DL_labelID 225
+#define SIO_TONES_DL_labelID 226
+#define SIO_VIB_DL_labelID 227
+#define SIO_BT_VX_DL_labelID 228
+#define SIO_PDM_DL_labelID 229
+#define SIO_MM_EXT_OUT_labelID 230
+#define SIO_MM_EXT_IN_labelID 231
+#define SIO_TDM_OUT_labelID 232
+#define SIO_TDM_IN_labelID 233
+#define DMIC_ATC_PTR_labelID 234
+#define MCPDM_UL_ATC_PTR_labelID 235
+#define BT_VX_UL_ATC_PTR_labelID 236
+#define MM_UL_ATC_PTR_labelID 237
+#define MM_UL2_ATC_PTR_labelID 238
+#define VX_UL_ATC_PTR_labelID 239
+#define MM_DL_ATC_PTR_labelID 240
+#define VX_DL_ATC_PTR_labelID 241
+#define TONES_DL_ATC_PTR_labelID 242
+#define VIB_DL_ATC_PTR_labelID 243
+#define BT_VX_DL_ATC_PTR_labelID 244
+#define PDM_DL_ATC_PTR_labelID 245
+#define MM_EXT_OUT_ATC_PTR_labelID 246
+#define MM_EXT_IN_ATC_PTR_labelID 247
+#define TDM_OUT_ATC_PTR_labelID 248
+#define TDM_IN_ATC_PTR_labelID 249
+#define MCU_IRQ_FIFO_ptr_labelID 250
+#define DEBUG_IRQ_FIFO_reg_labelID 251
+#define UP_DOWN_48_96_labelID 252
+#define OSR96_2_labelID 253
+#define DEBUG_GAINS_labelID 254
+#define DBG_8K_PATTERN_labelID 255
+#define DBG_16K_PATTERN_labelID 256
+#define DBG_24K_PATTERN_labelID 257
+#define DBG_48K_PATTERN_labelID 258
+#define DBG_96K_PATTERN_labelID 259
+#define UL_VX_UL_48_8K_labelID 260
+#define UL_VX_UL_48_16K_labelID 261
+#define BT_DL_labelID 262
+#define BT_UL_labelID 263
+#define BT_DL_8k_labelID 264
+#define BT_DL_16k_labelID 265
+#define BT_UL_8k_labelID 266
+#define BT_UL_16k_labelID 267
+#define MM_EXT_IN_labelID 268
+#define MM_EXT_IN_L_labelID 269
+#define MM_EXT_IN_R_labelID 270
+#define ECHO_REF_48_16_WRAP_labelID 271
+#define ECHO_REF_48_8_WRAP_labelID 272
+#define BT_UL_16_48_WRAP_labelID 273
+#define BT_UL_8_48_WRAP_labelID 274
+#define BT_DL_48_16_WRAP_labelID 275
+#define BT_DL_48_8_WRAP_labelID 276
+#define VX_DL_16_48_WRAP_labelID 277
+#define VX_DL_8_48_WRAP_labelID 278
+#define VX_UL_48_16_WRAP_labelID 279
+#define VX_UL_48_8_WRAP_labelID 280
+#define APS_DL1_IRQs_WRAP_labelID 281
+#define APS_DL2_L_IRQs_WRAP_labelID 282
+#define APS_DL2_R_IRQs_WRAP_labelID 283
+#define ATC_NULL_BUFFER_labelID 284
+#define MEM_INIT_hal_mem_labelID 285
+#define MEM_INIT_write_mem_labelID 286
+#define MEM_INIT_regs_labelID 287
+#define GAIN_0DB_labelID 288
+#define XinASRC_BT_UL_labelID 289
+#define IO_BT_UL_ASRC_labelID 290
+#define ASRC_BT_UL_Coefs_labelID 291
+#define ASRC_BT_UL_Alpha_labelID 292
+#define ASRC_BT_UL_VarsBeta_labelID 293
+#define ASRC_BT_UL_8k_Regs_labelID 294
+#define ASRC_BT_UL_16k_Regs_labelID 295
+#define XinASRC_BT_DL_labelID 296
+#define DL_48_8_DEC_labelID 297
+#define DL_48_16_DEC_labelID 298
+#define BT_DL_8k_TEMP_labelID 299
+#define BT_DL_16k_TEMP_labelID 300
+#define BT_DL_8k_opp100_labelID 301
+#define BT_DL_16k_opp100_labelID 302
+#define ASRC_BT_DL_Coefs_labelID 303
+#define ASRC_BT_DL_Alpha_labelID 304
+#define ASRC_BT_DL_VarsBeta_labelID 305
+#define ASRC_BT_DL_8k_Regs_labelID 306
+#define ASRC_BT_DL_16k_Regs_labelID 307
+#define BT_DL_48_8_OPP100_WRAP_labelID 308
+#define BT_DL_48_16_OPP100_WRAP_labelID 309
+#endif /* _ABE_INITXXXX_LABELS_H_ */
diff --git a/sound/soc/omap/abe/abe_irq.c b/sound/soc/omap/abe/abe_irq.c
new file mode 100644
index 0000000..d639894
--- /dev/null
+++ b/sound/soc/omap/abe/abe_irq.c
@@ -0,0 +1,107 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#include "abe_legacy.h"
+
+extern u32 abe_irq_pingpong_player_id;
+
+/*
+ * initialize the default values for call-backs to subroutines
+ * - FIFO IRQ call-backs for sequenced tasks
+ * - FIFO IRQ call-backs for audio player/recorders (ping-pong protocols)
+ * - Remote debugger interface
+ * - Error monitoring
+ * - Activity Tracing
+ */
+/**
+ * abe_irq_ping_pong
+ *
+ * Call the respective subroutine depending on the IRQ FIFO content:
+ * APS interrupts : IRQ_FIFO[31:28] = IRQtag_APS,
+ * IRQ_FIFO[27:16] = APS_IRQs, IRQ_FIFO[15:0] = loopCounter
+ * SEQ interrupts : IRQ_FIFO[31:28] = IRQtag_COUNT,
+ * IRQ_FIFO[27:16] = Count_IRQs, IRQ_FIFO[15:0] = loopCounter
+ * Ping-Pong Interrupts : IRQ_FIFO[31:28] = IRQtag_PP,
+ * IRQ_FIFO[27:16] = PP_MCU_IRQ, IRQ_FIFO[15:0] = loopCounter
+ */
+void abe_irq_ping_pong(void)
+{
+ abe_call_subroutine(abe_irq_pingpong_player_id, NOPARAMETER,
+ NOPARAMETER, NOPARAMETER, NOPARAMETER);
+}
+/**
+ * abe_irq_check_for_sequences
+* @i: sequence ID
+ *
+ * check the active sequence list
+ *
+ */
+void abe_irq_check_for_sequences(u32 i)
+{
+}
+/**
+ * abe_irq_aps
+ *
+ * call the application subroutines that updates
+ * the acoustics protection filters
+ */
+void abe_irq_aps(u32 aps_info)
+{
+ abe_call_subroutine(abe_irq_aps_adaptation_id, NOPARAMETER, NOPARAMETER,
+ NOPARAMETER, NOPARAMETER);
+}
diff --git a/sound/soc/omap/abe/abe_legacy.h b/sound/soc/omap/abe/abe_legacy.h
new file mode 100644
index 0000000..ca73dc2
--- /dev/null
+++ b/sound/soc/omap/abe/abe_legacy.h
@@ -0,0 +1,98 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_MAIN_H_
+#define _ABE_MAIN_H_
+
+#include <linux/io.h>
+
+#include "abe_dm_addr.h"
+#include "abe_sm_addr.h"
+#include "abe_cm_addr.h"
+#include "abe_define.h"
+#include "abe_fw.h"
+#include "abe_def.h"
+#include "abe_typ.h"
+#include "abe_ext.h"
+#include "abe_dbg.h"
+#include "abe_ref.h"
+#include "abe_api.h"
+#include "abe_typedef.h"
+#include "abe_functionsid.h"
+#include "abe_taskid.h"
+#include "abe_initxxx_labels.h"
+#include "abe_fw.h"
+
+/* pipe connection to the TARGET simulator */
+#define ABE_DEBUG_CHECKERS 0
+/* simulator data extracted from a text-file */
+#define ABE_DEBUG_HWFILE 0
+/* low-level log files */
+#define ABE_DEBUG_LL_LOG 0
+
+extern struct omap_abe *abe;
+
+void omap_abe_dbg_log(struct omap_abe *abe, u32 x, u32 y, u32 z, u32 t);
+void omap_abe_dbg_error(struct omap_abe *abe, int level, int error);
+
+/*
+ * MACROS
+ */
+#define _log(x, y, z, t) { if (x & abe->dbg.mask) omap_abe_dbg_log(abe, x, y, z, t); }
+
+#endif /* _ABE_MAIN_H_ */
diff --git a/sound/soc/omap/abe/abe_main.c b/sound/soc/omap/abe/abe_main.c
new file mode 100644
index 0000000..6c70a99
--- /dev/null
+++ b/sound/soc/omap/abe/abe_main.c
@@ -0,0 +1,727 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+
+#include "abe_legacy.h"
+#include "abe_dbg.h"
+#include "abe_port.h"
+
+
+struct omap_abe_equ {
+ /* type of filter */
+ u32 equ_type;
+ /* filter length */
+ u32 equ_length;
+ union {
+ /* parameters are the direct and recursive coefficients in */
+ /* Q6.26 integer fixed-point format. */
+ s32 type1[NBEQ1];
+ struct {
+ /* center frequency of the band [Hz] */
+ s32 freq[NBEQ2];
+ /* gain of each band. [dB] */
+ s32 gain[NBEQ2];
+ /* Q factor of this band [dB] */
+ s32 q[NBEQ2];
+ } type2;
+ } coef;
+ s32 equ_param3;
+};
+
+#include "abe_gain.h"
+#include "abe_aess.h"
+#include "abe_seq.h"
+
+
+int omap_abe_connect_debug_trace(struct omap_abe *abe,
+ struct omap_abe_dma *dma2);
+
+int omap_abe_reset_hal(struct omap_abe *abe);
+int omap_abe_load_fw(struct omap_abe *abe);
+int omap_abe_wakeup(struct omap_abe *abe);
+int omap_abe_irq_processing(struct omap_abe *abe);
+int omap_abe_clear_irq(struct omap_abe *abe);
+int omap_abe_disable_irq(struct omap_abe *abe);
+int omap_abe_set_debug_trace(struct omap_abe_dbg *dbg, int debug);
+int omap_abe_set_ping_pong_buffer(struct omap_abe *abe,
+ u32 port, u32 n_bytes);
+int omap_abe_read_next_ping_pong_buffer(struct omap_abe *abe,
+ u32 port, u32 *p, u32 *n);
+int omap_abe_init_ping_pong_buffer(struct omap_abe *abe,
+ u32 id, u32 size_bytes, u32 n_buffers,
+ u32 *p);
+int omap_abe_read_offset_from_ping_buffer(struct omap_abe *abe,
+ u32 id, u32 *n);
+int omap_abe_set_router_configuration(struct omap_abe *abe,
+ u32 id, u32 k, u32 *param);
+int omap_abe_set_opp_processing(struct omap_abe *abe, u32 opp);
+int omap_abe_disable_data_transfer(struct omap_abe *abe, u32 id);
+int omap_abe_enable_data_transfer(struct omap_abe *abe, u32 id);
+int omap_abe_connect_cbpr_dmareq_port(struct omap_abe *abe,
+ u32 id, abe_data_format_t *f,
+ u32 d,
+ abe_dma_t *returned_dma_t);
+int omap_abe_connect_irq_ping_pong_port(struct omap_abe *abe,
+ u32 id, abe_data_format_t *f,
+ u32 subroutine_id, u32 size,
+ u32 *sink, u32 dsp_mcu_flag);
+int omap_abe_connect_serial_port(struct omap_abe *abe,
+ u32 id, abe_data_format_t *f,
+ u32 mcbsp_id);
+int omap_abe_read_port_address(struct omap_abe *abe,
+ u32 port, abe_dma_t *dma2);
+int omap_abe_check_activity(struct omap_abe *abe);
+
+int omap_abe_use_compensated_gain(struct omap_abe *abe, int on_off);
+int omap_abe_write_equalizer(struct omap_abe *abe,
+ u32 id, struct omap_abe_equ *param);
+
+int omap_abe_disable_gain(struct omap_abe *abe, u32 id, u32 p);
+int omap_abe_enable_gain(struct omap_abe *abe, u32 id, u32 p);
+int omap_abe_mute_gain(struct omap_abe *abe, u32 id, u32 p);
+int omap_abe_unmute_gain(struct omap_abe *abe, u32 id, u32 p);
+
+int omap_abe_write_gain(struct omap_abe *abe,
+ u32 id, s32 f_g, u32 ramp, u32 p);
+int omap_abe_write_mixer(struct omap_abe *abe,
+ u32 id, s32 f_g, u32 f_ramp, u32 p);
+int omap_abe_read_gain(struct omap_abe *abe,
+ u32 id, u32 *f_g, u32 p);
+int omap_abe_read_mixer(struct omap_abe *abe,
+ u32 id, u32 *f_g, u32 p);
+
+extern struct omap_abe *abe;
+
+#if 0
+/**
+ * abe_init_mem - Allocate Kernel space memory map for ABE
+ *
+ * Memory map of ABE memory space for PMEM/DMEM/SMEM/DMEM
+ */
+void abe_init_mem(void __iomem *_io_base)
+{
+ omap_abe_init_mem(abe, _io_base);
+}
+EXPORT_SYMBOL(abe_init_mem);
+
+struct omap_abe* abe_probe_aess(void)
+{
+ return omap_abe_probe_aess(abe);
+}
+EXPORT_SYMBOL(abe_probe_aess);
+
+void abe_remove_aess(void)
+{
+ omap_abe_remove_aess(abe);
+}
+EXPORT_SYMBOL(abe_remove_aess);
+
+void abe_add_subroutine(u32 *id, abe_subroutine2 f,
+ u32 nparam, u32 *params)
+{
+ omap_abe_add_subroutine(abe, id, f, nparam, params);
+}
+EXPORT_SYMBOL(abe_add_subroutine);
+
+#endif
+
+/**
+ * abe_reset_hal - reset the ABE/HAL
+ * @rdev: regulator source
+ * @constraints: constraints to apply
+ *
+ * Operations : reset the HAL by reloading the static variables and
+ * default AESS registers.
+ * Called after a PRCM cold-start reset of ABE
+ */
+u32 abe_reset_hal(void)
+{
+ omap_abe_reset_hal(abe);
+ return 0;
+}
+EXPORT_SYMBOL(abe_reset_hal);
+
+/**
+ * abe_load_fw - Load ABE Firmware and initialize memories
+ *
+ */
+u32 abe_load_fw(void)
+{
+ omap_abe_load_fw(abe);
+ return 0;
+}
+EXPORT_SYMBOL(abe_load_fw);
+
+/**
+ * abe_wakeup - Wakeup ABE
+ *
+ * Wakeup ABE in case of retention
+ */
+u32 abe_wakeup(void)
+{
+ omap_abe_wakeup(abe);
+ return 0;
+}
+EXPORT_SYMBOL(abe_wakeup);
+
+/**
+ * abe_irq_processing - Process ABE interrupt
+ *
+ * This subroutine is call upon reception of "MA_IRQ_99 ABE_MPU_IRQ" Audio
+ * back-end interrupt. This subroutine will check the ATC Hrdware, the
+ * IRQ_FIFO from the AE and act accordingly. Some IRQ source are originated
+ * for the delivery of "end of time sequenced tasks" notifications, some are
+ * originated from the Ping-Pong protocols, some are generated from
+ * the embedded debugger when the firmware stops on programmable break-points,
+ * etc ...
+ */
+u32 abe_irq_processing(void)
+{
+ omap_abe_irq_processing(abe);
+ return 0;
+}
+EXPORT_SYMBOL(abe_irq_processing);
+
+/**
+ * abe_clear_irq - clear ABE interrupt
+ *
+ * This subroutine is call to clear MCU Irq
+ */
+u32 abe_clear_irq(void)
+{
+ omap_abe_clear_irq(abe);
+ return 0;
+}
+EXPORT_SYMBOL(abe_clear_irq);
+
+/**
+ * abe_disable_irq - disable MCU/DSP ABE interrupt
+ *
+ * This subroutine is disabling ABE MCU/DSP Irq
+ */
+u32 abe_disable_irq(void)
+{
+ omap_abe_disable_irq(abe);
+
+ return 0;
+}
+EXPORT_SYMBOL(abe_disable_irq);
+
+/**
+ * abe_write_event_generator - Selects event generator source
+ * @e: Event Generation Counter, McPDM, DMIC or default.
+ *
+ * Loads the AESS event generator hardware source.
+ * Loads the firmware parameters accordingly.
+ * Indicates to the FW which data stream is the most important to preserve
+ * in case all the streams are asynchronous.
+ * If the parameter is "default", then HAL decides which Event source
+ * is the best appropriate based on the opened ports.
+ *
+ * When neither the DMIC and the McPDM are activated, the AE will have
+ * its EVENT generator programmed with the EVENT_COUNTER.
+ * The event counter will be tuned in order to deliver a pulse frequency higher
+ * than 96 kHz.
+ * The DPLL output at 100% OPP is MCLK = (32768kHz x6000) = 196.608kHz
+ * The ratio is (MCLK/96000)+(1<<1) = 2050
+ * (1<<1) in order to have the same speed at 50% and 100% OPP
+ * (only 15 MSB bits are used at OPP50%)
+ */
+u32 abe_write_event_generator(u32 e) // should integarte abe as parameter
+{
+ omap_abe_write_event_generator(abe, e);
+ return 0;
+}
+EXPORT_SYMBOL(abe_write_event_generator);
+
+/**
+ * abe_start_event_generator - Starts event generator source
+ *
+ * Start the event genrator of AESS. No more event will be send to AESS engine.
+ * Upper layer must wait 1/96kHz to be sure that engine reaches
+ * the IDLE instruction.
+ */
+u32 abe_stop_event_generator(void)
+{
+ omap_abe_stop_event_generator(abe);
+ return 0;
+}
+EXPORT_SYMBOL(abe_stop_event_generator);
+
+/**
+ * abe_connect_debug_trace
+ * @dma2:pointer to the DMEM trace buffer
+ *
+ * returns the address and size of the real-time debug trace buffer,
+ * the content of which will vary from one firmware release to another
+ */
+u32 abe_connect_debug_trace(abe_dma_t *dma2)
+{
+ omap_abe_connect_debug_trace(abe, (struct omap_abe_dma *)dma2);
+ return 0;
+}
+EXPORT_SYMBOL(abe_connect_debug_trace);
+
+/**
+ * abe_set_debug_trace
+ * @debug: debug ID from a list to be defined
+ *
+ * loads a mask which filters the debug trace to dedicated types of data
+ */
+u32 abe_set_debug_trace(abe_dbg_t debug)
+{
+ omap_abe_set_debug_trace(&abe->dbg, (int)(debug));
+ return 0;
+}
+EXPORT_SYMBOL(abe_set_debug_trace);
+
+/**
+ * abe_set_ping_pong_buffer
+ * @port: ABE port ID
+ * @n_bytes: Size of Ping/Pong buffer
+ *
+ * Updates the next ping-pong buffer with "size" bytes copied from the
+ * host processor. This API notifies the FW that the data transfer is done.
+ */
+u32 abe_set_ping_pong_buffer(u32 port, u32 n_bytes)
+{
+ omap_abe_set_ping_pong_buffer(abe, port, n_bytes);
+ return 0;
+}
+EXPORT_SYMBOL(abe_set_ping_pong_buffer);
+
+/**
+ * abe_read_next_ping_pong_buffer
+ * @port: ABE portID
+ * @p: Next buffer address (pointer)
+ * @n: Next buffer size (pointer)
+ *
+ * Tell the next base address of the next ping_pong Buffer and its size
+ */
+u32 abe_read_next_ping_pong_buffer(u32 port, u32 *p, u32 *n)
+{
+ omap_abe_read_next_ping_pong_buffer(abe, port, p, n);
+ return 0;
+}
+EXPORT_SYMBOL(abe_read_next_ping_pong_buffer);
+
+/**
+ * abe_init_ping_pong_buffer
+ * @id: ABE port ID
+ * @size_bytes:size of the ping pong
+ * @n_buffers:number of buffers (2 = ping/pong)
+ * @p:returned address of the ping-pong list of base addresses
+ * (byte offset from DMEM start)
+ *
+ * Computes the base address of the ping_pong buffers
+ */
+u32 abe_init_ping_pong_buffer(u32 id, u32 size_bytes, u32 n_buffers,
+ u32 *p)
+{
+ omap_abe_init_ping_pong_buffer(abe, id, size_bytes, n_buffers, p);
+ return 0;
+}
+EXPORT_SYMBOL(abe_init_ping_pong_buffer);
+
+/**
+ * abe_read_offset_from_ping_buffer
+ * @id: ABE port ID
+ * @n: returned address of the offset
+ * from the ping buffer start address (in samples)
+ *
+ * Computes the current firmware ping pong read pointer location,
+ * expressed in samples, as the offset from the start address of ping buffer.
+ */
+u32 abe_read_offset_from_ping_buffer(u32 id, u32 *n)
+{
+ omap_abe_read_offset_from_ping_buffer(abe, id, n);
+ return 0;
+}
+EXPORT_SYMBOL(abe_read_offset_from_ping_buffer);
+
+/**
+ * abe_write_equalizer
+ * @id: name of the equalizer
+ * @param : equalizer coefficients
+ *
+ * Load the coefficients in CMEM.
+ */
+u32 abe_write_equalizer(u32 id, abe_equ_t *param)
+{
+ omap_abe_write_equalizer(abe, id, (struct omap_abe_equ *)param);
+ return 0;
+}
+EXPORT_SYMBOL(abe_write_equalizer);
+/**
+ * abe_disable_gain
+ * Parameters:
+ * mixer id
+ * sub-port id
+ *
+ */
+u32 abe_disable_gain(u32 id, u32 p)
+{
+ omap_abe_disable_gain(abe, id, p);
+ return 0;
+}
+EXPORT_SYMBOL(abe_disable_gain);
+/**
+ * abe_enable_gain
+ * Parameters:
+ * mixer id
+ * sub-port id
+ *
+ */
+u32 abe_enable_gain(u32 id, u32 p)
+{
+ omap_abe_enable_gain(abe, id, p);
+ return 0;
+}
+
+/**
+ * abe_mute_gain
+ * Parameters:
+ * mixer id
+ * sub-port id
+ *
+ */
+u32 abe_mute_gain(u32 id, u32 p)
+{
+ omap_abe_mute_gain(abe, id, p);
+ return 0;
+}
+EXPORT_SYMBOL(abe_mute_gain);
+
+/**
+ * abe_unmute_gain
+ * Parameters:
+ * mixer id
+ * sub-port id
+ *
+ */
+u32 abe_unmute_gain(u32 id, u32 p)
+{
+ omap_abe_unmute_gain(abe, id, p);
+ return 0;
+}
+EXPORT_SYMBOL(abe_unmute_gain);
+
+/**
+ * abe_write_gain
+ * @id: gain name or mixer name
+ * @f_g: list of input gains of the mixer
+ * @ramp: gain ramp speed factor
+ * @p: list of ports corresponding to the above gains
+ *
+ * Loads the gain coefficients to FW memory. This API can be called when
+ * the corresponding MIXER is not activated. After reloading the firmware
+ * the default coefficients corresponds to "all input and output mixer's gain
+ * in mute state". A mixer is disabled with a network reconfiguration
+ * corresponding to an OPP value.
+ */
+u32 abe_write_gain(u32 id, s32 f_g, u32 ramp, u32 p)
+{
+ omap_abe_write_gain(abe, id, f_g, ramp, p);
+ return 0;
+}
+EXPORT_SYMBOL(abe_write_gain);
+
+/**
+ * abe_write_mixer
+ * @id: name of the mixer
+ * @param: input gains and delay ramp of the mixer
+ * @p: port corresponding to the above gains
+ *
+ * Load the gain coefficients in FW memory. This API can be called when
+ * the corresponding MIXER is not activated. After reloading the firmware
+ * the default coefficients corresponds to "all input and output mixer's
+ * gain in mute state". A mixer is disabled with a network reconfiguration
+ * corresponding to an OPP value.
+ */
+u32 abe_write_mixer(u32 id, s32 f_g, u32 f_ramp, u32 p)
+{
+ omap_abe_write_gain(abe, id, f_g, f_ramp, p);
+ return 0;
+}
+EXPORT_SYMBOL(abe_write_mixer);
+
+/**
+ * abe_read_gain
+ * @id: name of the mixer
+ * @param: list of input gains of the mixer
+ * @p: list of port corresponding to the above gains
+ *
+ */
+u32 abe_read_gain(u32 id, u32 *f_g, u32 p)
+{
+ omap_abe_read_gain(abe, id, f_g, p);
+ return 0;
+}
+EXPORT_SYMBOL(abe_read_gain);
+
+/**
+ * abe_read_mixer
+ * @id: name of the mixer
+ * @param: gains of the mixer
+ * @p: port corresponding to the above gains
+ *
+ * Load the gain coefficients in FW memory. This API can be called when
+ * the corresponding MIXER is not activated. After reloading the firmware
+ * the default coefficients corresponds to "all input and output mixer's
+ * gain in mute state". A mixer is disabled with a network reconfiguration
+ * corresponding to an OPP value.
+ */
+u32 abe_read_mixer(u32 id, u32 *f_g, u32 p)
+{
+ omap_abe_read_gain(abe, id, f_g, p);
+ return 0;
+}
+EXPORT_SYMBOL(abe_read_mixer);
+
+/**
+ * abe_set_router_configuration
+ * @Id: name of the router
+ * @Conf: id of the configuration
+ * @param: list of output index of the route
+ *
+ * The uplink router takes its input from DMIC (6 samples), AMIC (2 samples)
+ * and PORT1/2 (2 stereo ports). Each sample will be individually stored in
+ * an intermediate table of 10 elements.
+ *
+ * Example of router table parameter for voice uplink with phoenix microphones
+ *
+ * indexes 0 .. 9 = MM_UL description (digital MICs and MMEXTIN)
+ * DMIC1_L_labelID, DMIC1_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID,
+ * MM_EXT_IN_L_labelID, MM_EXT_IN_R_labelID, ZERO_labelID, ZERO_labelID,
+ * ZERO_labelID, ZERO_labelID,
+ * indexes 10 .. 11 = MM_UL2 description (recording on DMIC3)
+ * DMIC3_L_labelID, DMIC3_R_labelID,
+ * indexes 12 .. 13 = VX_UL description (VXUL based on PDMUL data)
+ * AMIC_L_labelID, AMIC_R_labelID,
+ * indexes 14 .. 15 = RESERVED (NULL)
+ * ZERO_labelID, ZERO_labelID,
+ */
+u32 abe_set_router_configuration(u32 id, u32 k, u32 *param)
+{
+ omap_abe_set_router_configuration(abe, id, k, param);
+ return 0;
+}
+EXPORT_SYMBOL(abe_set_router_configuration);
+
+/**
+ * abe_set_opp_processing - Set OPP mode for ABE Firmware
+ * @opp: OOPP mode
+ *
+ * New processing network and OPP:
+ * 0: Ultra Lowest power consumption audio player (no post-processing, no mixer)
+ * 1: OPP 25% (simple multimedia features, including low-power player)
+ * 2: OPP 50% (multimedia and voice calls)
+ * 3: OPP100% ( multimedia complex use-cases)
+ *
+ * Rearranges the FW task network to the corresponding OPP list of features.
+ * The corresponding AE ports are supposed to be set/reset accordingly before
+ * this switch.
+ *
+ */
+u32 abe_set_opp_processing(u32 opp)
+{
+ omap_abe_set_opp_processing(abe, opp);
+ return 0;
+}
+EXPORT_SYMBOL(abe_set_opp_processing);
+
+/**
+ * abe_disable_data_transfer
+ * @id: ABE port id
+ *
+ * disables the ATC descriptor and stop IO/port activities
+ * disable the IO task (@f = 0)
+ * clear ATC DMEM buffer, ATC enabled
+ */
+u32 abe_disable_data_transfer(u32 id)
+{
+ omap_abe_disable_data_transfer(abe, id);
+ return 0;
+}
+EXPORT_SYMBOL(abe_disable_data_transfer);
+
+/**
+ * abe_enable_data_transfer
+ * @ip: ABE port id
+ *
+ * enables the ATC descriptor
+ * reset ATC pointers
+ * enable the IO task (@f <> 0)
+ */
+u32 abe_enable_data_transfer(u32 id)
+{
+ omap_abe_enable_data_transfer(abe, id);
+ return 0;
+}
+EXPORT_SYMBOL(abe_enable_data_transfer);
+
+/**
+ * abe_connect_cbpr_dmareq_port
+ * @id: port name
+ * @f: desired data format
+ * @d: desired dma_request line (0..7)
+ * @a: returned pointer to the base address of the CBPr register and number of
+ * samples to exchange during a DMA_request.
+ *
+ * enables the data echange between a DMA and the ABE through the
+ * CBPr registers of AESS.
+ */
+u32 abe_connect_cbpr_dmareq_port(u32 id, abe_data_format_t *f, u32 d,
+ abe_dma_t *returned_dma_t)
+{
+ omap_abe_connect_cbpr_dmareq_port(abe, id, f, d, returned_dma_t);
+ return 0;
+}
+EXPORT_SYMBOL(abe_connect_cbpr_dmareq_port);
+
+/**
+ * abe_connect_irq_ping_pong_port
+ * @id: port name
+ * @f: desired data format
+ * @I: index of the call-back subroutine to call
+ * @s: half-buffer (ping) size
+ * @p: returned base address of the first (ping) buffer)
+ *
+ * enables the data echanges between a direct access to the DMEM
+ * memory of ABE using cache flush. On each IRQ activation a subroutine
+ * registered with "abe_plug_subroutine" will be called. This subroutine
+ * will generate an amount of samples, send them to DMEM memory and call
+ * "abe_set_ping_pong_buffer" to notify the new amount of samples in the
+ * pong buffer.
+ */
+u32 abe_connect_irq_ping_pong_port(u32 id, abe_data_format_t *f,
+ u32 subroutine_id, u32 size,
+ u32 *sink, u32 dsp_mcu_flag)
+{
+ omap_abe_connect_irq_ping_pong_port(abe, id, f, subroutine_id, size,
+ sink, dsp_mcu_flag);
+ return 0;
+}
+EXPORT_SYMBOL(abe_connect_irq_ping_pong_port);
+
+/**
+ * abe_connect_serial_port()
+ * @id: port name
+ * @f: data format
+ * @i: peripheral ID (McBSP #1, #2, #3)
+ *
+ * Operations : enables the data echanges between a McBSP and an ATC buffer in
+ * DMEM. This API is used connect 48kHz McBSP streams to MM_DL and 8/16kHz
+ * voice streams to VX_UL, VX_DL, BT_VX_UL, BT_VX_DL. It abstracts the
+ * abe_write_port API.
+ */
+u32 abe_connect_serial_port(u32 id, abe_data_format_t *f,
+ u32 mcbsp_id)
+{
+ omap_abe_connect_serial_port(abe, id, f, mcbsp_id);
+ return 0;
+}
+EXPORT_SYMBOL(abe_connect_serial_port);
+
+/**
+ * abe_read_port_address
+ * @dma: output pointer to the DMA iteration and data destination pointer
+ *
+ * This API returns the address of the DMA register used on this audio port.
+ * Depending on the protocol being used, adds the base address offset L3
+ * (DMA) or MPU (ARM)
+ */
+u32 abe_read_port_address(u32 port, abe_dma_t *dma2)
+{
+ omap_abe_read_port_address(abe, port, dma2);
+ return 0;
+}
+EXPORT_SYMBOL(abe_read_port_address);
+
+/**
+ * abe_check_activity - Check if some ABE activity.
+ *
+ * Check if any ABE ports are running.
+ * return 1: still activity on ABE
+ * return 0: no more activity on ABE. Event generator can be stopped
+ *
+ */
+u32 abe_check_activity(void)
+{
+ return (u32)omap_abe_check_activity(abe);
+}
+EXPORT_SYMBOL(abe_check_activity);
+/**
+ * abe_use_compensated_gain
+ * @on_off:
+ *
+ * Selects the automatic Mixer's gain management
+ * on_off = 1 allows the "abe_write_gain" to adjust the overall
+ * gains of the mixer to be tuned not to create saturation
+ */
+abehal_status abe_use_compensated_gain(u32 on_off)
+{
+ omap_abe_use_compensated_gain(abe, (int)(on_off));
+ return 0;
+}
+EXPORT_SYMBOL(abe_use_compensated_gain);
diff --git a/sound/soc/omap/abe/abe_main.h b/sound/soc/omap/abe/abe_main.h
new file mode 100644
index 0000000..e6f64d0
--- /dev/null
+++ b/sound/soc/omap/abe/abe_main.h
@@ -0,0 +1,662 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_MAIN_H_
+#define _ABE_MAIN_H_
+
+#include <linux/io.h>
+
+#include "abe_initxxx_labels.h"
+
+#define D_DEBUG_FIFO_ADDR 8160
+#define D_DEBUG_FIFO_ADDR_END 8255
+
+#define SUB_0_PARAM 0
+#define SUB_1_PARAM 1
+
+#define ABE_DEFAULT_BASE_ADDRESS_L3 0x49000000L
+#define ABE_DMEM_BASE_ADDRESS_MPU 0x49088000L
+#define ABE_DMEM_BASE_OFFSET_MPU 0x00080000L
+#define ABE_DMEM_BASE_ADDRESS_L3 ABE_DMEM_BASE_ADDRESS_MPU
+
+/*
+ * HARDWARE AND PERIPHERAL DEFINITIONS
+ */
+/* MM_DL */
+#define ABE_CBPR0_IDX 0
+/* VX_DL */
+#define ABE_CBPR1_IDX 1
+/* VX_UL */
+#define ABE_CBPR2_IDX 2
+/* MM_UL */
+#define ABE_CBPR3_IDX 3
+/* MM_UL2 */
+#define ABE_CBPR4_IDX 4
+/* TONES */
+#define ABE_CBPR5_IDX 5
+/* VIB */
+#define ABE_CBPR6_IDX 6
+/* DEBUG/CTL */
+#define ABE_CBPR7_IDX 7
+
+/*
+ * OPP TYPE
+ *
+ * 0: Ultra Lowest power consumption audio player
+ * 1: OPP 25% (simple multimedia features)
+ * 2: OPP 50% (multimedia and voice calls)
+ * 3: OPP100% (multimedia complex use-cases)
+ */
+#define ABE_OPP0 0
+#define ABE_OPP25 1
+#define ABE_OPP50 2
+#define ABE_OPP100 3
+/*
+ * SAMPLES TYPE
+ *
+ * mono 16 bit sample LSB aligned, 16 MSB bits are unused;
+ * mono right shifted to 16bits LSBs on a 32bits DMEM FIFO for McBSP
+ * TX purpose;
+ * mono sample MSB aligned (16/24/32bits);
+ * two successive mono samples in one 32bits container;
+ * Two L/R 16bits samples in a 32bits container;
+ * Two channels defined with two MSB aligned samples;
+ * Three channels defined with three MSB aligned samples (MIC);
+ * Four channels defined with four MSB aligned samples (MIC);
+ * . . .
+ * Eight channels defined with eight MSB aligned samples (MIC);
+ */
+#define MONO_MSB 1
+#define MONO_RSHIFTED_16 2
+#define STEREO_RSHIFTED_16 3
+#define STEREO_16_16 4
+#define STEREO_MSB 5
+#define THREE_MSB 6
+#define FOUR_MSB 7
+#define FIVE_MSB 8
+#define SIX_MSB 9
+#define SEVEN_MSB 10
+#define EIGHT_MSB 11
+#define NINE_MSB 12
+#define TEN_MSB 13
+/*
+ * PORT PROTOCOL TYPE - abe_port_protocol_switch_id
+ */
+#define SLIMBUS_PORT_PROT 1
+#define SERIAL_PORT_PROT 2
+#define TDM_SERIAL_PORT_PROT 3
+#define DMIC_PORT_PROT 4
+#define MCPDMDL_PORT_PROT 5
+#define MCPDMUL_PORT_PROT 6
+#define PINGPONG_PORT_PROT 7
+#define DMAREQ_PORT_PROT 8
+/*
+ * PORT IDs, this list is aligned with the FW data mapping
+ */
+#define DMIC_PORT 0
+#define PDM_UL_PORT 1
+#define BT_VX_UL_PORT 2
+#define MM_UL_PORT 3
+#define MM_UL2_PORT 4
+#define VX_UL_PORT 5
+#define MM_DL_PORT 6
+#define VX_DL_PORT 7
+#define TONES_DL_PORT 8
+#define VIB_DL_PORT 9
+#define BT_VX_DL_PORT 10
+#define PDM_DL_PORT 11
+#define MM_EXT_OUT_PORT 12
+#define MM_EXT_IN_PORT 13
+#define TDM_DL_PORT 14
+#define TDM_UL_PORT 15
+#define DEBUG_PORT 16
+#define LAST_PORT_ID 17
+/* definitions for the compatibility with HAL05xx */
+#define PDM_DL1_PORT 18
+#define PDM_DL2_PORT 19
+#define PDM_VIB_PORT 20
+/* There is only one DMIC port, always used with 6 samples
+ per 96kHz periods */
+#define DMIC_PORT1 DMIC_PORT
+#define DMIC_PORT2 DMIC_PORT
+#define DMIC_PORT3 DMIC_PORT
+/*
+ * Signal processing module names - EQ APS MIX ROUT
+ */
+/* equalizer downlink path headset + earphone */
+#define FEAT_EQ1 1
+/* equalizer downlink path integrated handsfree LEFT */
+#define FEAT_EQ2L (FEAT_EQ1+1)
+/* equalizer downlink path integrated handsfree RIGHT */
+#define FEAT_EQ2R (FEAT_EQ2L+1)
+/* equalizer downlink path side-tone */
+#define FEAT_EQSDT (FEAT_EQ2R+1)
+/* equalizer uplink path AMIC */
+#define FEAT_EQAMIC (FEAT_EQSDT+1)
+/* equalizer uplink path DMIC */
+#define FEAT_EQDMIC (FEAT_EQAMIC+1)
+/* Acoustic protection for headset */
+#define FEAT_APS1 (FEAT_EQDMIC+1)
+/* acoustic protection high-pass filter for handsfree "Left" */
+#define FEAT_APS2 (FEAT_APS1+1)
+/* acoustic protection high-pass filter for handsfree "Right" */
+#define FEAT_APS3 (FEAT_APS2+1)
+/* asynchronous sample-rate-converter for the downlink voice path */
+#define FEAT_ASRC1 (FEAT_APS3+1)
+/* asynchronous sample-rate-converter for the uplink voice path */
+#define FEAT_ASRC2 (FEAT_ASRC1+1)
+/* asynchronous sample-rate-converter for the multimedia player */
+#define FEAT_ASRC3 (FEAT_ASRC2+1)
+/* asynchronous sample-rate-converter for the echo reference */
+#define FEAT_ASRC4 (FEAT_ASRC3+1)
+/* mixer of the headset and earphone path */
+#define FEAT_MIXDL1 (FEAT_ASRC4+1)
+/* mixer of the hands-free path */
+#define FEAT_MIXDL2 (FEAT_MIXDL1+1)
+/* mixer for audio being sent on the voice_ul path */
+#define FEAT_MIXAUDUL (FEAT_MIXDL2+1)
+/* mixer for voice communication recording */
+#define FEAT_MIXVXREC (FEAT_MIXAUDUL+1)
+/* mixer for side-tone */
+#define FEAT_MIXSDT (FEAT_MIXVXREC+1)
+/* mixer for echo reference */
+#define FEAT_MIXECHO (FEAT_MIXSDT+1)
+/* router of the uplink path */
+#define FEAT_UPROUTE (FEAT_MIXECHO+1)
+/* all gains */
+#define FEAT_GAINS (FEAT_UPROUTE+1)
+#define FEAT_GAINS_DMIC1 (FEAT_GAINS+1)
+#define FEAT_GAINS_DMIC2 (FEAT_GAINS_DMIC1+1)
+#define FEAT_GAINS_DMIC3 (FEAT_GAINS_DMIC2+1)
+#define FEAT_GAINS_AMIC (FEAT_GAINS_DMIC3+1)
+#define FEAT_GAINS_SPLIT (FEAT_GAINS_AMIC+1)
+#define FEAT_GAINS_DL1 (FEAT_GAINS_SPLIT+1)
+#define FEAT_GAINS_DL2 (FEAT_GAINS_DL1+1)
+#define FEAT_GAIN_BTUL (FEAT_GAINS_DL2+1)
+/* sequencing queue of micro tasks */
+#define FEAT_SEQ (FEAT_GAIN_BTUL+1)
+/* Phoenix control queue through McPDM */
+#define FEAT_CTL (FEAT_SEQ+1)
+/* list of features of the firmware -------------------------------*/
+#define MAXNBFEATURE FEAT_CTL
+/* abe_equ_id */
+/* equalizer downlink path headset + earphone */
+#define EQ1 FEAT_EQ1
+/* equalizer downlink path integrated handsfree LEFT */
+#define EQ2L FEAT_EQ2L
+#define EQ2R FEAT_EQ2R
+/* equalizer downlink path side-tone */
+#define EQSDT FEAT_EQSDT
+#define EQAMIC FEAT_EQAMIC
+#define EQDMIC FEAT_EQDMIC
+/* abe_aps_id */
+/* Acoustic protection for headset */
+#define APS1 FEAT_APS1
+#define APS2L FEAT_APS2
+#define APS2R FEAT_APS3
+/* abe_asrc_id */
+/* asynchronous sample-rate-converter for the downlink voice path */
+#define ASRC1 FEAT_ASRC1
+/* asynchronous sample-rate-converter for the uplink voice path */
+#define ASRC2 FEAT_ASRC2
+/* asynchronous sample-rate-converter for the multimedia player */
+#define ASRC3 FEAT_ASRC3
+/* asynchronous sample-rate-converter for the voice uplink echo_reference */
+#define ASRC4 FEAT_ASRC4
+/* abe_mixer_id */
+#define MIXDL1 FEAT_MIXDL1
+#define MIXDL2 FEAT_MIXDL2
+#define MIXSDT FEAT_MIXSDT
+#define MIXECHO FEAT_MIXECHO
+#define MIXAUDUL FEAT_MIXAUDUL
+#define MIXVXREC FEAT_MIXVXREC
+/* abe_router_id */
+/* there is only one router up to now */
+#define UPROUTE FEAT_UPROUTE
+/*
+ * gain controls
+ */
+#define GAIN_LEFT_OFFSET 0
+#define GAIN_RIGHT_OFFSET 1
+/*
+ * GAIN IDs
+ */
+#define GAINS_DMIC1 FEAT_GAINS_DMIC1
+#define GAINS_DMIC2 FEAT_GAINS_DMIC2
+#define GAINS_DMIC3 FEAT_GAINS_DMIC3
+#define GAINS_AMIC FEAT_GAINS_AMIC
+#define GAINS_SPLIT FEAT_GAINS_SPLIT
+#define GAINS_DL1 FEAT_GAINS_DL1
+#define GAINS_DL2 FEAT_GAINS_DL2
+#define GAINS_BTUL FEAT_GAIN_BTUL
+/*
+ * ABE CONST AREA FOR PARAMETERS TRANSLATION
+ */
+#define sizeof_alpha_iir_table 61
+#define sizeof_beta_iir_table 61
+#define GAIN_MAXIMUM 3000L
+#define GAIN_24dB 2400L
+#define GAIN_18dB 1800L
+#define GAIN_12dB 1200L
+#define GAIN_6dB 600L
+/* default gain = 1 */
+#define GAIN_0dB 0L
+#define GAIN_M6dB -600L
+#define GAIN_M12dB -1200L
+#define GAIN_M18dB -1800L
+#define GAIN_M24dB -2400L
+#define GAIN_M30dB -3000L
+#define GAIN_M40dB -4000L
+#define GAIN_M50dB -5000L
+/* muted gain = -120 decibels */
+#define MUTE_GAIN -12000L
+#define GAIN_TOOLOW -13000L
+#define GAIN_MUTE MUTE_GAIN
+#define RAMP_MINLENGTH 3L
+/* ramp_t is in milli- seconds */
+#define RAMP_0MS 0L
+#define RAMP_1MS 1L
+#define RAMP_2MS 2L
+#define RAMP_5MS 5L
+#define RAMP_10MS 10L
+#define RAMP_20MS 20L
+#define RAMP_50MS 50L
+#define RAMP_100MS 100L
+#define RAMP_200MS 200L
+#define RAMP_500MS 500L
+#define RAMP_1000MS 1000L
+#define RAMP_MAXLENGTH 10000L
+/* for abe_translate_gain_format */
+#define LINABE_TO_DECIBELS 1
+#define DECIBELS_TO_LINABE 2
+/* for abe_translate_ramp_format */
+#define IIRABE_TO_MICROS 1
+#define MICROS_TO_IIABE 2
+/*
+ * EVENT GENERATORS - abe_event_id
+ */
+#define EVENT_TIMER 0
+#define EVENT_44100 1
+/*
+ * DMA requests
+ */
+/*Internal connection doesn't connect at ABE boundary */
+#define External_DMA_0 0
+/*Transmit request digital microphone */
+#define DMIC_DMA_REQ 1
+/*Multichannel PDM downlink */
+#define McPDM_DMA_DL 2
+/*Multichannel PDM uplink */
+#define McPDM_DMA_UP 3
+/*MCBSP module 1 - transmit request */
+#define MCBSP1_DMA_TX 4
+/*MCBSP module 1 - receive request */
+#define MCBSP1_DMA_RX 5
+/*MCBSP module 2 - transmit request */
+#define MCBSP2_DMA_TX 6
+/*MCBSP module 2 - receive request */
+#define MCBSP2_DMA_RX 7
+/*MCBSP module 3 - transmit request */
+#define MCBSP3_DMA_TX 8
+/*MCBSP module 3 - receive request */
+#define MCBSP3_DMA_RX 9
+/*
+ * SERIAL PORTS IDs - abe_mcbsp_id
+ */
+#define MCBSP1_TX MCBSP1_DMA_TX
+#define MCBSP1_RX MCBSP1_DMA_RX
+#define MCBSP2_TX MCBSP2_DMA_TX
+#define MCBSP2_RX MCBSP2_DMA_RX
+#define MCBSP3_TX MCBSP3_DMA_TX
+#define MCBSP3_RX MCBSP3_DMA_RX
+
+#define PING_PONG_WITH_MCU_IRQ 1
+#define PING_PONG_WITH_DSP_IRQ 2
+
+/*
+ Mixer ID Input port ID Comments
+ DL1_MIXER 0 MMDL path
+ 1 MMUL2 path
+ 2 VXDL path
+ 3 TONES path
+ SDT_MIXER 0 Uplink path
+ 1 Downlink path
+ ECHO_MIXER 0 DL1_MIXER path
+ 1 DL2_MIXER path
+ AUDUL_MIXER 0 TONES_DL path
+ 1 Uplink path
+ 2 MM_DL path
+ VXREC_MIXER 0 TONES_DL path
+ 1 VX_DL path
+ 2 MM_DL path
+ 3 VX_UL path
+*/
+#define MIX_VXUL_INPUT_MM_DL 0
+#define MIX_VXUL_INPUT_TONES 1
+#define MIX_VXUL_INPUT_VX_UL 2
+#define MIX_VXUL_INPUT_VX_DL 3
+#define MIX_DL1_INPUT_MM_DL 0
+#define MIX_DL1_INPUT_MM_UL2 1
+#define MIX_DL1_INPUT_VX_DL 2
+#define MIX_DL1_INPUT_TONES 3
+#define MIX_DL2_INPUT_MM_DL 0
+#define MIX_DL2_INPUT_MM_UL2 1
+#define MIX_DL2_INPUT_VX_DL 2
+#define MIX_DL2_INPUT_TONES 3
+#define MIX_SDT_INPUT_UP_MIXER 0
+#define MIX_SDT_INPUT_DL1_MIXER 1
+#define MIX_AUDUL_INPUT_MM_DL 0
+#define MIX_AUDUL_INPUT_TONES 1
+#define MIX_AUDUL_INPUT_UPLINK 2
+#define MIX_AUDUL_INPUT_VX_DL 3
+#define MIX_VXREC_INPUT_MM_DL 0
+#define MIX_VXREC_INPUT_TONES 1
+#define MIX_VXREC_INPUT_VX_UL 2
+#define MIX_VXREC_INPUT_VX_DL 3
+#define MIX_ECHO_DL1 0
+#define MIX_ECHO_DL2 1
+/* nb of samples to route */
+#define NBROUTE_UL 16
+/* 10 routing tables max */
+#define NBROUTE_CONFIG_MAX 10
+/* 5 pre-computed routing tables */
+#define NBROUTE_CONFIG 6
+/* AMIC on VX_UL */
+#define UPROUTE_CONFIG_AMIC 0
+/* DMIC first pair on VX_UL */
+#define UPROUTE_CONFIG_DMIC1 1
+/* DMIC second pair on VX_UL */
+#define UPROUTE_CONFIG_DMIC2 2
+/* DMIC last pair on VX_UL */
+#define UPROUTE_CONFIG_DMIC3 3
+/* BT_UL on VX_UL */
+#define UPROUTE_CONFIG_BT 4
+/* ECHO_REF on MM_UL2 */
+#define UPROUTE_ECHO_MMUL2 5
+
+/*
+ * DMA_T
+ *
+ * dma structure for easing programming
+ */
+typedef struct {
+ /* OCP L3 pointer to the first address of the */
+ void *data;
+ /* destination buffer (either DMA or Ping-Pong read/write pointers). */
+ /* address L3 when addressing the DMEM buffer instead of CBPr */
+ void *l3_dmem;
+ /* address L3 translated to L4 the ARM memory space */
+ void *l4_dmem;
+ /* number of iterations for the DMA data moves. */
+ u32 iter;
+} abe_dma_t;
+typedef u32 abe_dbg_t;
+/*
+ * ROUTER_T
+ *
+ * table of indexes in unsigned bytes
+ */
+typedef u16 abe_router_t;
+/*
+ * DATA_FORMAT_T
+ *
+ * used in port declaration
+ */
+typedef struct {
+ /* Sampling frequency of the stream */
+ u32 f;
+ /* Sample format type */
+ u32 samp_format;
+} abe_data_format_t;
+/*
+ * PORT_PROTOCOL_T
+ *
+ * port declaration
+ */
+typedef struct {
+ /* Direction=0 means input from AESS point of view */
+ u32 direction;
+ /* Protocol type (switch) during the data transfers */
+ u32 protocol_switch;
+ union {
+ /* Slimbus peripheral connected to ATC */
+ struct {
+ /* Address of ATC Slimbus descriptor's index */
+ u32 desc_addr1;
+ /* DMEM address 1 in bytes */
+ u32 buf_addr1;
+ /* DMEM buffer size size in bytes */
+ u32 buf_size;
+ /* ITERation on each DMAreq signals */
+ u32 iter;
+ /* Second ATC index for SlimBus reception (or NULL) */
+ u32 desc_addr2;
+ /* DMEM address 2 in bytes */
+ u32 buf_addr2;
+ } prot_slimbus;
+ /* McBSP/McASP peripheral connected to ATC */
+ struct {
+ u32 desc_addr;
+ /* Address of ATC McBSP/McASP descriptor's in bytes */
+ u32 buf_addr;
+ /* DMEM address in bytes */
+ u32 buf_size;
+ /* ITERation on each DMAreq signals */
+ u32 iter;
+ } prot_serial;
+ /* DMIC peripheral connected to ATC */
+ struct {
+ /* DMEM address in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size in bytes */
+ u32 buf_size;
+ /* Number of activated DMIC */
+ u32 nbchan;
+ } prot_dmic;
+ /* McPDMDL peripheral connected to ATC */
+ struct {
+ /* DMEM address in bytes */
+ u32 buf_addr;
+ /* DMEM size in bytes */
+ u32 buf_size;
+ /* Control allowed on McPDM DL */
+ u32 control;
+ } prot_mcpdmdl;
+ /* McPDMUL peripheral connected to ATC */
+ struct {
+ /* DMEM address size in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size size in bytes */
+ u32 buf_size;
+ } prot_mcpdmul;
+ /* Ping-Pong interface to the Host using cache-flush */
+ struct {
+ /* Address of ATC descriptor's */
+ u32 desc_addr;
+ /* DMEM buffer base address in bytes */
+ u32 buf_addr;
+ /* DMEM size in bytes for each ping and pong buffers */
+ u32 buf_size;
+ /* IRQ address (either DMA (0) MCU (1) or DSP(2)) */
+ u32 irq_addr;
+ /* IRQ data content loaded in the AESS IRQ register */
+ u32 irq_data;
+ /* Call-back function upon IRQ reception */
+ u32 callback;
+ } prot_pingpong;
+ /* DMAreq line to CBPr */
+ struct {
+ /* Address of ATC descriptor's */
+ u32 desc_addr;
+ /* DMEM buffer address in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size size in bytes */
+ u32 buf_size;
+ /* ITERation on each DMAreq signals */
+ u32 iter;
+ /* DMAreq address */
+ u32 dma_addr;
+ /* DMA/AESS = 1 << #DMA */
+ u32 dma_data;
+ } prot_dmareq;
+ /* Circular buffer - direct addressing to DMEM */
+ struct {
+ /* DMEM buffer base address in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size in bytes */
+ u32 buf_size;
+ /* DMAreq address */
+ u32 dma_addr;
+ /* DMA/AESS = 1 << #DMA */
+ u32 dma_data;
+ } prot_circular_buffer;
+ } p;
+} abe_port_protocol_t;
+
+/*
+ * EQU_T
+ *
+ * coefficients of the equalizer
+ */
+/* 24 Q6.26 coefficients */
+#define NBEQ1 25
+/* 2x12 Q6.26 coefficients */
+#define NBEQ2 13
+
+typedef struct {
+ /* type of filter */
+ u32 equ_type;
+ /* filter length */
+ u32 equ_length;
+ union {
+ /* parameters are the direct and recursive coefficients in */
+ /* Q6.26 integer fixed-point format. */
+ s32 type1[NBEQ1];
+ struct {
+ /* center frequency of the band [Hz] */
+ s32 freq[NBEQ2];
+ /* gain of each band. [dB] */
+ s32 gain[NBEQ2];
+ /* Q factor of this band [dB] */
+ s32 q[NBEQ2];
+ } type2;
+ } coef;
+ s32 equ_param3;
+} abe_equ_t;
+
+
+/* subroutine with no parameter */
+typedef void (*abe_subroutine0) (void);
+/* subroutine with one parameter */
+typedef void (*abe_subroutine1) (u32);
+typedef void (*abe_subroutine2) (u32, u32);
+typedef void (*abe_subroutine3) (u32, u32, u32);
+typedef void (*abe_subroutine4) (u32, u32, u32, u32);
+
+
+extern u32 abe_irq_pingpong_player_id;
+
+
+void abe_init_mem(void __iomem **_io_base);
+u32 abe_reset_hal(void);
+u32 abe_load_fw(void);
+u32 abe_reload_fw(void);
+u32 abe_wakeup(void);
+u32 abe_irq_processing(void);
+u32 abe_clear_irq(void);
+u32 abe_disable_irq(void);
+u32 abe_write_event_generator(u32 e);
+u32 abe_stop_event_generator(void);
+u32 abe_connect_debug_trace(abe_dma_t *dma2);
+u32 abe_set_debug_trace(abe_dbg_t debug);
+u32 abe_set_ping_pong_buffer(u32 port, u32 n_bytes);
+u32 abe_read_next_ping_pong_buffer(u32 port, u32 *p, u32 *n);
+u32 abe_init_ping_pong_buffer(u32 id, u32 size_bytes, u32 n_buffers,
+ u32 *p);
+u32 abe_read_offset_from_ping_buffer(u32 id, u32 *n);
+u32 abe_write_equalizer(u32 id, abe_equ_t *param);
+u32 abe_disable_gain(u32 id, u32 p);
+u32 abe_enable_gain(u32 id, u32 p);
+u32 abe_mute_gain(u32 id, u32 p);
+u32 abe_unmute_gain(u32 id, u32 p);
+u32 abe_write_gain(u32 id, s32 f_g, u32 ramp, u32 p);
+u32 abe_write_mixer(u32 id, s32 f_g, u32 f_ramp, u32 p);
+u32 abe_read_gain(u32 id, u32 *f_g, u32 p);
+u32 abe_read_mixer(u32 id, u32 *f_g, u32 p);
+u32 abe_set_router_configuration(u32 id, u32 k, u32 *param);
+u32 abe_set_opp_processing(u32 opp);
+u32 abe_disable_data_transfer(u32 id);
+u32 abe_enable_data_transfer(u32 id);
+u32 abe_connect_cbpr_dmareq_port(u32 id, abe_data_format_t *f, u32 d,
+ abe_dma_t *returned_dma_t);
+u32 abe_connect_irq_ping_pong_port(u32 id, abe_data_format_t *f,
+ u32 subroutine_id, u32 size,
+ u32 *sink, u32 dsp_mcu_flag);
+u32 abe_connect_serial_port(u32 id, abe_data_format_t *f,
+ u32 mcbsp_id);
+u32 abe_read_port_address(u32 port, abe_dma_t *dma2);
+void abe_add_subroutine(u32 *id, abe_subroutine2 f, u32 nparam, u32 *params);
+u32 abe_read_next_ping_pong_buffer(u32 port, u32 *p, u32 *n);
+u32 abe_check_activity(void);
+void abe_add_subroutine(u32 *id, abe_subroutine2 f,
+ u32 nparam, u32 *params);
+
+u32 abe_plug_subroutine(u32 *id, abe_subroutine2 f, u32 n,
+ u32 *params);
+
+#endif /* _ABE_MAIN_H_ */
diff --git a/sound/soc/omap/abe/abe_mem.h b/sound/soc/omap/abe/abe_mem.h
new file mode 100644
index 0000000..683968e
--- /dev/null
+++ b/sound/soc/omap/abe/abe_mem.h
@@ -0,0 +1,99 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_MEM_H_
+#define _ABE_MEM_H_
+
+#define OMAP_ABE_DMEM 0
+#define OMAP_ABE_CMEM 1
+#define OMAP_ABE_SMEM 2
+#define OMAP_ABE_PMEM 3
+#define OMAP_ABE_AESS 4
+
+/* Distinction between Read and Write from/to ABE memory
+ * is useful for simulation tool */
+static inline void omap_abe_mem_write(struct omap_abe *abe, int bank,
+ u32 offset, u32 *src, size_t bytes)
+{
+ memcpy((abe->io_base[bank] + offset), src, bytes);
+}
+
+static inline void omap_abe_mem_read(struct omap_abe *abe, int bank,
+ u32 offset, u32 *dest, size_t bytes)
+{
+ memcpy(dest, (abe->io_base[bank] + offset), bytes);
+}
+
+static inline u32 omap_abe_reg_readl(struct omap_abe *abe, u32 offset)
+{
+ return __raw_readl(abe->io_base[OMAP_ABE_AESS] + offset);
+}
+
+static inline void omap_abe_reg_writel(struct omap_abe *abe,
+ u32 offset, u32 val)
+{
+ __raw_writel(val, (abe->io_base[OMAP_ABE_AESS] + offset));
+}
+
+static inline void *omap_abe_reset_mem(struct omap_abe *abe, int bank,
+ u32 offset, size_t bytes)
+{
+ return memset(abe->io_base[bank] + offset, 0, bytes);
+}
+
+#endif /*_ABE_MEM_H_*/
diff --git a/sound/soc/omap/abe/abe_port.c b/sound/soc/omap/abe/abe_port.c
new file mode 100644
index 0000000..0cb0b67
--- /dev/null
+++ b/sound/soc/omap/abe/abe_port.c
@@ -0,0 +1,1580 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include "abe_legacy.h"
+#include "abe_port.h"
+#include "abe_dbg.h"
+#include "abe_mem.h"
+#include "abe_gain.h"
+
+/**
+ * abe_clean_temporay buffers
+ *
+ * clear temporary buffers
+ */
+void omap_abe_clean_temporary_buffers(struct omap_abe *abe, u32 id)
+{
+ switch (id) {
+ case OMAP_ABE_DMIC_PORT:
+ omap_abe_reset_mem(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_DMIC_UL_FIFO_ADDR,
+ OMAP_ABE_D_DMIC_UL_FIFO_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_DMIC0_96_48_DATA_ADDR,
+ OMAP_ABE_S_DMIC0_96_48_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_DMIC1_96_48_DATA_ADDR,
+ OMAP_ABE_S_DMIC1_96_48_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_DMIC2_96_48_DATA_ADDR,
+ OMAP_ABE_S_DMIC2_96_48_DATA_SIZE);
+ /* reset working values of the gain, target gain is preserved */
+ omap_abe_reset_gain_mixer(abe, GAINS_DMIC1, GAIN_LEFT_OFFSET);
+ omap_abe_reset_gain_mixer(abe, GAINS_DMIC1, GAIN_RIGHT_OFFSET);
+ omap_abe_reset_gain_mixer(abe, GAINS_DMIC2, GAIN_LEFT_OFFSET);
+ omap_abe_reset_gain_mixer(abe, GAINS_DMIC2, GAIN_RIGHT_OFFSET);
+ omap_abe_reset_gain_mixer(abe, GAINS_DMIC3, GAIN_LEFT_OFFSET);
+ omap_abe_reset_gain_mixer(abe, GAINS_DMIC3, GAIN_RIGHT_OFFSET);
+ break;
+ case OMAP_ABE_PDM_UL_PORT:
+ omap_abe_reset_mem(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_MCPDM_UL_FIFO_ADDR,
+ OMAP_ABE_D_MCPDM_UL_FIFO_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_AMIC_96_48_DATA_ADDR,
+ OMAP_ABE_S_AMIC_96_48_DATA_SIZE);
+ /* reset working values of the gain, target gain is preserved */
+ omap_abe_reset_gain_mixer(abe, GAINS_AMIC, GAIN_LEFT_OFFSET);
+ omap_abe_reset_gain_mixer(abe, GAINS_AMIC, GAIN_RIGHT_OFFSET);
+ break;
+ case OMAP_ABE_BT_VX_UL_PORT:
+ omap_abe_reset_mem(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_BT_UL_FIFO_ADDR,
+ OMAP_ABE_D_BT_UL_FIFO_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_BT_UL_ADDR,
+ OMAP_ABE_S_BT_UL_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_BT_UL_8_48_HP_DATA_ADDR,
+ OMAP_ABE_S_BT_UL_8_48_HP_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_BT_UL_8_48_LP_DATA_ADDR,
+ OMAP_ABE_S_BT_UL_8_48_LP_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_BT_UL_16_48_HP_DATA_ADDR,
+ OMAP_ABE_S_BT_UL_16_48_HP_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_BT_UL_16_48_LP_DATA_ADDR,
+ OMAP_ABE_S_BT_UL_16_48_LP_DATA_SIZE);
+ /* reset working values of the gain, target gain is preserved */
+ omap_abe_reset_gain_mixer(abe, GAINS_BTUL, GAIN_LEFT_OFFSET);
+ omap_abe_reset_gain_mixer(abe, GAINS_BTUL, GAIN_RIGHT_OFFSET);
+ break;
+ case OMAP_ABE_MM_UL_PORT:
+ omap_abe_reset_mem(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_MM_UL_FIFO_ADDR,
+ OMAP_ABE_D_MM_UL_FIFO_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_MM_UL_ADDR,
+ OMAP_ABE_S_MM_UL_SIZE);
+ break;
+ case OMAP_ABE_MM_UL2_PORT:
+ omap_abe_reset_mem(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_MM_UL2_FIFO_ADDR,
+ OMAP_ABE_D_MM_UL2_FIFO_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_MM_UL2_ADDR,
+ OMAP_ABE_S_MM_UL2_SIZE);
+ break;
+ case OMAP_ABE_VX_UL_PORT:
+ omap_abe_reset_mem(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_VX_UL_FIFO_ADDR,
+ OMAP_ABE_D_VX_UL_FIFO_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_VX_UL_ADDR,
+ OMAP_ABE_S_VX_UL_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_VX_UL_48_8_HP_DATA_ADDR,
+ OMAP_ABE_S_VX_UL_48_8_HP_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_VX_UL_48_8_LP_DATA_ADDR,
+ OMAP_ABE_S_VX_UL_48_8_LP_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_VX_UL_48_16_HP_DATA_ADDR,
+ OMAP_ABE_S_VX_UL_48_16_HP_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_VX_UL_48_16_LP_DATA_ADDR,
+ OMAP_ABE_S_VX_UL_48_16_LP_DATA_SIZE);
+ omap_abe_reset_gain_mixer(abe, MIXAUDUL, MIX_AUDUL_INPUT_UPLINK);
+ break;
+ case OMAP_ABE_MM_DL_PORT:
+ omap_abe_reset_mem(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_MM_DL_FIFO_ADDR,
+ OMAP_ABE_D_MM_DL_FIFO_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_MM_DL_ADDR,
+ OMAP_ABE_S_MM_DL_SIZE);
+ omap_abe_reset_gain_mixer(abe, MIXDL1, MIX_DL1_INPUT_MM_DL);
+ omap_abe_reset_gain_mixer(abe, MIXDL2, MIX_DL2_INPUT_MM_DL);
+ break;
+ case OMAP_ABE_VX_DL_PORT:
+ omap_abe_reset_mem(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_VX_DL_FIFO_ADDR,
+ OMAP_ABE_D_VX_DL_FIFO_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_VX_DL_ADDR,
+ OMAP_ABE_S_VX_DL_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_VX_DL_8_48_HP_DATA_ADDR,
+ OMAP_ABE_S_VX_DL_8_48_HP_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_VX_DL_8_48_LP_DATA_ADDR,
+ OMAP_ABE_S_VX_DL_8_48_LP_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_VX_DL_16_48_HP_DATA_ADDR,
+ OMAP_ABE_S_VX_DL_16_48_HP_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_VX_DL_16_48_LP_DATA_ADDR,
+ OMAP_ABE_S_VX_DL_16_48_LP_DATA_SIZE);
+ omap_abe_reset_gain_mixer(abe, MIXDL1, MIX_DL1_INPUT_VX_DL);
+ omap_abe_reset_gain_mixer(abe, MIXDL2, MIX_DL2_INPUT_VX_DL);
+ break;
+ case OMAP_ABE_TONES_DL_PORT:
+ omap_abe_reset_mem(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_TONES_DL_FIFO_ADDR,
+ OMAP_ABE_D_TONES_DL_FIFO_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_TONES_ADDR,
+ OMAP_ABE_S_TONES_SIZE);
+ omap_abe_reset_gain_mixer(abe, MIXDL1, MIX_DL1_INPUT_TONES);
+ omap_abe_reset_gain_mixer(abe, MIXDL2, MIX_DL2_INPUT_TONES);
+ break;
+ case OMAP_ABE_VIB_DL_PORT:
+ omap_abe_reset_mem(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_VIB_DL_FIFO_ADDR,
+ OMAP_ABE_D_VIB_DL_FIFO_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_VIBRA_ADDR,
+ OMAP_ABE_S_VIBRA_SIZE);
+ break;
+ case OMAP_ABE_BT_VX_DL_PORT:
+ omap_abe_reset_mem(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_BT_DL_FIFO_ADDR,
+ OMAP_ABE_D_BT_DL_FIFO_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_BT_DL_ADDR,
+ OMAP_ABE_S_BT_DL_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_BT_DL_48_8_HP_DATA_ADDR,
+ OMAP_ABE_S_BT_DL_48_8_HP_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_BT_DL_48_8_LP_DATA_ADDR,
+ OMAP_ABE_S_BT_DL_48_8_LP_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_BT_DL_48_16_HP_DATA_ADDR,
+ OMAP_ABE_S_BT_DL_48_16_HP_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_BT_DL_48_16_LP_DATA_ADDR,
+ OMAP_ABE_S_BT_DL_48_16_LP_DATA_SIZE);
+ break;
+ case OMAP_ABE_PDM_DL_PORT:
+ omap_abe_reset_mem(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_MCPDM_DL_FIFO_ADDR,
+ OMAP_ABE_D_MCPDM_DL_FIFO_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_DL2_M_LR_EQ_DATA_ADDR,
+ OMAP_ABE_S_DL2_M_LR_EQ_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_DL1_M_EQ_DATA_ADDR,
+ OMAP_ABE_S_DL1_M_EQ_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_EARP_48_96_LP_DATA_ADDR,
+ OMAP_ABE_S_EARP_48_96_LP_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_IHF_48_96_LP_DATA_ADDR,
+ OMAP_ABE_S_IHF_48_96_LP_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_APS_DL1_EQ_DATA_ADDR,
+ OMAP_ABE_S_APS_DL1_EQ_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_APS_DL2_EQ_DATA_ADDR,
+ OMAP_ABE_S_APS_DL2_EQ_DATA_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_APS_DL2_L_IIRMEM1_ADDR,
+ OMAP_ABE_S_APS_DL2_L_IIRMEM1_SIZE);
+ omap_abe_reset_mem(abe, OMAP_ABE_SMEM,
+ OMAP_ABE_S_APS_DL2_R_IIRMEM1_ADDR,
+ OMAP_ABE_S_APS_DL2_R_IIRMEM1_SIZE);
+ omap_abe_reset_gain_mixer(abe, GAINS_DL1, GAIN_LEFT_OFFSET);
+ omap_abe_reset_gain_mixer(abe, GAINS_DL1, GAIN_RIGHT_OFFSET);
+ omap_abe_reset_gain_mixer(abe, GAINS_DL2, GAIN_LEFT_OFFSET);
+ omap_abe_reset_gain_mixer(abe, GAINS_DL2, GAIN_RIGHT_OFFSET);
+ omap_abe_reset_gain_mixer(abe, MIXSDT, MIX_SDT_INPUT_UP_MIXER);
+ omap_abe_reset_gain_mixer(abe, MIXSDT, MIX_SDT_INPUT_DL1_MIXER);
+ break;
+ case OMAP_ABE_MM_EXT_OUT_PORT:
+ omap_abe_reset_mem(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_MM_EXT_OUT_FIFO_ADDR,
+ OMAP_ABE_D_MM_EXT_OUT_FIFO_SIZE);
+ break;
+ case OMAP_ABE_MM_EXT_IN_PORT:
+ omap_abe_reset_mem(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_MM_EXT_IN_FIFO_ADDR,
+ OMAP_ABE_D_MM_EXT_IN_FIFO_SIZE);
+ break;
+ }
+}
+
+/**
+ * omap_abe_disable_enable_dma_request
+ * Parameter:
+ * Operations:
+ * Return value:
+ */
+void omap_abe_disable_enable_dma_request(struct omap_abe *abe, u32 id,
+ u32 on_off)
+{
+ u8 desc_third_word[4], irq_dmareq_field;
+ u32 sio_desc_address;
+ u32 struct_offset;
+ struct ABE_SIODescriptor sio_desc;
+ struct ABE_SPingPongDescriptor desc_pp;
+
+ if (abe_port[id].protocol.protocol_switch == PINGPONG_PORT_PROT) {
+ irq_dmareq_field =
+ (u8) (on_off *
+ abe_port[id].protocol.p.prot_pingpong.irq_data);
+ sio_desc_address = OMAP_ABE_D_PINGPONGDESC_ADDR;
+ struct_offset = (u32) &(desc_pp.data_size) - (u32) &(desc_pp);
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM,
+ sio_desc_address + struct_offset,
+ (u32 *) desc_third_word, 4);
+ desc_third_word[2] = irq_dmareq_field;
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ sio_desc_address + struct_offset,
+ (u32 *) desc_third_word, 4);
+ } else {
+ /* serial interface: sync ATC with Firmware activity */
+ sio_desc_address =
+ OMAP_ABE_D_IODESCR_ADDR +
+ (id * sizeof(struct ABE_SIODescriptor));
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM,
+ sio_desc_address, (u32 *) &sio_desc,
+ sizeof(sio_desc));
+ if (on_off) {
+ sio_desc.atc_irq_data =
+ (u8) abe_port[id].protocol.p.prot_dmareq.
+ dma_data;
+ sio_desc.on_off = 0x80;
+ } else {
+ sio_desc.atc_irq_data = 0;
+ sio_desc.on_off = 0;
+ }
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ sio_desc_address, (u32 *) &sio_desc,
+ sizeof(sio_desc));
+ }
+
+}
+
+/**
+ * omap_abe_enable_dma_request
+ *
+ * Parameter:
+ * Operations:
+ * Return value:
+ *
+ */
+void omap_abe_enable_dma_request(struct omap_abe *abe, u32 id)
+{
+ omap_abe_disable_enable_dma_request(abe, id, 1);
+}
+
+/**
+ * omap_abe_disable_dma_request
+ *
+ * Parameter:
+ * Operations:
+ * Return value:
+ *
+ */
+void omap_abe_disable_dma_request(struct omap_abe *abe, u32 id)
+{
+ omap_abe_disable_enable_dma_request(abe, id, 0);
+}
+
+/**
+ * abe_init_atc
+ * @id: ABE port ID
+ *
+ * load the DMEM ATC/AESS descriptors
+ */
+void omap_abe_init_atc(struct omap_abe *abe, u32 id)
+{
+ u8 iter;
+ s32 datasize;
+ struct omap_abe_atc_desc atc_desc;
+
+#define JITTER_MARGIN 4
+ /* load default values of the descriptor */
+ atc_desc.rdpt = 0;
+ atc_desc.wrpt = 0;
+ atc_desc.irqdest = 0;
+ atc_desc.cberr = 0;
+ atc_desc.desen = 0;
+ atc_desc.nw = 0;
+ atc_desc.reserved0 = 0;
+ atc_desc.reserved1 = 0;
+ atc_desc.reserved2 = 0;
+ atc_desc.srcid = 0;
+ atc_desc.destid = 0;
+ atc_desc.badd = 0;
+ atc_desc.iter = 0;
+ atc_desc.cbsize = 0;
+ datasize = abe_dma_port_iter_factor(&((abe_port[id]).format));
+ iter = (u8) abe_dma_port_iteration(&((abe_port[id]).format));
+ /* if the ATC FIFO is too small there will be two ABE firmware
+ utasks to do the copy this happems on DMIC and MCPDMDL */
+ /* VXDL_8kMono = 4 = 2 + 2x1 */
+ /* VXDL_16kstereo = 12 = 8 + 2x2 */
+ /* MM_DL_1616 = 14 = 12 + 2x1 */
+ /* DMIC = 84 = 72 + 2x6 */
+ /* VXUL_8kMono = 2 */
+ /* VXUL_16kstereo = 4 */
+ /* MM_UL2_Stereo = 4 */
+ /* PDMDL = 12 */
+ /* IN from AESS point of view */
+ if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN)
+ if (iter + 2 * datasize > 126)
+ atc_desc.wrpt = (iter >> 1) +
+ ((JITTER_MARGIN-1) * datasize);
+ else
+ atc_desc.wrpt = iter + ((JITTER_MARGIN-1) * datasize);
+ else
+ atc_desc.wrpt = 0 + ((JITTER_MARGIN+1) * datasize);
+ switch ((abe_port[id]).protocol.protocol_switch) {
+ case SLIMBUS_PORT_PROT:
+ atc_desc.cbdir = (abe_port[id]).protocol.direction;
+ atc_desc.cbsize =
+ (abe_port[id]).protocol.p.prot_slimbus.buf_size;
+ atc_desc.badd =
+ ((abe_port[id]).protocol.p.prot_slimbus.buf_addr1) >> 4;
+ atc_desc.iter = (abe_port[id]).protocol.p.prot_slimbus.iter;
+ atc_desc.srcid =
+ abe_atc_srcid[(abe_port[id]).protocol.p.prot_slimbus.
+ desc_addr1 >> 3];
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ (abe_port[id]).protocol.p.prot_slimbus.
+ desc_addr1, (u32 *) &atc_desc, sizeof(atc_desc));
+ atc_desc.badd =
+ (abe_port[id]).protocol.p.prot_slimbus.buf_addr2;
+ atc_desc.srcid =
+ abe_atc_srcid[(abe_port[id]).protocol.p.prot_slimbus.
+ desc_addr2 >> 3];
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ (abe_port[id]).protocol.p.prot_slimbus.
+ desc_addr2, (u32 *) &atc_desc, sizeof(atc_desc));
+ break;
+ case SERIAL_PORT_PROT:
+ atc_desc.cbdir = (abe_port[id]).protocol.direction;
+ atc_desc.cbsize =
+ (abe_port[id]).protocol.p.prot_serial.buf_size;
+ atc_desc.badd =
+ ((abe_port[id]).protocol.p.prot_serial.buf_addr) >> 4;
+ atc_desc.iter = (abe_port[id]).protocol.p.prot_serial.iter;
+ atc_desc.srcid =
+ abe_atc_srcid[(abe_port[id]).protocol.p.prot_serial.
+ desc_addr >> 3];
+ atc_desc.destid =
+ abe_atc_dstid[(abe_port[id]).protocol.p.prot_serial.
+ desc_addr >> 3];
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ (abe_port[id]).protocol.p.prot_serial.desc_addr,
+ (u32 *) &atc_desc, sizeof(atc_desc));
+ break;
+ case DMIC_PORT_PROT:
+ atc_desc.cbdir = ABE_ATC_DIRECTION_IN;
+ atc_desc.cbsize = (abe_port[id]).protocol.p.prot_dmic.buf_size;
+ atc_desc.badd =
+ ((abe_port[id]).protocol.p.prot_dmic.buf_addr) >> 4;
+ atc_desc.iter = DMIC_ITER;
+ atc_desc.srcid = abe_atc_srcid[ABE_ATC_DMIC_DMA_REQ];
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ (ABE_ATC_DMIC_DMA_REQ*ATC_SIZE),
+ (u32 *) &atc_desc, sizeof(atc_desc));
+ break;
+ case MCPDMDL_PORT_PROT:
+ atc_desc.cbdir = ABE_ATC_DIRECTION_OUT;
+ atc_desc.cbsize =
+ (abe_port[id]).protocol.p.prot_mcpdmdl.buf_size;
+ atc_desc.badd =
+ ((abe_port[id]).protocol.p.prot_mcpdmdl.buf_addr) >> 4;
+ atc_desc.iter = MCPDM_DL_ITER;
+ atc_desc.destid = abe_atc_dstid[ABE_ATC_MCPDMDL_DMA_REQ];
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ (ABE_ATC_MCPDMDL_DMA_REQ*ATC_SIZE),
+ (u32 *) &atc_desc, sizeof(atc_desc));
+ break;
+ case MCPDMUL_PORT_PROT:
+ atc_desc.cbdir = ABE_ATC_DIRECTION_IN;
+ atc_desc.cbsize =
+ (abe_port[id]).protocol.p.prot_mcpdmul.buf_size;
+ atc_desc.badd =
+ ((abe_port[id]).protocol.p.prot_mcpdmul.buf_addr) >> 4;
+ atc_desc.iter = MCPDM_UL_ITER;
+ atc_desc.srcid = abe_atc_srcid[ABE_ATC_MCPDMUL_DMA_REQ];
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ (ABE_ATC_MCPDMUL_DMA_REQ*ATC_SIZE),
+ (u32 *) &atc_desc, sizeof(atc_desc));
+ break;
+ case PINGPONG_PORT_PROT:
+ /* software protocol, nothing to do on ATC */
+ break;
+ case DMAREQ_PORT_PROT:
+ atc_desc.cbdir = (abe_port[id]).protocol.direction;
+ atc_desc.cbsize =
+ (abe_port[id]).protocol.p.prot_dmareq.buf_size;
+ atc_desc.badd =
+ ((abe_port[id]).protocol.p.prot_dmareq.buf_addr) >> 4;
+ /* CBPr needs ITER=1.
+ It is the job of eDMA to do the iterations */
+ atc_desc.iter = 1;
+ /* input from ABE point of view */
+ if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN) {
+ /* atc_atc_desc.rdpt = 127; */
+ /* atc_atc_desc.wrpt = 0; */
+ atc_desc.srcid = abe_atc_srcid
+ [(abe_port[id]).protocol.p.prot_dmareq.
+ desc_addr >> 3];
+ } else {
+ /* atc_atc_desc.rdpt = 0; */
+ /* atc_atc_desc.wrpt = 127; */
+ atc_desc.destid = abe_atc_dstid
+ [(abe_port[id]).protocol.p.prot_dmareq.
+ desc_addr >> 3];
+ }
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ (abe_port[id]).protocol.p.prot_dmareq.desc_addr,
+ (u32 *) &atc_desc, sizeof(atc_desc));
+ break;
+ }
+}
+
+/**
+ * omap_abe_enable_pp_io_task
+ * @id: port_id
+ *
+ *
+ */
+void omap_abe_enable_pp_io_task(struct omap_abe *abe, u32 id)
+{
+ if (OMAP_ABE_MM_DL_PORT == id) {
+ /* MM_DL managed in ping-pong */
+ abe->MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] =
+ ABE_TASK_ID(C_ABE_FW_TASK_IO_PING_PONG);
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_MULTIFRAME_ADDR, (u32 *) abe->MultiFrame,
+ sizeof(abe->MultiFrame));
+ } else {
+ /* ping_pong is only supported on MM_DL */
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_API,
+ ABE_PARAMETER_ERROR);
+ }
+}
+/**
+ * omap_abe_disable_pp_io_task
+ * @id: port_id
+ *
+ *
+ */
+void omap_abe_disable_pp_io_task(struct omap_abe *abe, u32 id)
+{
+ if (OMAP_ABE_MM_DL_PORT == id) {
+ /* MM_DL managed in ping-pong */
+ abe->MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] = 0;
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_MULTIFRAME_ADDR, (u32 *) abe->MultiFrame,
+ sizeof(abe->MultiFrame));
+ } else {
+ /* ping_pong is only supported on MM_DL */
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_API,
+ ABE_PARAMETER_ERROR);
+ }
+}
+
+/**
+ * omap_abe_disable_data_transfer
+ * @id: ABE port id
+ *
+ * disables the ATC descriptor and stop IO/port activities
+ * disable the IO task (@f = 0)
+ * clear ATC DMEM buffer, ATC enabled
+ */
+int omap_abe_disable_data_transfer(struct omap_abe *abe, u32 id)
+{
+
+ _log(ABE_ID_DISABLE_DATA_TRANSFER, id, 0, 0);
+
+ /* MM_DL managed in ping-pong */
+ if (id == OMAP_ABE_MM_DL_PORT) {
+ if (abe_port[OMAP_ABE_MM_DL_PORT].protocol.protocol_switch == PINGPONG_PORT_PROT)
+ omap_abe_disable_pp_io_task(abe, OMAP_ABE_MM_DL_PORT);
+ }
+ /* local host variable status= "port is running" */
+ abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_IDLE;
+ /* disable DMA requests */
+ omap_abe_disable_dma_request(abe, id);
+ /* disable ATC transfers */
+ omap_abe_init_atc(abe, id);
+ omap_abe_clean_temporary_buffers(abe, id);
+ /* select the main port based on the desactivation of this port */
+ abe_decide_main_port();
+
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_disable_data_transfer);
+
+/**
+ * omap_abe_enable_data_transfer
+ * @ip: ABE port id
+ *
+ * enables the ATC descriptor
+ * reset ATC pointers
+ * enable the IO task (@f <> 0)
+ */
+int omap_abe_enable_data_transfer(struct omap_abe *abe, u32 id)
+{
+ abe_port_protocol_t *protocol;
+ abe_data_format_t format;
+
+ _log(ABE_ID_ENABLE_DATA_TRANSFER, id, 0, 0);
+ omap_abe_clean_temporary_buffers(abe, id);
+ if (id == OMAP_ABE_PDM_UL_PORT) {
+ /* initializes the ABE ATC descriptors in DMEM - MCPDM_UL */
+ protocol = &(abe_port[OMAP_ABE_PDM_UL_PORT].protocol);
+ format = abe_port[OMAP_ABE_PDM_UL_PORT].format;
+ omap_abe_init_atc(abe, OMAP_ABE_PDM_UL_PORT);
+ abe_init_io_tasks(OMAP_ABE_PDM_UL_PORT, &format, protocol);
+ }
+ if (id == OMAP_ABE_PDM_DL_PORT) {
+ /* initializes the ABE ATC descriptors in DMEM - MCPDM_DL */
+ protocol = &(abe_port[OMAP_ABE_PDM_DL_PORT].protocol);
+ format = abe_port[OMAP_ABE_PDM_DL_PORT].format;
+ omap_abe_init_atc(abe, OMAP_ABE_PDM_DL_PORT);
+ abe_init_io_tasks(OMAP_ABE_PDM_DL_PORT, &format, protocol);
+ }
+ /* MM_DL managed in ping-pong */
+ if (id == OMAP_ABE_MM_DL_PORT) {
+ protocol = &(abe_port[OMAP_ABE_MM_DL_PORT].protocol);
+ if (protocol->protocol_switch == PINGPONG_PORT_PROT)
+ omap_abe_enable_pp_io_task(abe, OMAP_ABE_MM_DL_PORT);
+ }
+ if (id == OMAP_ABE_DMIC_PORT) {
+ /* one DMIC port enabled = all DMICs enabled,
+ * since there is a single DMIC path for all DMICs */
+ protocol = &(abe_port[OMAP_ABE_DMIC_PORT].protocol);
+ format = abe_port[OMAP_ABE_DMIC_PORT].format;
+ omap_abe_init_atc(abe, OMAP_ABE_DMIC_PORT);
+ abe_init_io_tasks(OMAP_ABE_DMIC_PORT, &format, protocol);
+ }
+ if (id == OMAP_ABE_VX_UL_PORT) {
+ /* Init VX_UL ASRC and enable its adaptation */
+ abe_init_asrc_vx_ul(250);
+ }
+ if (id == OMAP_ABE_VX_DL_PORT) {
+ /* Init VX_DL ASRC and enable its adaptation */
+ abe_init_asrc_vx_dl(250);
+ }
+ /* local host variable status= "port is running" */
+ abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING;
+ /* enable DMA requests */
+ omap_abe_enable_dma_request(abe, id);
+ /* select the main port based on the activation of this new port */
+ abe_decide_main_port();
+
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_enable_data_transfer);
+
+/**
+ * omap_abe_connect_cbpr_dmareq_port
+ * @id: port name
+ * @f: desired data format
+ * @d: desired dma_request line (0..7)
+ * @a: returned pointer to the base address of the CBPr register and number of
+ * samples to exchange during a DMA_request.
+ *
+ * enables the data echange between a DMA and the ABE through the
+ * CBPr registers of AESS.
+ */
+int omap_abe_connect_cbpr_dmareq_port(struct omap_abe *abe,
+ u32 id, abe_data_format_t *f,
+ u32 d,
+ abe_dma_t *returned_dma_t)
+{
+ _log(ABE_ID_CONNECT_CBPR_DMAREQ_PORT, id, f->f, f->samp_format);
+
+ abe_port[id] = ((abe_port_t *) abe_port_init)[id];
+ (abe_port[id]).format = (*f);
+ abe_port[id].protocol.protocol_switch = DMAREQ_PORT_PROT;
+ abe_port[id].protocol.p.prot_dmareq.iter = abe_dma_port_iteration(f);
+ abe_port[id].protocol.p.prot_dmareq.dma_addr = ABE_DMASTATUS_RAW;
+ abe_port[id].protocol.p.prot_dmareq.dma_data = (1 << d);
+ abe_port[id].status = OMAP_ABE_PORT_INITIALIZED;
+ /* load the dma_t with physical information from AE memory mapping */
+ abe_init_dma_t(id, &((abe_port[id]).protocol));
+ /* load the micro-task parameters */
+ abe_init_io_tasks(id, &((abe_port[id]).format),
+ &((abe_port[id]).protocol));
+ /* load the ATC descriptors - disabled */
+ omap_abe_init_atc(abe, id);
+ /* return the dma pointer address */
+ abe_read_port_address(id, returned_dma_t);
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_connect_cbpr_dmareq_port);
+
+/**
+ * omap_abe_connect_irq_ping_pong_port
+ * @id: port name
+ * @f: desired data format
+ * @I: index of the call-back subroutine to call
+ * @s: half-buffer (ping) size
+ * @p: returned base address of the first (ping) buffer)
+ *
+ * enables the data echanges between a direct access to the DMEM
+ * memory of ABE using cache flush. On each IRQ activation a subroutine
+ * registered with "abe_plug_subroutine" will be called. This subroutine
+ * will generate an amount of samples, send them to DMEM memory and call
+ * "abe_set_ping_pong_buffer" to notify the new amount of samples in the
+ * pong buffer.
+ */
+int omap_abe_connect_irq_ping_pong_port(struct omap_abe *abe,
+ u32 id, abe_data_format_t *f,
+ u32 subroutine_id, u32 size,
+ u32 *sink, u32 dsp_mcu_flag)
+{
+ _log(ABE_ID_CONNECT_IRQ_PING_PONG_PORT, id, f->f, f->samp_format);
+
+ /* ping_pong is only supported on MM_DL */
+ if (id != OMAP_ABE_MM_DL_PORT) {
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_API,
+ ABE_PARAMETER_ERROR);
+ }
+ abe_port[id] = ((abe_port_t *) abe_port_init)[id];
+ (abe_port[id]).format = (*f);
+ (abe_port[id]).protocol.protocol_switch = PINGPONG_PORT_PROT;
+ (abe_port[id]).protocol.p.prot_pingpong.buf_addr =
+ OMAP_ABE_D_PING_ADDR;
+ (abe_port[id]).protocol.p.prot_pingpong.buf_size = size;
+ (abe_port[id]).protocol.p.prot_pingpong.irq_data = (1);
+ abe_init_ping_pong_buffer(OMAP_ABE_MM_DL_PORT, size, 2, sink);
+ if (dsp_mcu_flag == PING_PONG_WITH_MCU_IRQ)
+ (abe_port[id]).protocol.p.prot_pingpong.irq_addr =
+ ABE_MCU_IRQSTATUS_RAW;
+ if (dsp_mcu_flag == PING_PONG_WITH_DSP_IRQ)
+ (abe_port[id]).protocol.p.prot_pingpong.irq_addr =
+ ABE_DSP_IRQSTATUS_RAW;
+ abe_port[id].status = OMAP_ABE_PORT_INITIALIZED;
+ /* load the micro-task parameters */
+ abe_init_io_tasks(id, &((abe_port[id]).format),
+ &((abe_port[id]).protocol));
+ /* load the ATC descriptors - disabled */
+ omap_abe_init_atc(abe, id);
+ *sink = (abe_port[id]).protocol.p.prot_pingpong.buf_addr;
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_connect_irq_ping_pong_port);
+
+/**
+ * omap_abe_connect_serial_port()
+ * @id: port name
+ * @f: data format
+ * @i: peripheral ID (McBSP #1, #2, #3)
+ *
+ * Operations : enables the data echanges between a McBSP and an ATC buffer in
+ * DMEM. This API is used connect 48kHz McBSP streams to MM_DL and 8/16kHz
+ * voice streams to VX_UL, VX_DL, BT_VX_UL, BT_VX_DL. It abstracts the
+ * abe_write_port API.
+ */
+int omap_abe_connect_serial_port(struct omap_abe *abe,
+ u32 id, abe_data_format_t *f,
+ u32 mcbsp_id)
+{
+ _log(ABE_ID_CONNECT_SERIAL_PORT, id, f->samp_format, mcbsp_id);
+
+ abe_port[id] = ((abe_port_t *) abe_port_init)[id];
+ (abe_port[id]).format = (*f);
+ (abe_port[id]).protocol.protocol_switch = SERIAL_PORT_PROT;
+ /* McBSP peripheral connected to ATC */
+ (abe_port[id]).protocol.p.prot_serial.desc_addr = mcbsp_id*ATC_SIZE;
+ /* check the iteration of ATC */
+ (abe_port[id]).protocol.p.prot_serial.iter =
+ abe_dma_port_iter_factor(f);
+ abe_port[id].status = OMAP_ABE_PORT_INITIALIZED;
+ /* load the micro-task parameters */
+ abe_init_io_tasks(id, &((abe_port[id]).format),
+ &((abe_port[id]).protocol));
+ /* load the ATC descriptors - disabled */
+ omap_abe_init_atc(abe, id);
+
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_connect_serial_port);
+
+/**
+ * omap_abe_read_port_address
+ * @dma: output pointer to the DMA iteration and data destination pointer
+ *
+ * This API returns the address of the DMA register used on this audio port.
+ * Depending on the protocol being used, adds the base address offset L3
+ * (DMA) or MPU (ARM)
+ */
+int omap_abe_read_port_address(struct omap_abe *abe,
+ u32 port, abe_dma_t *dma2)
+{
+ abe_dma_t_offset dma1;
+ u32 protocol_switch;
+
+ _log(ABE_ID_READ_PORT_ADDRESS, port, 0, 0);
+
+ dma1 = (abe_port[port]).dma;
+ protocol_switch = abe_port[port].protocol.protocol_switch;
+ switch (protocol_switch) {
+ case PINGPONG_PORT_PROT:
+ /* return the base address of the buffer in L3 and L4 spaces */
+ (*dma2).data = (void *)(dma1.data +
+ ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_DMEM_BASE_OFFSET_MPU);
+ (*dma2).l3_dmem = (void *)(dma1.data +
+ ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_DMEM_BASE_OFFSET_MPU);
+ (*dma2).l4_dmem = (void *)(dma1.data +
+ ABE_DEFAULT_BASE_ADDRESS_L4 + ABE_DMEM_BASE_OFFSET_MPU);
+ break;
+ case DMAREQ_PORT_PROT:
+ /* return the CBPr(L3), DMEM(L3), DMEM(L4) address */
+ (*dma2).data = (void *)(dma1.data +
+ ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_ATC_BASE_OFFSET_MPU);
+ (*dma2).l3_dmem =
+ (void *)((abe_port[port]).protocol.p.prot_dmareq.buf_addr +
+ ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_DMEM_BASE_OFFSET_MPU);
+ (*dma2).l4_dmem =
+ (void *)((abe_port[port]).protocol.p.prot_dmareq.buf_addr +
+ ABE_DEFAULT_BASE_ADDRESS_L4 + ABE_DMEM_BASE_OFFSET_MPU);
+ break;
+ default:
+ break;
+ }
+ (*dma2).iter = (dma1.iter);
+
+ return 0;
+}
+EXPORT_SYMBOL(omap_abe_read_port_address);
+
+/**
+ * abe_init_dma_t
+ * @ id: ABE port ID
+ * @ prot: protocol being used
+ *
+ * load the dma_t with physical information from AE memory mapping
+ */
+void abe_init_dma_t(u32 id, abe_port_protocol_t *prot)
+{
+ abe_dma_t_offset dma;
+ u32 idx;
+ /* default dma_t points to address 0000... */
+ dma.data = 0;
+ dma.iter = 0;
+ switch (prot->protocol_switch) {
+ case PINGPONG_PORT_PROT:
+ for (idx = 0; idx < 32; idx++) {
+ if (((prot->p).prot_pingpong.irq_data) ==
+ (u32) (1 << idx))
+ break;
+ }
+ (prot->p).prot_dmareq.desc_addr =
+ ((CBPr_DMA_RTX0 + idx)*ATC_SIZE);
+ /* translate byte address/size in DMEM words */
+ dma.data = (prot->p).prot_pingpong.buf_addr >> 2;
+ dma.iter = (prot->p).prot_pingpong.buf_size >> 2;
+ break;
+ case DMAREQ_PORT_PROT:
+ for (idx = 0; idx < 32; idx++) {
+ if (((prot->p).prot_dmareq.dma_data) ==
+ (u32) (1 << idx))
+ break;
+ }
+ dma.data = (CIRCULAR_BUFFER_PERIPHERAL_R__0 + (idx << 2));
+ dma.iter = (prot->p).prot_dmareq.iter;
+ (prot->p).prot_dmareq.desc_addr =
+ ((CBPr_DMA_RTX0 + idx)*ATC_SIZE);
+ break;
+ case SLIMBUS_PORT_PROT:
+ case SERIAL_PORT_PROT:
+ case DMIC_PORT_PROT:
+ case MCPDMDL_PORT_PROT:
+ case MCPDMUL_PORT_PROT:
+ default:
+ break;
+ }
+ /* upload the dma type */
+ abe_port[id].dma = dma;
+}
+
+/**
+ * abe_enable_atc
+ * Parameter:
+ * Operations:
+ * Return value:
+ */
+void abe_enable_atc(u32 id)
+{
+ struct omap_abe_atc_desc atc_desc;
+
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM,
+ (abe_port[id]).protocol.p.prot_dmareq.desc_addr,
+ (u32 *) &atc_desc, sizeof(atc_desc));
+ atc_desc.desen = 1;
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ (abe_port[id]).protocol.p.prot_dmareq.desc_addr,
+ (u32 *) &atc_desc, sizeof(atc_desc));
+
+}
+/**
+ * abe_disable_atc
+ * Parameter:
+ * Operations:
+ * Return value:
+ */
+void abe_disable_atc(u32 id)
+{
+ struct omap_abe_atc_desc atc_desc;
+
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM,
+ (abe_port[id]).protocol.p.prot_dmareq.desc_addr,
+ (u32 *) &atc_desc, sizeof(atc_desc));
+ atc_desc.desen = 0;
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ (abe_port[id]).protocol.p.prot_dmareq.desc_addr,
+ (u32 *) &atc_desc, sizeof(atc_desc));
+
+}
+/**
+ * abe_init_io_tasks
+ * @prot : protocol being used
+ *
+ * load the micro-task parameters doing to DMEM <==> SMEM data moves
+ *
+ * I/O descriptors input parameters :
+ * For Read from DMEM usually THR1/THR2 = X+1/X-1
+ * For Write to DMEM usually THR1/THR2 = 2/0
+ * UP_1/2 =X+1/X-1
+ */
+void abe_init_io_tasks(u32 id, abe_data_format_t *format,
+ abe_port_protocol_t *prot)
+{
+ u32 x_io, direction, iter_samples, smem1, smem2, smem3, io_sub_id,
+ io_flag;
+ u32 copy_func_index, before_func_index, after_func_index;
+ u32 dmareq_addr, dmareq_field;
+ u32 sio_desc_address, datasize, iter, nsamp, datasize2, dOppMode32;
+ u32 atc_ptr_saved, atc_ptr_saved2, copy_func_index1;
+ u32 copy_func_index2, atc_desc_address1, atc_desc_address2;
+ struct ABE_SPingPongDescriptor desc_pp;
+ struct ABE_SIODescriptor sio_desc;
+
+ if (prot->protocol_switch == PINGPONG_PORT_PROT) {
+ /* ping_pong is only supported on MM_DL */
+ if (OMAP_ABE_MM_DL_PORT != id) {
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_API,
+ ABE_PARAMETER_ERROR);
+ }
+ smem1 = smem_mm_dl;
+ copy_func_index = (u8) abe_dma_port_copy_subroutine_id(id);
+ dmareq_addr = abe_port[id].protocol.p.prot_pingpong.irq_addr;
+ dmareq_field = abe_port[id].protocol.p.prot_pingpong.irq_data;
+ datasize = abe_dma_port_iter_factor(format);
+ /* number of "samples" either mono or stereo */
+ iter = abe_dma_port_iteration(format);
+ iter_samples = (iter / datasize);
+ /* load the IO descriptor */
+ /* no drift */
+ desc_pp.drift_ASRC = 0;
+ /* no drift */
+ desc_pp.drift_io = 0;
+ desc_pp.hw_ctrl_addr = (u16) dmareq_addr;
+ desc_pp.copy_func_index = (u8) copy_func_index;
+ desc_pp.smem_addr = (u8) smem1;
+ /* DMA req 0 is used for CBPr0 */
+ desc_pp.atc_irq_data = (u8) dmareq_field;
+ /* size of block transfer */
+ desc_pp.x_io = (u8) iter_samples;
+ desc_pp.data_size = (u8) datasize;
+ /* address comunicated in Bytes */
+ desc_pp.workbuff_BaseAddr =
+ (u16) (abe_base_address_pingpong[1]);
+ /* size comunicated in XIO sample */
+ desc_pp.workbuff_Samples = 0;
+ desc_pp.nextbuff0_BaseAddr =
+ (u16) (abe_base_address_pingpong[0]);
+ desc_pp.nextbuff1_BaseAddr =
+ (u16) (abe_base_address_pingpong[1]);
+ if (dmareq_addr == ABE_DMASTATUS_RAW) {
+ desc_pp.nextbuff0_Samples =
+ (u16) ((abe_size_pingpong >> 2) / datasize);
+ desc_pp.nextbuff1_Samples =
+ (u16) ((abe_size_pingpong >> 2) / datasize);
+ } else {
+ desc_pp.nextbuff0_Samples = 0;
+ desc_pp.nextbuff1_Samples = 0;
+ }
+ /* next buffer to send is B1, first IRQ fills B0 */
+ desc_pp.counter = 0;
+ /* send a DMA req to fill B0 with N samples
+ abe_block_copy (COPY_FROM_HOST_TO_ABE,
+ ABE_ATC,
+ ABE_DMASTATUS_RAW,
+ &(abe_port[id].protocol.p.prot_pingpong.irq_data),
+ 4); */
+ sio_desc_address = OMAP_ABE_D_PINGPONGDESC_ADDR;
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ sio_desc_address, (u32 *) &desc_pp,
+ sizeof(desc_pp));
+ } else {
+ io_sub_id = dmareq_addr = ABE_DMASTATUS_RAW;
+ dmareq_field = 0;
+ atc_desc_address1 = atc_desc_address2 = 0;
+ /* default: repeat of the last downlink samples in case of
+ DMA errors, (disable=0x00) */
+ io_flag = 0xFF;
+ datasize2 = datasize = abe_dma_port_iter_factor(format);
+ x_io = (u8) abe_dma_port_iteration(format);
+ nsamp = (x_io / datasize);
+ atc_ptr_saved2 = atc_ptr_saved = DMIC_ATC_PTR_labelID + id;
+ smem1 = abe_port[id].smem_buffer1;
+ smem3 = smem2 = abe_port[id].smem_buffer2;
+ copy_func_index1 = (u8) abe_dma_port_copy_subroutine_id(id);
+ before_func_index = after_func_index =
+ copy_func_index2 = NULL_COPY_CFPID;
+ switch (prot->protocol_switch) {
+ case DMIC_PORT_PROT:
+ /* DMIC port is read in two steps */
+ x_io = x_io >> 1;
+ nsamp = nsamp >> 1;
+ atc_desc_address1 = (ABE_ATC_DMIC_DMA_REQ*ATC_SIZE);
+ io_sub_id = IO_IP_CFPID;
+ break;
+ case MCPDMDL_PORT_PROT:
+ /* PDMDL port is written to in two steps */
+ x_io = x_io >> 1;
+ atc_desc_address1 =
+ (ABE_ATC_MCPDMDL_DMA_REQ*ATC_SIZE);
+ io_sub_id = IO_IP_CFPID;
+ break;
+ case MCPDMUL_PORT_PROT:
+ atc_desc_address1 =
+ (ABE_ATC_MCPDMUL_DMA_REQ*ATC_SIZE);
+ io_sub_id = IO_IP_CFPID;
+ break;
+ case SLIMBUS_PORT_PROT:
+ atc_desc_address1 =
+ abe_port[id].protocol.p.prot_slimbus.desc_addr1;
+ atc_desc_address2 =
+ abe_port[id].protocol.p.prot_slimbus.desc_addr2;
+ copy_func_index2 = NULL_COPY_CFPID;
+ /* @@@@@@
+ #define SPLIT_SMEM_CFPID 9
+ #define MERGE_SMEM_CFPID 10
+ #define SPLIT_TDM_12_CFPID 11
+ #define MERGE_TDM_12_CFPID 12
+ */
+ io_sub_id = IO_IP_CFPID;
+ break;
+ case SERIAL_PORT_PROT: /* McBSP/McASP */
+ atc_desc_address1 =
+ (s16) abe_port[id].protocol.p.prot_serial.
+ desc_addr;
+ io_sub_id = IO_IP_CFPID;
+ break;
+ case DMAREQ_PORT_PROT: /* DMA w/wo CBPr */
+ dmareq_addr =
+ abe_port[id].protocol.p.prot_dmareq.dma_addr;
+ dmareq_field = 0;
+ atc_desc_address1 =
+ abe_port[id].protocol.p.prot_dmareq.desc_addr;
+ io_sub_id = IO_IP_CFPID;
+ break;
+ }
+ /* special situation of the PING_PONG protocol which
+ has its own SIO descriptor format */
+ /*
+ Sequence of operations on ping-pong buffers B0/B1
+ -------------- time ---------------------------->>>>
+ Host Application is ready to send data from DDR to B0
+ SDMA is initialized from "abe_connect_irq_ping_pong_port" to B0
+ FIRMWARE starts with #12 B1 data,
+ sends IRQ/DMAreq, sends #pong B1 data,
+ sends IRQ/DMAreq, sends #ping B0,
+ sends B1 samples
+ ARM / SDMA | fills B0 | fills B1 ... | fills B0 ...
+ Counter 0 1 2 3
+ */
+ switch (id) {
+ case OMAP_ABE_PDM_DL_PORT:
+ abe->MultiFrame[7][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_PDM_DL);
+ abe->MultiFrame[19][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_PDM_DL);
+ break;
+ case OMAP_ABE_TONES_DL_PORT:
+ abe->MultiFrame[20][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_TONES_DL);
+ break;
+ case OMAP_ABE_PDM_UL_PORT:
+ abe->MultiFrame[5][2] = ABE_TASK_ID(C_ABE_FW_TASK_IO_PDM_UL);
+ break;
+ case OMAP_ABE_DMIC_PORT:
+ abe->MultiFrame[2][5] = ABE_TASK_ID(C_ABE_FW_TASK_IO_DMIC);
+ abe->MultiFrame[14][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_DMIC);
+ break;
+ case OMAP_ABE_MM_UL_PORT:
+ copy_func_index1 = COPY_MM_UL_CFPID;
+ before_func_index = ROUTE_MM_UL_CFPID;
+ break;
+ case OMAP_ABE_MM_UL2_PORT:
+ abe->MultiFrame[17][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_UL2);
+ break;
+ case OMAP_ABE_VX_DL_PORT:
+ /* check for 8kHz/16kHz */
+ if (abe_port[id].format.f == 8000) {
+ abe->MultiFrame[TASK_ASRC_VX_DL_SLT]
+ [TASK_ASRC_VX_DL_IDX] =
+ ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_DL_8);
+ abe->MultiFrame[TASK_VX_DL_SLT][TASK_VX_DL_IDX] =
+ ABE_TASK_ID(C_ABE_FW_TASK_VX_DL_8_48);
+ /*Voice_8k_DL_labelID */
+ smem1 = IO_VX_DL_ASRC_labelID;
+ } else {
+ abe->MultiFrame[TASK_ASRC_VX_DL_SLT]
+ [TASK_ASRC_VX_DL_IDX] =
+ ABE_TASK_ID
+ (C_ABE_FW_TASK_ASRC_VX_DL_16);
+ abe->MultiFrame[TASK_VX_DL_SLT][TASK_VX_DL_IDX] =
+ ABE_TASK_ID(C_ABE_FW_TASK_VX_DL_16_48);
+ /* Voice_16k_DL_labelID */
+ smem1 = IO_VX_DL_ASRC_labelID;
+ }
+ abe->MultiFrame[0][2] = ABE_TASK_ID(C_ABE_FW_TASK_IO_VX_DL);
+ break;
+ case OMAP_ABE_VX_UL_PORT:
+ /* check for 8kHz/16kHz */
+ if (abe_port[id].format.f == 8000) {
+ abe->MultiFrame[TASK_ASRC_VX_UL_SLT]
+ [TASK_ASRC_VX_UL_IDX] =
+ ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_UL_8);
+ abe->MultiFrame[TASK_VX_UL_SLT][TASK_VX_UL_IDX] =
+ ABE_TASK_ID(C_ABE_FW_TASK_VX_UL_48_8);
+ /* MultiFrame[TASK_ECHO_SLT][TASK_ECHO_IDX] =
+ ABE_TASK_ID(C_ABE_FW_TASK_ECHO_REF_48_8); */
+ smem1 = Voice_8k_UL_labelID;
+ } else {
+ abe->MultiFrame[TASK_ASRC_VX_UL_SLT]
+ [TASK_ASRC_VX_UL_IDX] =
+ ABE_TASK_ID
+ (C_ABE_FW_TASK_ASRC_VX_UL_16);
+ abe->MultiFrame[TASK_VX_UL_SLT][TASK_VX_UL_IDX] =
+ ABE_TASK_ID(C_ABE_FW_TASK_VX_UL_48_16);
+ /* MultiFrame[TASK_ECHO_SLT][TASK_ECHO_IDX] =
+ ABE_TASK_ID(C_ABE_FW_TASK_ECHO_REF_48_16); */
+ smem1 = Voice_16k_UL_labelID;
+ }
+ abe->MultiFrame[16][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_VX_UL);
+ break;
+ case OMAP_ABE_BT_VX_DL_PORT:
+ /* check for 8kHz/16kHz */
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_MAXTASKBYTESINSLOT_ADDR, &dOppMode32,
+ sizeof(u32));
+ if (abe_port[id].format.f == 8000) {
+ abe->MultiFrame[TASK_ASRC_BT_DL_SLT]
+ [TASK_ASRC_BT_DL_IDX] =
+ ABE_TASK_ID(C_ABE_FW_TASK_ASRC_BT_DL_8);
+ if (dOppMode32 == DOPPMODE32_OPP100) {
+ abe->MultiFrame[TASK_BT_DL_48_8_SLT]
+ [TASK_BT_DL_48_8_IDX] =
+ ABE_TASK_ID
+ (C_ABE_FW_TASK_BT_DL_48_8_OPP100);
+ smem1 = BT_DL_8k_opp100_labelID;
+ } else {
+ abe->MultiFrame[TASK_BT_DL_48_8_SLT]
+ [TASK_BT_DL_48_8_IDX] =
+ ABE_TASK_ID
+ (C_ABE_FW_TASK_BT_DL_48_8);
+ smem1 = BT_DL_8k_labelID;
+ }
+ } else {
+ abe->MultiFrame[TASK_ASRC_BT_DL_SLT]
+ [TASK_ASRC_BT_DL_IDX] =
+ ABE_TASK_ID
+ (C_ABE_FW_TASK_ASRC_BT_DL_16);
+ if (dOppMode32 == DOPPMODE32_OPP100) {
+ abe->MultiFrame[TASK_BT_DL_48_8_SLT]
+ [TASK_BT_DL_48_8_IDX] =
+ ABE_TASK_ID
+ (C_ABE_FW_TASK_BT_DL_48_16_OPP100);
+ smem1 = BT_DL_16k_opp100_labelID;
+ } else {
+ abe->MultiFrame[TASK_BT_DL_48_8_SLT]
+ [TASK_BT_DL_48_8_IDX] =
+ ABE_TASK_ID
+ (C_ABE_FW_TASK_BT_DL_48_16);
+ smem1 = BT_DL_16k_labelID;
+ }
+ }
+ abe->MultiFrame[13][5] = ABE_TASK_ID(C_ABE_FW_TASK_IO_BT_VX_DL);
+ break;
+ case OMAP_ABE_BT_VX_UL_PORT:
+ /* check for 8kHz/16kHz */
+ /* set the SMEM buffer -- programming sequence */
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_MAXTASKBYTESINSLOT_ADDR, &dOppMode32,
+ sizeof(u32));
+ if (abe_port[id].format.f == 8000) {
+ abe->MultiFrame[TASK_ASRC_BT_UL_SLT]
+ [TASK_ASRC_BT_UL_IDX] =
+ ABE_TASK_ID(C_ABE_FW_TASK_ASRC_BT_UL_8);
+ abe->MultiFrame[TASK_BT_UL_8_48_SLT]
+ [TASK_BT_UL_8_48_IDX] =
+ ABE_TASK_ID(C_ABE_FW_TASK_BT_UL_8_48);
+ if (dOppMode32 == DOPPMODE32_OPP100)
+ /* ASRC input buffer, size 40 */
+ smem1 = smem_bt_vx_ul_opp100;
+ else
+ /* at OPP 50 without ASRC */
+ smem1 = BT_UL_8k_labelID;
+ } else {
+ abe->MultiFrame[TASK_ASRC_BT_UL_SLT]
+ [TASK_ASRC_BT_UL_IDX] =
+ ABE_TASK_ID
+ (C_ABE_FW_TASK_ASRC_BT_UL_16);
+ abe->MultiFrame[TASK_BT_UL_8_48_SLT]
+ [TASK_BT_UL_8_48_IDX] =
+ ABE_TASK_ID(C_ABE_FW_TASK_BT_UL_16_48);
+ if (dOppMode32 == DOPPMODE32_OPP100)
+ /* ASRC input buffer, size 40 */
+ smem1 = smem_bt_vx_ul_opp100;
+ else
+ /* at OPP 50 without ASRC */
+ smem1 = BT_UL_16k_labelID;
+ }
+ abe->MultiFrame[15][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_BT_VX_UL);
+ break;
+ case OMAP_ABE_MM_DL_PORT:
+ /* check for CBPr / serial_port / Ping-pong access */
+ abe->MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] =
+ ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_DL);
+ smem1 = smem_mm_dl;
+ break;
+ case OMAP_ABE_MM_EXT_IN_PORT:
+ /* set the SMEM buffer -- programming sequence */
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_MAXTASKBYTESINSLOT_ADDR, &dOppMode32,
+ sizeof(u32));
+ if (dOppMode32 == DOPPMODE32_OPP100)
+ /* ASRC input buffer, size 40 */
+ smem1 = smem_mm_ext_in_opp100;
+ else
+ /* at OPP 50 without ASRC */
+ smem1 = smem_mm_ext_in_opp50;
+
+ abe->MultiFrame[21][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_EXT_IN);
+ break;
+ case OMAP_ABE_MM_EXT_OUT_PORT:
+ abe->MultiFrame[15][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_EXT_OUT);
+ break;
+ default:
+ break;
+ }
+
+ if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN)
+ direction = 0;
+ else
+ /* offset of the write pointer in the ATC descriptor */
+ direction = 3;
+
+ sio_desc.drift_ASRC = 0;
+ sio_desc.drift_io = 0;
+ sio_desc.io_type_idx = (u8) io_sub_id;
+ sio_desc.samp_size = (u8) datasize;
+ sio_desc.hw_ctrl_addr = (u16) (dmareq_addr << 2);
+ sio_desc.atc_irq_data = (u8) dmareq_field;
+ sio_desc.flow_counter = (u16) 0;
+ sio_desc.direction_rw = (u8) direction;
+ sio_desc.repeat_last_samp = (u8) io_flag;
+ sio_desc.nsamp = (u8) nsamp;
+ sio_desc.x_io = (u8) x_io;
+ /* set ATC ON */
+ sio_desc.on_off = 0x80;
+ sio_desc.split_addr1 = (u16) smem1;
+ sio_desc.split_addr2 = (u16) smem2;
+ sio_desc.split_addr3 = (u16) smem3;
+ sio_desc.before_f_index = (u8) before_func_index;
+ sio_desc.after_f_index = (u8) after_func_index;
+ sio_desc.smem_addr1 = (u16) smem1;
+ sio_desc.atc_address1 = (u16) atc_desc_address1;
+ sio_desc.atc_pointer_saved1 = (u16) atc_ptr_saved;
+ sio_desc.data_size1 = (u8) datasize;
+ sio_desc.copy_f_index1 = (u8) copy_func_index1;
+ sio_desc.smem_addr2 = (u16) smem2;
+ sio_desc.atc_address2 = (u16) atc_desc_address2;
+ sio_desc.atc_pointer_saved2 = (u16) atc_ptr_saved2;
+ sio_desc.data_size2 = (u8) datasize2;
+ sio_desc.copy_f_index2 = (u8) copy_func_index2;
+ sio_desc_address = OMAP_ABE_D_IODESCR_ADDR + (id *
+ sizeof(struct ABE_SIODescriptor));
+
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ sio_desc_address, (u32 *) &sio_desc,
+ sizeof(sio_desc));
+
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ OMAP_ABE_D_MULTIFRAME_ADDR, (u32 *) abe->MultiFrame,
+ sizeof(abe->MultiFrame));
+ }
+
+}
+
+/**
+ * omap_abe_select_main_port - Select stynchronization port for Event generator.
+ * @id: audio port name
+ *
+ * tells the FW which is the reference stream for adjusting
+ * the processing on 23/24/25 slots
+ */
+int omap_abe_select_main_port(u32 id)
+{
+ u32 selection;
+
+ _log(ABE_ID_SELECT_MAIN_PORT, id, 0, 0);
+
+ /* flow control */
+ selection = OMAP_ABE_D_IODESCR_ADDR + id * sizeof(struct ABE_SIODescriptor) +
+ flow_counter_;
+ /* when the main port is a sink port from AESS point of view
+ the sign the firmware task analysis must be changed */
+ selection &= 0xFFFFL;
+ if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN)
+ selection |= 0x80000;
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM, OMAP_ABE_D_SLOT23_CTRL_ADDR,
+ &selection, 4);
+ return 0;
+}
+/**
+ * abe_decide_main_port - Select stynchronization port for Event generator.
+ * @id: audio port name
+ *
+ * tells the FW which is the reference stream for adjusting
+ * the processing on 23/24/25 slots
+ *
+ * takes the first port in a list which is slave on the data interface
+ */
+u32 abe_valid_port_for_synchro(u32 id)
+{
+ if ((abe_port[id].protocol.protocol_switch ==
+ DMAREQ_PORT_PROT) ||
+ (abe_port[id].protocol.protocol_switch ==
+ PINGPONG_PORT_PROT) ||
+ (abe_port[id].status != OMAP_ABE_PORT_ACTIVITY_RUNNING))
+ return 0;
+ else
+ return 1;
+}
+void abe_decide_main_port(void)
+{
+ u32 id, id_not_found;
+ id_not_found = 1;
+ for (id = 0; id < LAST_PORT_ID - 1; id++) {
+ if (abe_valid_port_for_synchro(abe_port_priority[id])) {
+ id_not_found = 0;
+ break;
+ }
+ }
+ /* if no port is currently activated, the default one is PDM_DL */
+ if (id_not_found)
+ omap_abe_select_main_port(OMAP_ABE_PDM_DL_PORT);
+ else
+ omap_abe_select_main_port(abe_port_priority[id]);
+}
+/**
+ * abe_format_switch
+ * @f: port format
+ * @iter: port iteration
+ * @mulfac: multiplication factor
+ *
+ * translates the sampling and data length to ITER number for the DMA
+ * and the multiplier factor to apply during data move with DMEM
+ *
+ */
+void abe_format_switch(abe_data_format_t *f, u32 *iter, u32 *mulfac)
+{
+ u32 n_freq;
+#if FW_SCHED_LOOP_FREQ == 4000
+ switch (f->f) {
+ /* nb of samples processed by scheduling loop */
+ case 8000:
+ n_freq = 2;
+ break;
+ case 16000:
+ n_freq = 4;
+ break;
+ case 24000:
+ n_freq = 6;
+ break;
+ case 44100:
+ n_freq = 12;
+ break;
+ case 96000:
+ n_freq = 24;
+ break;
+ default/*case 48000 */ :
+ n_freq = 12;
+ break;
+ }
+#else
+ /* erroneous cases */
+ n_freq = 0;
+#endif
+ switch (f->samp_format) {
+ case MONO_MSB:
+ case MONO_RSHIFTED_16:
+ case STEREO_16_16:
+ *mulfac = 1;
+ break;
+ case STEREO_MSB:
+ case STEREO_RSHIFTED_16:
+ *mulfac = 2;
+ break;
+ case THREE_MSB:
+ *mulfac = 3;
+ break;
+ case FOUR_MSB:
+ *mulfac = 4;
+ break;
+ case FIVE_MSB:
+ *mulfac = 5;
+ break;
+ case SIX_MSB:
+ *mulfac = 6;
+ break;
+ case SEVEN_MSB:
+ *mulfac = 7;
+ break;
+ case EIGHT_MSB:
+ *mulfac = 8;
+ break;
+ case NINE_MSB:
+ *mulfac = 9;
+ break;
+ default:
+ *mulfac = 1;
+ break;
+ }
+ *iter = (n_freq * (*mulfac));
+}
+/**
+ * abe_dma_port_iteration
+ * @f: port format
+ *
+ * translates the sampling and data length to ITER number for the DMA
+ */
+u32 abe_dma_port_iteration(abe_data_format_t *f)
+{
+ u32 iter, mulfac;
+ abe_format_switch(f, &iter, &mulfac);
+ return iter;
+}
+/**
+ * abe_dma_port_iter_factor
+ * @f: port format
+ *
+ * returns the multiplier factor to apply during data move with DMEM
+ */
+u32 abe_dma_port_iter_factor(abe_data_format_t *f)
+{
+ u32 iter, mulfac;
+ abe_format_switch(f, &iter, &mulfac);
+ return mulfac;
+}
+/**
+ * omap_abe_dma_port_iter_factor
+ * @f: port format
+ *
+ * returns the multiplier factor to apply during data move with DMEM
+ */
+u32 omap_abe_dma_port_iter_factor(struct omap_abe_data_format *f)
+{
+ u32 iter, mulfac;
+ abe_format_switch((abe_data_format_t *)f, &iter, &mulfac);
+ return mulfac;
+}
+/**
+ * abe_dma_port_copy_subroutine_id
+ *
+ * @port_id: ABE port ID
+ *
+ * returns the index of the function doing the copy in I/O tasks
+ */
+u32 abe_dma_port_copy_subroutine_id(u32 port_id)
+{
+ u32 sub_id;
+ if (abe_port[port_id].protocol.direction == ABE_ATC_DIRECTION_IN) {
+ switch (abe_port[port_id].format.samp_format) {
+ case MONO_MSB:
+ sub_id = D2S_MONO_MSB_CFPID;
+ break;
+ case MONO_RSHIFTED_16:
+ sub_id = D2S_MONO_RSHIFTED_16_CFPID;
+ break;
+ case STEREO_RSHIFTED_16:
+ sub_id = D2S_STEREO_RSHIFTED_16_CFPID;
+ break;
+ case STEREO_16_16:
+ sub_id = D2S_STEREO_16_16_CFPID;
+ break;
+ case STEREO_MSB:
+ sub_id = D2S_STEREO_MSB_CFPID;
+ break;
+ case SIX_MSB:
+ if (port_id == OMAP_ABE_DMIC_PORT) {
+ sub_id = COPY_DMIC_CFPID;
+ break;
+ }
+ default:
+ sub_id = NULL_COPY_CFPID;
+ break;
+ }
+ } else {
+ switch (abe_port[port_id].format.samp_format) {
+ case MONO_MSB:
+ sub_id = S2D_MONO_MSB_CFPID;
+ break;
+ case MONO_RSHIFTED_16:
+ sub_id = S2D_MONO_RSHIFTED_16_CFPID;
+ break;
+ case STEREO_RSHIFTED_16:
+ sub_id = S2D_STEREO_RSHIFTED_16_CFPID;
+ break;
+ case STEREO_16_16:
+ sub_id = S2D_STEREO_16_16_CFPID;
+ break;
+ case STEREO_MSB:
+ sub_id = S2D_STEREO_MSB_CFPID;
+ break;
+ case SIX_MSB:
+ if (port_id == OMAP_ABE_PDM_DL_PORT) {
+ sub_id = COPY_MCPDM_DL_CFPID;
+ break;
+ }
+ if (port_id == OMAP_ABE_MM_UL_PORT) {
+ sub_id = COPY_MM_UL_CFPID;
+ break;
+ }
+ case THREE_MSB:
+ case FOUR_MSB:
+ case FIVE_MSB:
+ case SEVEN_MSB:
+ case EIGHT_MSB:
+ case NINE_MSB:
+ sub_id = COPY_MM_UL_CFPID;
+ break;
+ default:
+ sub_id = NULL_COPY_CFPID;
+ break;
+ }
+ }
+ return sub_id;
+}
+
+/**
+ * abe_read_remaining_data
+ * @id: ABE port_ID
+ * @n: size pointer to the remaining number of 32bits words
+ *
+ * computes the remaining amount of data in the buffer.
+ */
+abehal_status abe_read_remaining_data(u32 port, u32 *n)
+{
+ u32 sio_pp_desc_address;
+ struct ABE_SPingPongDescriptor desc_pp;
+
+ _log(ABE_ID_READ_REMAINING_DATA, port, 0, 0);
+
+ /*
+ * read the port SIO descriptor and extract the
+ * current pointer address after reading the counter
+ */
+ sio_pp_desc_address = OMAP_ABE_D_PINGPONGDESC_ADDR;
+ omap_abe_mem_read(abe, OMAP_ABE_DMEM, sio_pp_desc_address,
+ (u32 *) &desc_pp, sizeof(struct ABE_SPingPongDescriptor));
+ *n = desc_pp.workbuff_Samples;
+
+ return 0;
+}
+EXPORT_SYMBOL(abe_read_remaining_data);
diff --git a/sound/soc/omap/abe/abe_port.h b/sound/soc/omap/abe/abe_port.h
new file mode 100644
index 0000000..290f8b5
--- /dev/null
+++ b/sound/soc/omap/abe/abe_port.h
@@ -0,0 +1,161 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_PORT_H_
+#define _ABE_PORT_H_
+
+struct omap_abe_data_format {
+ /* Sampling frequency of the stream */
+ u32 f;
+ /* Sample format type */
+ u32 samp_format;
+};
+
+struct omap_abe_port_protocol {
+ /* Direction=0 means input from AESS point of view */
+ u32 direction;
+ /* Protocol type (switch) during the data transfers */
+ u32 protocol_switch;
+ union {
+ /* McBSP/McASP peripheral connected to ATC */
+ struct {
+ u32 desc_addr;
+ /* Address of ATC McBSP/McASP descriptor's in bytes */
+ u32 buf_addr;
+ /* DMEM address in bytes */
+ u32 buf_size;
+ /* ITERation on each DMAreq signals */
+ u32 iter;
+ } serial;
+ /* DMIC peripheral connected to ATC */
+ struct {
+ /* DMEM address in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size in bytes */
+ u32 buf_size;
+ /* Number of activated DMIC */
+ u32 nbchan;
+ } dmic;
+ /* McPDMDL peripheral connected to ATC */
+ struct {
+ /* DMEM address in bytes */
+ u32 buf_addr;
+ /* DMEM size in bytes */
+ u32 buf_size;
+ /* Control allowed on McPDM DL */
+ u32 control;
+ } mcpdmdl;
+ /* McPDMUL peripheral connected to ATC */
+ struct {
+ /* DMEM address size in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size size in bytes */
+ u32 buf_size;
+ } mcpdmul;
+ /* Ping-Pong interface to the Host using cache-flush */
+ struct {
+ /* Address of ATC descriptor's */
+ u32 desc_addr;
+ /* DMEM buffer base address in bytes */
+ u32 buf_addr;
+ /* DMEM size in bytes for each ping and pong buffers */
+ u32 buf_size;
+ /* IRQ address (either DMA (0) MCU (1) or DSP(2)) */
+ u32 irq_addr;
+ /* IRQ data content loaded in the AESS IRQ register */
+ u32 irq_data;
+ /* Call-back function upon IRQ reception */
+ u32 callback;
+ } pingpong;
+ /* DMAreq line to CBPr */
+ struct {
+ /* Address of ATC descriptor's */
+ u32 desc_addr;
+ /* DMEM buffer address in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size size in bytes */
+ u32 buf_size;
+ /* ITERation on each DMAreq signals */
+ u32 iter;
+ /* DMAreq address */
+ u32 dma_addr;
+ /* DMA/AESS = 1 << #DMA */
+ u32 dma_data;
+ } dmareq;
+ /* Circular buffer - direct addressing to DMEM */
+ struct {
+ /* DMEM buffer base address in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size in bytes */
+ u32 buf_size;
+ /* DMAreq address */
+ u32 dma_addr;
+ /* DMA/AESS = 1 << #DMA */
+ u32 dma_data;
+ } circular_buffer;
+ } port;
+};
+
+extern const abe_port_t abe_port_init[];
+extern abe_port_t abe_port[];
+extern const u32 abe_port_priority[];
+
+int omap_abe_select_main_port(u32 id);
+u32 omap_abe_dma_port_iter_factor(struct omap_abe_data_format *f);
+
+#endif/* _ABE_PORT_H_ */
diff --git a/sound/soc/omap/abe/abe_ref.h b/sound/soc/omap/abe/abe_ref.h
new file mode 100644
index 0000000..4c8a9bb
--- /dev/null
+++ b/sound/soc/omap/abe/abe_ref.h
@@ -0,0 +1,152 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_REF_H_
+#define _ABE_REF_H_
+
+#include "abe_api.h"
+
+/*
+ * 'ABE_PRO.H' all non-API prototypes for INI, IRQ, SEQ ...
+ */
+/*
+ * HAL EXTERNAL AP
+ */
+/*
+ * HAL INTERNAL AP
+ */
+void abe_decide_main_port(void);
+void abe_reset_all_ports(void);
+void abe_reset_all_fifo(void);
+void abe_reset_all_sequence(void);
+u32 abe_dma_port_iteration(abe_data_format_t *format);
+void abe_read_sys_clock(u32 *time);
+void abe_enable_atc(u32 id);
+void abe_disable_atc(u32 id);
+void abe_init_io_tasks(u32 id, abe_data_format_t *format,
+ abe_port_protocol_t *prot);
+void abe_init_dma_t(u32 id, abe_port_protocol_t *prot);
+u32 abe_dma_port_iter_factor(abe_data_format_t *f);
+u32 abe_dma_port_copy_subroutine_id(u32 i);
+void abe_call_subroutine(u32 idx, u32 p1, u32 p2, u32 p3, u32 p4);
+void abe_monitoring(void);
+void abe_add_subroutine(u32 *id, abe_subroutine2 f, u32 nparam, u32 *params);
+abehal_status abe_read_next_ping_pong_buffer(u32 port, u32 *p, u32 *n);
+void abe_irq_ping_pong(void);
+void abe_irq_check_for_sequences(u32 seq_info);
+void abe_default_irq_pingpong_player(void);
+void abe_default_irq_pingpong_player_32bits(void);
+void abe_rshifted16_irq_pingpong_player_32bits(void);
+void abe_1616_irq_pingpong_player_1616bits(void);
+void abe_default_irq_aps_adaptation(void);
+void abe_irq_aps(u32 aps_info);
+void abe_dbg_error_log(u32 x);
+void abe_init_asrc_vx_dl(s32 dppm);
+void abe_init_asrc_vx_ul(s32 dppm);
+void abe_init_asrc_mm_ext_in(s32 dppm);
+void abe_init_asrc_bt_ul(s32 dppm);
+void abe_init_asrc_bt_dl(s32 dppm);
+
+void omap_abe_hw_configuration(struct omap_abe *abe);
+void omap_abe_gain_offset(struct omap_abe *abe, u32 id, u32 *mixer_offset);
+int omap_abe_use_compensated_gain(struct omap_abe *abe, int on_off);
+
+/*
+ * HAL INTERNAL DATA
+ */
+extern const u32 abe_port_priority[LAST_PORT_ID - 1];
+extern const u32 abe_firmware_array[ABE_FIRMWARE_MAX_SIZE];
+extern const u32 abe_atc_srcid[];
+extern const u32 abe_atc_dstid[];
+extern const abe_port_t abe_port_init[];
+extern const abe_seq_t all_sequence_init[];
+extern const abe_router_t abe_router_ul_table_preset
+ [NBROUTE_CONFIG][NBROUTE_UL];
+extern const abe_sequence_t seq_null;
+
+extern abe_port_t abe_port[];
+extern abe_seq_t all_sequence[];
+extern abe_router_t abe_router_ul_table[NBROUTE_CONFIG_MAX][NBROUTE_UL];
+/* table of new subroutines called in the sequence */
+extern abe_subroutine2 abe_all_subsubroutine[MAXNBSUBROUTINE];
+/* number of parameters per calls */
+extern u32 abe_all_subsubroutine_nparam[MAXNBSUBROUTINE];
+extern u32 abe_subroutine_id[MAXNBSUBROUTINE];
+extern u32 *abe_all_subroutine_params[MAXNBSUBROUTINE];
+extern u32 abe_subroutine_write_pointer;
+extern abe_sequence_t abe_all_sequence[MAXNBSEQUENCE];
+extern u32 abe_sequence_write_pointer;
+/* current number of pending sequences (avoids to look in the table) */
+extern u32 abe_nb_pending_sequences;
+/* pending sequences due to ressource collision */
+extern u32 abe_pending_sequences[MAXNBSEQUENCE];
+/* mask of unsharable ressources among other sequences */
+extern u32 abe_global_sequence_mask;
+/* table of active sequences */
+extern abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE][MAXSEQUENCESTEPS];
+/* index of the plugged subroutine doing ping-pong cache-flush
+ DMEM accesses */
+extern u32 abe_irq_aps_adaptation_id;
+/* base addresses of the ping pong buffers */
+extern u32 abe_base_address_pingpong[MAX_PINGPONG_BUFFERS];
+/* size of each ping/pong buffers */
+extern u32 abe_size_pingpong;
+/* number of ping/pong buffer being used */
+extern u32 abe_nb_pingpong;
+
+#endif/* _ABE_REF_H_ */
diff --git a/sound/soc/omap/abe/abe_seq.c b/sound/soc/omap/abe/abe_seq.c
new file mode 100644
index 0000000..6ae2aa5
--- /dev/null
+++ b/sound/soc/omap/abe/abe_seq.c
@@ -0,0 +1,308 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#include "abe_legacy.h"
+
+#include "abe_mem.h"
+
+extern struct omap_abe *abe;
+extern u32 abe_irq_pingpong_player_id;
+
+/**
+ * abe_null_subroutine
+ *
+ */
+void abe_null_subroutine_0(void)
+{
+}
+void abe_null_subroutine_2(u32 a, u32 b)
+{
+}
+void abe_null_subroutine_4(u32 a, u32 b, u32 c, u32 d)
+{
+}
+/**
+ * abe_init_subroutine_table - initializes the default table of pointers
+ * to subroutines
+ *
+ * initializes the default table of pointers to subroutines
+ *
+ */
+void abe_init_subroutine_table(void)
+{
+ u32 id;
+ /* reset the table's pointers */
+ abe_subroutine_write_pointer = 0;
+ /* the first index is the NULL task */
+ abe_add_subroutine(&id, (abe_subroutine2) abe_null_subroutine_2,
+ SUB_0_PARAM, (u32 *) 0);
+ /* write mixer has 4 parameters */
+ abe_add_subroutine(&(abe_subroutine_id[SUB_WRITE_MIXER]),
+ (abe_subroutine2) abe_write_mixer, SUB_4_PARAM,
+ (u32 *) 0);
+ /* ping-pong player IRQ */
+ abe_add_subroutine(&abe_irq_pingpong_player_id,
+ (abe_subroutine2) abe_null_subroutine_0, SUB_0_PARAM,
+ (u32 *) 0);
+}
+/**
+ * abe_add_subroutine
+ * @id: ABE port id
+ * @f: pointer to the subroutines
+ * @nparam: number of parameters
+ * @params: pointer to the psrameters
+ *
+ * add one function pointer more and returns the index to it
+ */
+void abe_add_subroutine(u32 *id, abe_subroutine2 f, u32 nparam, u32 *params)
+{
+ u32 i, i_found;
+ if ((abe_subroutine_write_pointer >= MAXNBSUBROUTINE) ||
+ ((u32) f == 0)) {
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_SEQ,
+ ABE_PARAMETER_OVERFLOW);
+ } else {
+ /* search if this subroutine address was not already
+ * declared, then return the previous index
+ */
+ for (i_found = abe_subroutine_write_pointer, i = 0;
+ i < abe_subroutine_write_pointer; i++) {
+ if (f == abe_all_subsubroutine[i])
+ i_found = i;
+ }
+ if (i_found == abe_subroutine_write_pointer) {
+ *id = abe_subroutine_write_pointer;
+ abe_all_subsubroutine
+ [abe_subroutine_write_pointer] = (f);
+ abe_all_subroutine_params
+ [abe_subroutine_write_pointer] = params;
+ abe_all_subsubroutine_nparam
+ [abe_subroutine_write_pointer] = nparam;
+ abe_subroutine_write_pointer++;
+ } else {
+ abe_all_subroutine_params[i_found] = params;
+ *id = i_found;
+ }
+ }
+}
+/**
+ * abe_add_sequence
+ * @id: returned sequence index after pluging a new sequence
+ * (index in the tables)
+ * @s: sequence to be inserted
+ *
+ * Load a time-sequenced operations.
+ */
+void abe_add_sequence(u32 *id, abe_sequence_t *s)
+{
+ abe_seq_t *seq_src, *seq_dst;
+ u32 i, no_end_of_sequence_found;
+ seq_src = &(s->seq1);
+ seq_dst = &((abe_all_sequence[abe_sequence_write_pointer]).seq1);
+ if ((abe_sequence_write_pointer >= MAXNBSEQUENCE) || ((u32) s == 0)) {
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_SEQ,
+ ABE_PARAMETER_OVERFLOW);
+ } else {
+ *id = abe_subroutine_write_pointer;
+ /* copy the mask */
+ (abe_all_sequence[abe_sequence_write_pointer]).mask = s->mask;
+ for (no_end_of_sequence_found = 1, i = 0; i < MAXSEQUENCESTEPS;
+ i++, seq_src++, seq_dst++) {
+ /* sequence copied line by line */
+ (*seq_dst) = (*seq_src);
+ /* stop when the line start with time=(-1) */
+ if ((*(s32 *) seq_src) == (-1)) {
+ /* stop when the line start with time=(-1) */
+ no_end_of_sequence_found = 0;
+ break;
+ }
+ }
+ abe_subroutine_write_pointer++;
+ if (no_end_of_sequence_found)
+ omap_abe_dbg_error(abe, OMAP_ABE_ERR_API,
+ ABE_SEQTOOLONG);
+ }
+}
+/**
+ * abe_reset_one_sequence
+ * @id: sequence ID
+ *
+ * load default configuration for that sequence
+ * kill running activities
+ */
+void abe_reset_one_sequence(u32 id)
+{
+}
+/**
+ * abe_reset_all_sequence
+ *
+ * load default configuration for all sequences
+ * kill any running activities
+ */
+void omap_abe_reset_all_sequence(struct omap_abe *abe)
+{
+ u32 i;
+ abe_init_subroutine_table();
+ /* arrange to have the first sequence index=0 to the NULL operation
+ sequence */
+ abe_add_sequence(&i, (abe_sequence_t *) &seq_null);
+ /* reset the the collision protection mask */
+ abe_global_sequence_mask = 0;
+ /* reset the pending sequences list */
+ for (abe_nb_pending_sequences = i = 0; i < MAXNBSEQUENCE; i++)
+ abe_pending_sequences[i] = 0;
+}
+/**
+ * abe_call_subroutine
+ * @idx: index to the table of all registered Call-backs and subroutines
+ *
+ * run and log a subroutine
+ */
+void abe_call_subroutine(u32 idx, u32 p1, u32 p2, u32 p3, u32 p4)
+{
+ abe_subroutine0 f0;
+ abe_subroutine1 f1;
+ abe_subroutine2 f2;
+ abe_subroutine3 f3;
+ abe_subroutine4 f4;
+ u32 *params;
+ if (idx > MAXNBSUBROUTINE)
+ return;
+ switch (idx) {
+ /* call the subroutines defined at compilation time
+ (const .. sequences) */
+#if 0
+ case SUB_WRITE_MIXER_DL1:
+ abe_write_mixer_dl1(p1, p2, p3)
+ abe_fprintf("write_mixer");
+ break;
+#endif
+ /* call the subroutines defined at execution time
+ (dynamic sequences) */
+ default:
+ switch (abe_all_subsubroutine_nparam[idx]) {
+ case SUB_0_PARAM:
+ f0 = (abe_subroutine0) abe_all_subsubroutine[idx];
+ (*f0) ();
+ break;
+ case SUB_1_PARAM:
+ f1 = (abe_subroutine1) abe_all_subsubroutine[idx];
+ params = abe_all_subroutine_params
+ [abe_irq_pingpong_player_id];
+ if (params != (u32 *) 0)
+ p1 = params[0];
+ (*f1) (p1);
+ break;
+ case SUB_2_PARAM:
+ f2 = abe_all_subsubroutine[idx];
+ params = abe_all_subroutine_params
+ [abe_irq_pingpong_player_id];
+ if (params != (u32 *) 0) {
+ p1 = params[0];
+ p2 = params[1];
+ }
+ (*f2) (p1, p2);
+ break;
+ case SUB_3_PARAM:
+ f3 = (abe_subroutine3) abe_all_subsubroutine[idx];
+ params = abe_all_subroutine_params
+ [abe_irq_pingpong_player_id];
+ if (params != (u32 *) 0) {
+ p1 = params[0];
+ p2 = params[1];
+ p3 = params[2];
+ }
+ (*f3) (p1, p2, p3);
+ break;
+ case SUB_4_PARAM:
+ f4 = (abe_subroutine4) abe_all_subsubroutine[idx];
+ params = abe_all_subroutine_params
+ [abe_irq_pingpong_player_id];
+ if (params != (u32 *) 0) {
+ p1 = params[0];
+ p2 = params[1];
+ p3 = params[2];
+ p4 = params[3];
+ }
+ (*f4) (p1, p2, p3, p4);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+/**
+ * abe_set_sequence_time_accuracy
+ * @fast: fast counter
+ * @slow: slow counter
+ *
+ */
+abehal_status abe_set_sequence_time_accuracy(u32 fast, u32 slow)
+{
+ u32 data;
+ _log(ABE_ID_SET_SEQUENCE_TIME_ACCURACY, fast, slow, 0);
+ data = minimum(MAX_UINT16, fast / FW_SCHED_LOOP_FREQ_DIV1000);
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM, OMAP_ABE_D_FASTCOUNTER_ADDR,
+ &data, sizeof(data));
+ data = minimum(MAX_UINT16, slow / FW_SCHED_LOOP_FREQ_DIV1000);
+ omap_abe_mem_write(abe, OMAP_ABE_DMEM, OMAP_ABE_D_SLOWCOUNTER_ADDR,
+ &data, sizeof(data));
+ return 0;
+}
+EXPORT_SYMBOL(abe_set_sequence_time_accuracy);
diff --git a/sound/soc/omap/abe/abe_seq.h b/sound/soc/omap/abe/abe_seq.h
new file mode 100644
index 0000000..e5047ad
--- /dev/null
+++ b/sound/soc/omap/abe/abe_seq.h
@@ -0,0 +1,64 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_SEQ_H_
+#define _ABE_SEQ_H_
+
+void omap_abe_reset_all_sequence(struct omap_abe *abe);
+
+#endif /* _ABE_SEQ_H_ */
diff --git a/sound/soc/omap/abe/abe_sm_addr.h b/sound/soc/omap/abe/abe_sm_addr.h
new file mode 100644
index 0000000..ad2295f
--- /dev/null
+++ b/sound/soc/omap/abe/abe_sm_addr.h
@@ -0,0 +1,537 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#define OMAP_ABE_INIT_SM_ADDR 0x0
+#define OMAP_ABE_INIT_SM_SIZE 0x9B8
+
+#define OMAP_ABE_S_DATA0_ADDR 0x9B8
+#define OMAP_ABE_S_DATA0_SIZE 0x8
+
+#define OMAP_ABE_S_TEMP_ADDR 0x9C0
+#define OMAP_ABE_S_TEMP_SIZE 0x8
+
+#define OMAP_ABE_S_PHOENIXOFFSET_ADDR 0x9C8
+#define OMAP_ABE_S_PHOENIXOFFSET_SIZE 0x8
+
+#define OMAP_ABE_S_GTARGET1_ADDR 0x9D0
+#define OMAP_ABE_S_GTARGET1_SIZE 0x38
+
+#define OMAP_ABE_S_GTARGET_DL1_ADDR 0xA08
+#define OMAP_ABE_S_GTARGET_DL1_SIZE 0x10
+
+#define OMAP_ABE_S_GTARGET_DL2_ADDR 0xA18
+#define OMAP_ABE_S_GTARGET_DL2_SIZE 0x10
+
+#define OMAP_ABE_S_GTARGET_ECHO_ADDR 0xA28
+#define OMAP_ABE_S_GTARGET_ECHO_SIZE 0x8
+
+#define OMAP_ABE_S_GTARGET_SDT_ADDR 0xA30
+#define OMAP_ABE_S_GTARGET_SDT_SIZE 0x8
+
+#define OMAP_ABE_S_GTARGET_VXREC_ADDR 0xA38
+#define OMAP_ABE_S_GTARGET_VXREC_SIZE 0x10
+
+#define OMAP_ABE_S_GTARGET_UL_ADDR 0xA48
+#define OMAP_ABE_S_GTARGET_UL_SIZE 0x10
+
+#define OMAP_ABE_S_GTARGET_BTUL_ADDR 0xA58
+#define OMAP_ABE_S_GTARGET_BTUL_SIZE 0x8
+
+#define OMAP_ABE_S_GCURRENT_ADDR 0xA60
+#define OMAP_ABE_S_GCURRENT_SIZE 0x90
+
+#define OMAP_ABE_S_GAIN_ONE_ADDR 0xAF0
+#define OMAP_ABE_S_GAIN_ONE_SIZE 0x8
+
+#define OMAP_ABE_S_TONES_ADDR 0xAF8
+#define OMAP_ABE_S_TONES_SIZE 0x60
+
+#define OMAP_ABE_S_VX_DL_ADDR 0xB58
+#define OMAP_ABE_S_VX_DL_SIZE 0x60
+
+#define OMAP_ABE_S_MM_UL2_ADDR 0xBB8
+#define OMAP_ABE_S_MM_UL2_SIZE 0x60
+
+#define OMAP_ABE_S_MM_DL_ADDR 0xC18
+#define OMAP_ABE_S_MM_DL_SIZE 0x60
+
+#define OMAP_ABE_S_DL1_M_OUT_ADDR 0xC78
+#define OMAP_ABE_S_DL1_M_OUT_SIZE 0x60
+
+#define OMAP_ABE_S_DL2_M_OUT_ADDR 0xCD8
+#define OMAP_ABE_S_DL2_M_OUT_SIZE 0x60
+
+#define OMAP_ABE_S_ECHO_M_OUT_ADDR 0xD38
+#define OMAP_ABE_S_ECHO_M_OUT_SIZE 0x60
+
+#define OMAP_ABE_S_SDT_M_OUT_ADDR 0xD98
+#define OMAP_ABE_S_SDT_M_OUT_SIZE 0x60
+
+#define OMAP_ABE_S_VX_UL_ADDR 0xDF8
+#define OMAP_ABE_S_VX_UL_SIZE 0x60
+
+#define OMAP_ABE_S_VX_UL_M_ADDR 0xE58
+#define OMAP_ABE_S_VX_UL_M_SIZE 0x60
+
+#define OMAP_ABE_S_BT_DL_ADDR 0xEB8
+#define OMAP_ABE_S_BT_DL_SIZE 0x60
+
+#define OMAP_ABE_S_BT_UL_ADDR 0xF18
+#define OMAP_ABE_S_BT_UL_SIZE 0x60
+
+#define OMAP_ABE_S_BT_DL_8K_ADDR 0xF78
+#define OMAP_ABE_S_BT_DL_8K_SIZE 0x18
+
+#define OMAP_ABE_S_BT_DL_16K_ADDR 0xF90
+#define OMAP_ABE_S_BT_DL_16K_SIZE 0x28
+
+#define OMAP_ABE_S_BT_UL_8K_ADDR 0xFB8
+#define OMAP_ABE_S_BT_UL_8K_SIZE 0x10
+
+#define OMAP_ABE_S_BT_UL_16K_ADDR 0xFC8
+#define OMAP_ABE_S_BT_UL_16K_SIZE 0x20
+
+#define OMAP_ABE_S_SDT_F_ADDR 0xFE8
+#define OMAP_ABE_S_SDT_F_SIZE 0x60
+
+#define OMAP_ABE_S_SDT_F_DATA_ADDR 0x1048
+#define OMAP_ABE_S_SDT_F_DATA_SIZE 0x48
+
+#define OMAP_ABE_S_MM_DL_OSR_ADDR 0x1090
+#define OMAP_ABE_S_MM_DL_OSR_SIZE 0xC0
+
+#define OMAP_ABE_S_24_ZEROS_ADDR 0x1150
+#define OMAP_ABE_S_24_ZEROS_SIZE 0xC0
+
+#define OMAP_ABE_S_DMIC1_ADDR 0x1210
+#define OMAP_ABE_S_DMIC1_SIZE 0x60
+
+#define OMAP_ABE_S_DMIC2_ADDR 0x1270
+#define OMAP_ABE_S_DMIC2_SIZE 0x60
+
+#define OMAP_ABE_S_DMIC3_ADDR 0x12D0
+#define OMAP_ABE_S_DMIC3_SIZE 0x60
+
+#define OMAP_ABE_S_AMIC_ADDR 0x1330
+#define OMAP_ABE_S_AMIC_SIZE 0x60
+
+#define OMAP_ABE_S_DMIC1_L_ADDR 0x1390
+#define OMAP_ABE_S_DMIC1_L_SIZE 0x60
+
+#define OMAP_ABE_S_DMIC1_R_ADDR 0x13F0
+#define OMAP_ABE_S_DMIC1_R_SIZE 0x60
+
+#define OMAP_ABE_S_DMIC2_L_ADDR 0x1450
+#define OMAP_ABE_S_DMIC2_L_SIZE 0x60
+
+#define OMAP_ABE_S_DMIC2_R_ADDR 0x14B0
+#define OMAP_ABE_S_DMIC2_R_SIZE 0x60
+
+#define OMAP_ABE_S_DMIC3_L_ADDR 0x1510
+#define OMAP_ABE_S_DMIC3_L_SIZE 0x60
+
+#define OMAP_ABE_S_DMIC3_R_ADDR 0x1570
+#define OMAP_ABE_S_DMIC3_R_SIZE 0x60
+
+#define OMAP_ABE_S_BT_UL_L_ADDR 0x15D0
+#define OMAP_ABE_S_BT_UL_L_SIZE 0x60
+
+#define OMAP_ABE_S_BT_UL_R_ADDR 0x1630
+#define OMAP_ABE_S_BT_UL_R_SIZE 0x60
+
+#define OMAP_ABE_S_AMIC_L_ADDR 0x1690
+#define OMAP_ABE_S_AMIC_L_SIZE 0x60
+
+#define OMAP_ABE_S_AMIC_R_ADDR 0x16F0
+#define OMAP_ABE_S_AMIC_R_SIZE 0x60
+
+#define OMAP_ABE_S_ECHOREF_L_ADDR 0x1750
+#define OMAP_ABE_S_ECHOREF_L_SIZE 0x60
+
+#define OMAP_ABE_S_ECHOREF_R_ADDR 0x17B0
+#define OMAP_ABE_S_ECHOREF_R_SIZE 0x60
+
+#define OMAP_ABE_S_MM_DL_L_ADDR 0x1810
+#define OMAP_ABE_S_MM_DL_L_SIZE 0x60
+
+#define OMAP_ABE_S_MM_DL_R_ADDR 0x1870
+#define OMAP_ABE_S_MM_DL_R_SIZE 0x60
+
+#define OMAP_ABE_S_MM_UL_ADDR 0x18D0
+#define OMAP_ABE_S_MM_UL_SIZE 0x3C0
+
+#define OMAP_ABE_S_AMIC_96K_ADDR 0x1C90
+#define OMAP_ABE_S_AMIC_96K_SIZE 0xC0
+
+#define OMAP_ABE_S_DMIC0_96K_ADDR 0x1D50
+#define OMAP_ABE_S_DMIC0_96K_SIZE 0xC0
+
+#define OMAP_ABE_S_DMIC1_96K_ADDR 0x1E10
+#define OMAP_ABE_S_DMIC1_96K_SIZE 0xC0
+
+#define OMAP_ABE_S_DMIC2_96K_ADDR 0x1ED0
+#define OMAP_ABE_S_DMIC2_96K_SIZE 0xC0
+
+#define OMAP_ABE_S_UL_VX_UL_48_8K_ADDR 0x1F90
+#define OMAP_ABE_S_UL_VX_UL_48_8K_SIZE 0x60
+
+#define OMAP_ABE_S_UL_VX_UL_48_16K_ADDR 0x1FF0
+#define OMAP_ABE_S_UL_VX_UL_48_16K_SIZE 0x60
+
+#define OMAP_ABE_S_UL_MIC_48K_ADDR 0x2050
+#define OMAP_ABE_S_UL_MIC_48K_SIZE 0x60
+
+#define OMAP_ABE_S_VOICE_8K_UL_ADDR 0x20B0
+#define OMAP_ABE_S_VOICE_8K_UL_SIZE 0x18
+
+#define OMAP_ABE_S_VOICE_8K_DL_ADDR 0x20C8
+#define OMAP_ABE_S_VOICE_8K_DL_SIZE 0x10
+
+#define OMAP_ABE_S_MCPDM_OUT1_ADDR 0x20D8
+#define OMAP_ABE_S_MCPDM_OUT1_SIZE 0xC0
+
+#define OMAP_ABE_S_MCPDM_OUT2_ADDR 0x2198
+#define OMAP_ABE_S_MCPDM_OUT2_SIZE 0xC0
+
+#define OMAP_ABE_S_MCPDM_OUT3_ADDR 0x2258
+#define OMAP_ABE_S_MCPDM_OUT3_SIZE 0xC0
+
+#define OMAP_ABE_S_VOICE_16K_UL_ADDR 0x2318
+#define OMAP_ABE_S_VOICE_16K_UL_SIZE 0x28
+
+#define OMAP_ABE_S_VOICE_16K_DL_ADDR 0x2340
+#define OMAP_ABE_S_VOICE_16K_DL_SIZE 0x20
+
+#define OMAP_ABE_S_XINASRC_DL_VX_ADDR 0x2360
+#define OMAP_ABE_S_XINASRC_DL_VX_SIZE 0x140
+
+#define OMAP_ABE_S_XINASRC_UL_VX_ADDR 0x24A0
+#define OMAP_ABE_S_XINASRC_UL_VX_SIZE 0x140
+
+#define OMAP_ABE_S_XINASRC_MM_EXT_IN_ADDR 0x25E0
+#define OMAP_ABE_S_XINASRC_MM_EXT_IN_SIZE 0x140
+
+#define OMAP_ABE_S_VX_REC_ADDR 0x2720
+#define OMAP_ABE_S_VX_REC_SIZE 0x60
+
+#define OMAP_ABE_S_VX_REC_L_ADDR 0x2780
+#define OMAP_ABE_S_VX_REC_L_SIZE 0x60
+
+#define OMAP_ABE_S_VX_REC_R_ADDR 0x27E0
+#define OMAP_ABE_S_VX_REC_R_SIZE 0x60
+
+#define OMAP_ABE_S_DL2_M_L_ADDR 0x2840
+#define OMAP_ABE_S_DL2_M_L_SIZE 0x60
+
+#define OMAP_ABE_S_DL2_M_R_ADDR 0x28A0
+#define OMAP_ABE_S_DL2_M_R_SIZE 0x60
+
+#define OMAP_ABE_S_DL2_M_LR_EQ_DATA_ADDR 0x2900
+#define OMAP_ABE_S_DL2_M_LR_EQ_DATA_SIZE 0xC8
+
+#define OMAP_ABE_S_DL1_M_EQ_DATA_ADDR 0x29C8
+#define OMAP_ABE_S_DL1_M_EQ_DATA_SIZE 0xC8
+
+#define OMAP_ABE_S_EARP_48_96_LP_DATA_ADDR 0x2A90
+#define OMAP_ABE_S_EARP_48_96_LP_DATA_SIZE 0x78
+
+#define OMAP_ABE_S_IHF_48_96_LP_DATA_ADDR 0x2B08
+#define OMAP_ABE_S_IHF_48_96_LP_DATA_SIZE 0x78
+
+#define OMAP_ABE_S_VX_UL_8_TEMP_ADDR 0x2B80
+#define OMAP_ABE_S_VX_UL_8_TEMP_SIZE 0x10
+
+#define OMAP_ABE_S_VX_UL_16_TEMP_ADDR 0x2B90
+#define OMAP_ABE_S_VX_UL_16_TEMP_SIZE 0x20
+
+#define OMAP_ABE_S_VX_DL_8_48_LP_DATA_ADDR 0x2BB0
+#define OMAP_ABE_S_VX_DL_8_48_LP_DATA_SIZE 0x58
+
+#define OMAP_ABE_S_VX_DL_8_48_HP_DATA_ADDR 0x2C08
+#define OMAP_ABE_S_VX_DL_8_48_HP_DATA_SIZE 0x38
+
+#define OMAP_ABE_S_VX_DL_16_48_LP_DATA_ADDR 0x2C40
+#define OMAP_ABE_S_VX_DL_16_48_LP_DATA_SIZE 0x58
+
+#define OMAP_ABE_S_VX_DL_16_48_HP_DATA_ADDR 0x2C98
+#define OMAP_ABE_S_VX_DL_16_48_HP_DATA_SIZE 0x28
+
+#define OMAP_ABE_S_VX_UL_48_8_LP_DATA_ADDR 0x2CC0
+#define OMAP_ABE_S_VX_UL_48_8_LP_DATA_SIZE 0x58
+
+#define OMAP_ABE_S_VX_UL_48_8_HP_DATA_ADDR 0x2D18
+#define OMAP_ABE_S_VX_UL_48_8_HP_DATA_SIZE 0x38
+
+#define OMAP_ABE_S_VX_UL_48_16_LP_DATA_ADDR 0x2D50
+#define OMAP_ABE_S_VX_UL_48_16_LP_DATA_SIZE 0x58
+
+#define OMAP_ABE_S_VX_UL_48_16_HP_DATA_ADDR 0x2DA8
+#define OMAP_ABE_S_VX_UL_48_16_HP_DATA_SIZE 0x38
+
+#define OMAP_ABE_S_BT_UL_8_48_LP_DATA_ADDR 0x2DE0
+#define OMAP_ABE_S_BT_UL_8_48_LP_DATA_SIZE 0x58
+
+#define OMAP_ABE_S_BT_UL_8_48_HP_DATA_ADDR 0x2E38
+#define OMAP_ABE_S_BT_UL_8_48_HP_DATA_SIZE 0x38
+
+#define OMAP_ABE_S_BT_UL_16_48_LP_DATA_ADDR 0x2E70
+#define OMAP_ABE_S_BT_UL_16_48_LP_DATA_SIZE 0x58
+
+#define OMAP_ABE_S_BT_UL_16_48_HP_DATA_ADDR 0x2EC8
+#define OMAP_ABE_S_BT_UL_16_48_HP_DATA_SIZE 0x28
+
+#define OMAP_ABE_S_BT_DL_48_8_LP_DATA_ADDR 0x2EF0
+#define OMAP_ABE_S_BT_DL_48_8_LP_DATA_SIZE 0x58
+
+#define OMAP_ABE_S_BT_DL_48_8_HP_DATA_ADDR 0x2F48
+#define OMAP_ABE_S_BT_DL_48_8_HP_DATA_SIZE 0x38
+
+#define OMAP_ABE_S_BT_DL_48_16_LP_DATA_ADDR 0x2F80
+#define OMAP_ABE_S_BT_DL_48_16_LP_DATA_SIZE 0x58
+
+#define OMAP_ABE_S_BT_DL_48_16_HP_DATA_ADDR 0x2FD8
+#define OMAP_ABE_S_BT_DL_48_16_HP_DATA_SIZE 0x28
+
+#define OMAP_ABE_S_ECHO_REF_48_8_LP_DATA_ADDR 0x3000
+#define OMAP_ABE_S_ECHO_REF_48_8_LP_DATA_SIZE 0x58
+
+#define OMAP_ABE_S_ECHO_REF_48_8_HP_DATA_ADDR 0x3058
+#define OMAP_ABE_S_ECHO_REF_48_8_HP_DATA_SIZE 0x38
+
+#define OMAP_ABE_S_ECHO_REF_48_16_LP_DATA_ADDR 0x3090
+#define OMAP_ABE_S_ECHO_REF_48_16_LP_DATA_SIZE 0x58
+
+#define OMAP_ABE_S_ECHO_REF_48_16_HP_DATA_ADDR 0x30E8
+#define OMAP_ABE_S_ECHO_REF_48_16_HP_DATA_SIZE 0x28
+
+#define OMAP_ABE_S_APS_IIRMEM1_ADDR 0x3110
+#define OMAP_ABE_S_APS_IIRMEM1_SIZE 0x48
+
+#define OMAP_ABE_S_APS_M_IIRMEM2_ADDR 0x3158
+#define OMAP_ABE_S_APS_M_IIRMEM2_SIZE 0x18
+
+#define OMAP_ABE_S_APS_C_IIRMEM2_ADDR 0x3170
+#define OMAP_ABE_S_APS_C_IIRMEM2_SIZE 0x18
+
+#define OMAP_ABE_S_APS_DL1_OUTSAMPLES_ADDR 0x3188
+#define OMAP_ABE_S_APS_DL1_OUTSAMPLES_SIZE 0x10
+
+#define OMAP_ABE_S_APS_DL1_COIL_OUTSAMPLES_ADDR 0x3198
+#define OMAP_ABE_S_APS_DL1_COIL_OUTSAMPLES_SIZE 0x10
+
+#define OMAP_ABE_S_APS_DL2_L_OUTSAMPLES_ADDR 0x31A8
+#define OMAP_ABE_S_APS_DL2_L_OUTSAMPLES_SIZE 0x10
+
+#define OMAP_ABE_S_APS_DL2_L_COIL_OUTSAMPLES_ADDR 0x31B8
+#define OMAP_ABE_S_APS_DL2_L_COIL_OUTSAMPLES_SIZE 0x10
+
+#define OMAP_ABE_S_APS_DL2_R_OUTSAMPLES_ADDR 0x31C8
+#define OMAP_ABE_S_APS_DL2_R_OUTSAMPLES_SIZE 0x10
+
+#define OMAP_ABE_S_APS_DL2_R_COIL_OUTSAMPLES_ADDR 0x31D8
+#define OMAP_ABE_S_APS_DL2_R_COIL_OUTSAMPLES_SIZE 0x10
+
+#define OMAP_ABE_S_XINASRC_ECHO_REF_ADDR 0x31E8
+#define OMAP_ABE_S_XINASRC_ECHO_REF_SIZE 0x140
+
+#define OMAP_ABE_S_ECHO_REF_16K_ADDR 0x3328
+#define OMAP_ABE_S_ECHO_REF_16K_SIZE 0x28
+
+#define OMAP_ABE_S_ECHO_REF_8K_ADDR 0x3350
+#define OMAP_ABE_S_ECHO_REF_8K_SIZE 0x18
+
+#define OMAP_ABE_S_DL1_EQ_ADDR 0x3368
+#define OMAP_ABE_S_DL1_EQ_SIZE 0x60
+
+#define OMAP_ABE_S_DL2_EQ_ADDR 0x33C8
+#define OMAP_ABE_S_DL2_EQ_SIZE 0x60
+
+#define OMAP_ABE_S_DL1_GAIN_OUT_ADDR 0x3428
+#define OMAP_ABE_S_DL1_GAIN_OUT_SIZE 0x60
+
+#define OMAP_ABE_S_DL2_GAIN_OUT_ADDR 0x3488
+#define OMAP_ABE_S_DL2_GAIN_OUT_SIZE 0x60
+
+#define OMAP_ABE_S_APS_DL2_L_IIRMEM1_ADDR 0x34E8
+#define OMAP_ABE_S_APS_DL2_L_IIRMEM1_SIZE 0x48
+
+#define OMAP_ABE_S_APS_DL2_R_IIRMEM1_ADDR 0x3530
+#define OMAP_ABE_S_APS_DL2_R_IIRMEM1_SIZE 0x48
+
+#define OMAP_ABE_S_APS_DL2_L_M_IIRMEM2_ADDR 0x3578
+#define OMAP_ABE_S_APS_DL2_L_M_IIRMEM2_SIZE 0x18
+
+#define OMAP_ABE_S_APS_DL2_R_M_IIRMEM2_ADDR 0x3590
+#define OMAP_ABE_S_APS_DL2_R_M_IIRMEM2_SIZE 0x18
+
+#define OMAP_ABE_S_APS_DL2_L_C_IIRMEM2_ADDR 0x35A8
+#define OMAP_ABE_S_APS_DL2_L_C_IIRMEM2_SIZE 0x18
+
+#define OMAP_ABE_S_APS_DL2_R_C_IIRMEM2_ADDR 0x35C0
+#define OMAP_ABE_S_APS_DL2_R_C_IIRMEM2_SIZE 0x18
+
+#define OMAP_ABE_S_DL1_APS_ADDR 0x35D8
+#define OMAP_ABE_S_DL1_APS_SIZE 0x60
+
+#define OMAP_ABE_S_DL2_L_APS_ADDR 0x3638
+#define OMAP_ABE_S_DL2_L_APS_SIZE 0x60
+
+#define OMAP_ABE_S_DL2_R_APS_ADDR 0x3698
+#define OMAP_ABE_S_DL2_R_APS_SIZE 0x60
+
+#define OMAP_ABE_S_APS_DL1_EQ_DATA_ADDR 0x36F8
+#define OMAP_ABE_S_APS_DL1_EQ_DATA_SIZE 0x48
+
+#define OMAP_ABE_S_APS_DL2_EQ_DATA_ADDR 0x3740
+#define OMAP_ABE_S_APS_DL2_EQ_DATA_SIZE 0x48
+
+#define OMAP_ABE_S_DC_DCVALUE_ADDR 0x3788
+#define OMAP_ABE_S_DC_DCVALUE_SIZE 0x8
+
+#define OMAP_ABE_S_VIBRA_ADDR 0x3790
+#define OMAP_ABE_S_VIBRA_SIZE 0x30
+
+#define OMAP_ABE_S_VIBRA2_IN_ADDR 0x37C0
+#define OMAP_ABE_S_VIBRA2_IN_SIZE 0x30
+
+#define OMAP_ABE_S_VIBRA2_ADDR_ADDR 0x37F0
+#define OMAP_ABE_S_VIBRA2_ADDR_SIZE 0x8
+
+#define OMAP_ABE_S_VIBRACTRL_FORRIGHTSM_ADDR 0x37F8
+#define OMAP_ABE_S_VIBRACTRL_FORRIGHTSM_SIZE 0xC0
+
+#define OMAP_ABE_S_RNOISE_MEM_ADDR 0x38B8
+#define OMAP_ABE_S_RNOISE_MEM_SIZE 0x8
+
+#define OMAP_ABE_S_CTRL_ADDR 0x38C0
+#define OMAP_ABE_S_CTRL_SIZE 0x90
+
+#define OMAP_ABE_S_VIBRA1_IN_ADDR 0x3950
+#define OMAP_ABE_S_VIBRA1_IN_SIZE 0x30
+
+#define OMAP_ABE_S_VIBRA1_TEMP_ADDR 0x3980
+#define OMAP_ABE_S_VIBRA1_TEMP_SIZE 0xC0
+
+#define OMAP_ABE_S_VIBRACTRL_FORLEFTSM_ADDR 0x3A40
+#define OMAP_ABE_S_VIBRACTRL_FORLEFTSM_SIZE 0xC0
+
+#define OMAP_ABE_S_VIBRA1_MEM_ADDR 0x3B00
+#define OMAP_ABE_S_VIBRA1_MEM_SIZE 0x58
+
+#define OMAP_ABE_S_VIBRACTRL_STEREO_ADDR 0x3B58
+#define OMAP_ABE_S_VIBRACTRL_STEREO_SIZE 0xC0
+
+#define OMAP_ABE_S_AMIC_96_48_DATA_ADDR 0x3C18
+#define OMAP_ABE_S_AMIC_96_48_DATA_SIZE 0x98
+
+#define OMAP_ABE_S_DMIC0_96_48_DATA_ADDR 0x3CB0
+#define OMAP_ABE_S_DMIC0_96_48_DATA_SIZE 0x98
+
+#define OMAP_ABE_S_DMIC1_96_48_DATA_ADDR 0x3D48
+#define OMAP_ABE_S_DMIC1_96_48_DATA_SIZE 0x98
+
+#define OMAP_ABE_S_DMIC2_96_48_DATA_ADDR 0x3DE0
+#define OMAP_ABE_S_DMIC2_96_48_DATA_SIZE 0x98
+
+#define OMAP_ABE_S_DBG_8K_PATTERN_ADDR 0x3E78
+#define OMAP_ABE_S_DBG_8K_PATTERN_SIZE 0x10
+
+#define OMAP_ABE_S_DBG_16K_PATTERN_ADDR 0x3E88
+#define OMAP_ABE_S_DBG_16K_PATTERN_SIZE 0x20
+
+#define OMAP_ABE_S_DBG_24K_PATTERN_ADDR 0x3EA8
+#define OMAP_ABE_S_DBG_24K_PATTERN_SIZE 0x30
+
+#define OMAP_ABE_S_DBG_48K_PATTERN_ADDR 0x3ED8
+#define OMAP_ABE_S_DBG_48K_PATTERN_SIZE 0x60
+
+#define OMAP_ABE_S_DBG_96K_PATTERN_ADDR 0x3F38
+#define OMAP_ABE_S_DBG_96K_PATTERN_SIZE 0xC0
+
+#define OMAP_ABE_S_MM_EXT_IN_ADDR 0x3FF8
+#define OMAP_ABE_S_MM_EXT_IN_SIZE 0x60
+
+#define OMAP_ABE_S_MM_EXT_IN_L_ADDR 0x4058
+#define OMAP_ABE_S_MM_EXT_IN_L_SIZE 0x60
+
+#define OMAP_ABE_S_MM_EXT_IN_R_ADDR 0x40B8
+#define OMAP_ABE_S_MM_EXT_IN_R_SIZE 0x60
+
+#define OMAP_ABE_S_MIC4_ADDR 0x4118
+#define OMAP_ABE_S_MIC4_SIZE 0x60
+
+#define OMAP_ABE_S_MIC4_L_ADDR 0x4178
+#define OMAP_ABE_S_MIC4_L_SIZE 0x60
+
+#define OMAP_ABE_S_MIC4_R_ADDR 0x41D8
+#define OMAP_ABE_S_MIC4_R_SIZE 0x60
+
+#define OMAP_ABE_S_HW_TEST_ADDR 0x4238
+#define OMAP_ABE_S_HW_TEST_SIZE 0x8
+
+#define OMAP_ABE_S_XINASRC_BT_UL_ADDR 0x4240
+#define OMAP_ABE_S_XINASRC_BT_UL_SIZE 0x140
+
+#define OMAP_ABE_S_XINASRC_BT_DL_ADDR 0x4380
+#define OMAP_ABE_S_XINASRC_BT_DL_SIZE 0x140
+
+#define OMAP_ABE_S_BT_DL_8K_TEMP_ADDR 0x44C0
+#define OMAP_ABE_S_BT_DL_8K_TEMP_SIZE 0x10
+
+#define OMAP_ABE_S_BT_DL_16K_TEMP_ADDR 0x44D0
+#define OMAP_ABE_S_BT_DL_16K_TEMP_SIZE 0x20
diff --git a/sound/soc/omap/abe/abe_taskid.h b/sound/soc/omap/abe/abe_taskid.h
new file mode 100644
index 0000000..f55caba
--- /dev/null
+++ b/sound/soc/omap/abe/abe_taskid.h
@@ -0,0 +1,188 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_TASKID_H_
+#define _ABE_TASKID_H_
+
+#define C_ABE_FW_TASK_DL1_APS_CORE 0
+#define C_ABE_FW_TASK_DL1_APS_COIL_CORE 1
+#define C_ABE_FW_TASK_DL2_L_APS_CORE 2
+#define C_ABE_FW_TASK_DL2_L_APS_COIL_CORE 3
+#define C_ABE_FW_TASK_DL2_R_APS_CORE 4
+#define C_ABE_FW_TASK_DL2_R_APS_COIL_CORE 5
+#define C_ABE_FW_TASK_ASRC_VX_DL_8 6
+#define C_ABE_FW_TASK_ASRC_VX_DL_16 7
+#define C_ABE_FW_TASK_ASRC_MM_EXT_IN 8
+#define C_ABE_FW_TASK_ASRC_VX_UL_8 9
+#define C_ABE_FW_TASK_ASRC_VX_UL_16 10
+#define C_ABE_FW_TASK_VX_UL_48_8_DEC 11
+#define C_ABE_FW_TASK_VX_UL_48_16_DEC 12
+#define C_ABE_FW_TASK_BT_DL_48_8_DEC 13
+#define C_ABE_FW_TASK_BT_DL_48_16_DEC 14
+#define C_ABE_FW_TASK_ECHO_REF_48_8_DEC 15
+#define C_ABE_FW_TASK_ECHO_REF_48_16_DEC 16
+#define C_ABE_FW_TASK_DL2_EQ 17
+#define C_ABE_FW_TASK_DL2_L_APS_IIR 18
+#define C_ABE_FW_TASK_DL2_R_APS_IIR 19
+#define C_ABE_FW_TASK_DL2_APS_EQ 20
+#define C_ABE_FW_TASK_ECHO_REF_48_16 21
+#define C_ABE_FW_TASK_ECHO_REF_48_8 22
+#define C_ABE_FW_TASK_GAIN_UPDATE 23
+#define C_ABE_FW_TASK_SideTone 24
+#define C_ABE_FW_TASK_VX_DL_8_48_LP 25
+#define C_ABE_FW_TASK_VX_DL_8_48_HP 26
+#define C_ABE_FW_TASK_VX_DL_16_48_LP 27
+#define C_ABE_FW_TASK_VX_DL_16_48_HP 28
+#define C_ABE_FW_TASK_VX_UL_48_8_LP 29
+#define C_ABE_FW_TASK_VX_UL_48_8_HP 30
+#define C_ABE_FW_TASK_VX_UL_48_16_LP 31
+#define C_ABE_FW_TASK_VX_UL_48_16_HP 32
+#define C_ABE_FW_TASK_BT_UL_8_48_LP 33
+#define C_ABE_FW_TASK_BT_UL_8_48_HP 34
+#define C_ABE_FW_TASK_BT_UL_16_48_LP 35
+#define C_ABE_FW_TASK_BT_UL_16_48_HP 36
+#define C_ABE_FW_TASK_BT_DL_48_8_LP 37
+#define C_ABE_FW_TASK_BT_DL_48_8_HP 38
+#define C_ABE_FW_TASK_BT_DL_48_16_LP 39
+#define C_ABE_FW_TASK_BT_DL_48_16_HP 40
+#define C_ABE_FW_TASK_ECHO_REF_48_8_LP 41
+#define C_ABE_FW_TASK_ECHO_REF_48_8_HP 42
+#define C_ABE_FW_TASK_ECHO_REF_48_16_LP 43
+#define C_ABE_FW_TASK_ECHO_REF_48_16_HP 44
+#define C_ABE_FW_TASK_DL1_EQ 45
+#define C_ABE_FW_TASK_DL1_APS_IIR 46
+#define C_ABE_FW_TASK_DL1_APS_EQ 47
+#define C_ABE_FW_TASK_IHF_48_96_LP 48
+#define C_ABE_FW_TASK_EARP_48_96_LP 49
+#define C_ABE_FW_TASK_DL1_GAIN 50
+#define C_ABE_FW_TASK_DL2_GAIN 51
+#define C_ABE_FW_TASK_IO_PING_PONG 52
+#define C_ABE_FW_TASK_IO_DMIC 53
+#define C_ABE_FW_TASK_IO_PDM_UL 54
+#define C_ABE_FW_TASK_IO_BT_VX_UL 55
+#define C_ABE_FW_TASK_IO_MM_UL 56
+#define C_ABE_FW_TASK_IO_MM_UL2 57
+#define C_ABE_FW_TASK_IO_VX_UL 58
+#define C_ABE_FW_TASK_IO_MM_DL 59
+#define C_ABE_FW_TASK_IO_VX_DL 60
+#define C_ABE_FW_TASK_IO_TONES_DL 61
+#define C_ABE_FW_TASK_IO_VIB_DL 62
+#define C_ABE_FW_TASK_IO_BT_VX_DL 63
+#define C_ABE_FW_TASK_IO_PDM_DL 64
+#define C_ABE_FW_TASK_IO_MM_EXT_OUT 65
+#define C_ABE_FW_TASK_IO_MM_EXT_IN 66
+#define C_ABE_FW_TASK_IO_TDM_OUT 67
+#define C_ABE_FW_TASK_IO_TDM_IN 68
+#define C_ABE_FW_TASK_DEBUG_IRQFIFO 69
+#define C_ABE_FW_TASK_EchoMixer 70
+#define C_ABE_FW_TASK_SDTMixer 71
+#define C_ABE_FW_TASK_DL1Mixer 72
+#define C_ABE_FW_TASK_DL2Mixer 73
+#define C_ABE_FW_TASK_VXRECMixer 74
+#define C_ABE_FW_TASK_ULMixer 75
+#define C_ABE_FW_TASK_VIBRA_PACK 76
+#define C_ABE_FW_TASK_VX_DL_8_48_0SR 77
+#define C_ABE_FW_TASK_VX_DL_16_48_0SR 78
+#define C_ABE_FW_TASK_BT_UL_8_48_0SR 79
+#define C_ABE_FW_TASK_BT_UL_16_48_0SR 80
+#define C_ABE_FW_TASK_IHF_48_96_0SR 81
+#define C_ABE_FW_TASK_EARP_48_96_0SR 82
+#define C_ABE_FW_TASK_AMIC_SPLIT 83
+#define C_ABE_FW_TASK_DMIC1_SPLIT 84
+#define C_ABE_FW_TASK_DMIC2_SPLIT 85
+#define C_ABE_FW_TASK_DMIC3_SPLIT 86
+#define C_ABE_FW_TASK_VXREC_SPLIT 87
+#define C_ABE_FW_TASK_BT_UL_SPLIT 88
+#define C_ABE_FW_TASK_MM_SPLIT 89
+#define C_ABE_FW_TASK_DL2_APS_SPLIT 90
+#define C_ABE_FW_TASK_VIBRA_SPLIT 91
+#define C_ABE_FW_TASK_MM_EXT_IN_SPLIT 92
+#define C_ABE_FW_TASK_ECHO_REF_SPLIT 93
+#define C_ABE_FW_TASK_MIC4_SPLIT 94
+#define C_ABE_FW_TASK_VX_UL_ROUTING 95
+#define C_ABE_FW_TASK_MM_UL2_ROUTING 96
+#define C_ABE_FW_TASK_VIBRA1 97
+#define C_ABE_FW_TASK_VIBRA2 98
+#define C_ABE_FW_TASK_BT_UL_16_48 99
+#define C_ABE_FW_TASK_BT_UL_8_48 100
+#define C_ABE_FW_TASK_BT_DL_48_16 101
+#define C_ABE_FW_TASK_BT_DL_48_8 102
+#define C_ABE_FW_TASK_VX_DL_16_48 103
+#define C_ABE_FW_TASK_VX_DL_8_48 104
+#define C_ABE_FW_TASK_VX_UL_48_16 105
+#define C_ABE_FW_TASK_VX_UL_48_8 106
+#define C_ABE_FW_TASK_DBG_SYNC 107
+#define C_ABE_FW_TASK_APS_DL1_IRQs 108
+#define C_ABE_FW_TASK_APS_DL2_L_IRQs 109
+#define C_ABE_FW_TASK_APS_DL2_R_IRQs 110
+#define C_ABE_FW_TASK_AMIC_96_48_LP 111
+#define C_ABE_FW_TASK_DMIC1_96_48_LP 112
+#define C_ABE_FW_TASK_DMIC2_96_48_LP 113
+#define C_ABE_FW_TASK_DMIC3_96_48_LP 114
+#define C_ABE_FW_TASK_INIT_FW_MEMORY 115
+#define C_ABE_FW_TASK_DEBUGTRACE_VX_ASRCs 116
+#define C_ABE_FW_TASK_ASRC_BT_UL_8 117
+#define C_ABE_FW_TASK_ASRC_BT_UL_16 118
+#define C_ABE_FW_TASK_ASRC_BT_DL_8 119
+#define C_ABE_FW_TASK_ASRC_BT_DL_16 120
+#define C_ABE_FW_TASK_BT_DL_48_8_HP_OPP100 121
+#define C_ABE_FW_TASK_BT_DL_48_16_HP_OPP100 122
+#define C_ABE_FW_TASK_BT_DL_48_8_OPP100 123
+#define C_ABE_FW_TASK_BT_DL_48_16_OPP100 124
+
+#endif /* _ABE_TASKID_H_ */
diff --git a/sound/soc/omap/abe/abe_typ.h b/sound/soc/omap/abe/abe_typ.h
new file mode 100644
index 0000000..650d043
--- /dev/null
+++ b/sound/soc/omap/abe/abe_typ.h
@@ -0,0 +1,654 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#include "abe_def.h"
+#include "abe_initxxx_labels.h"
+
+#ifndef _ABE_TYP_H_
+#define _ABE_TYP_H_
+/*
+ * BASIC TYPES
+ */
+#define MAX_UINT8 ((((1L << 7) - 1) << 1) + 1)
+#define MAX_UINT16 ((((1L << 15) - 1) << 1) + 1)
+#define MAX_UINT32 ((((1L << 31) - 1) << 1) + 1)
+#define s8 char
+#define u8 unsigned char
+#define s16 short
+#define u16 unsigned short
+#define s32 int
+#define u32 unsigned int
+/* returned status from HAL APIs */
+#define abehal_status u32
+/* 4 bytes Bit field indicating the type of informations to be traced */
+typedef u32 abe_dbg_mask_t;
+/* scheduling task loops (250us / 272us with respectively 48kHz /
+ 44.1kHz on Phoenix). */
+typedef u32 abe_dbg_t;
+/* Index to the table of sequences */
+typedef u32 abe_seq_code_t;
+/* Index to the table of subroutines called in the sequence */
+typedef u32 abe_sub_code_t;
+/* subroutine with no parameter */
+typedef void (*abe_subroutine0) (void);
+/* subroutine with one parameter */
+typedef void (*abe_subroutine1) (u32);
+typedef void (*abe_subroutine2) (u32, u32);
+typedef void (*abe_subroutine3) (u32, u32, u32);
+typedef void (*abe_subroutine4) (u32, u32, u32, u32);
+/*
+ * CODE PORTABILITY - FUTURE PATCHES
+ *
+ * 32bits field for having the code compatible with future revisions of
+ * the hardware (audio integration) or evolution of the software
+ * partitionning. Used for the highest level APIs (launch_sequences)
+ */
+typedef u32 abe_patch_rev;
+/*
+ * ENUMS
+ */
+/*
+ * MEMORY CONFIG TYPE
+ *
+ * 0: Ultra Lowest power consumption audio player
+ * 1: OPP 25% (simple multimedia features)
+ * 2: OPP 50% (multimedia and voice calls)
+ * 3: OPP100% (multimedia complex use-cases)
+ */
+#define ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE 1
+#define ABE_DRIFT_MANAGEMENT_FOR_AUDIO_PLAYER 2
+#define ABE_DRIFT_MANAGEMENT_FOR_VOICE_CALL 3
+#define ABE_VOICE_CALL_ON_HEADSET_OR_EARPHONE_OR_BT 4
+#define ABE_MULTIMEDIA_AUDIO_RECORDER 5
+#define ABE_VIBRATOR_OR_HAPTICS 6
+#define ABE_VOICE_CALL_ON_HANDS_FREE_SPEAKER 7
+#define ABE_RINGER_TONES 8
+#define ABE_VOICE_CALL_WITH_EARPHONE_ACTIVE_NOISE_CANCELLER 9
+#define ABE_LAST_USE_CASE 10
+/*
+ * OPP TYPE
+ *
+ * 0: Ultra Lowest power consumption audio player
+ * 1: OPP 25% (simple multimedia features)
+ * 2: OPP 50% (multimedia and voice calls)
+ * 3: OPP100% (multimedia complex use-cases)
+ */
+#define ABE_OPP0 0
+#define ABE_OPP25 1
+#define ABE_OPP50 2
+#define ABE_OPP100 3
+/*
+ * DMIC DECIMATION RATIO
+ *
+ */
+#define ABE_DEC16 16
+#define ABE_DEC25 25
+#define ABE_DEC32 32
+#define ABE_DEC40 40
+/*
+ * SAMPLES TYPE
+ *
+ * mono 16 bit sample LSB aligned, 16 MSB bits are unused;
+ * mono right shifted to 16bits LSBs on a 32bits DMEM FIFO for McBSP
+ * TX purpose;
+ * mono sample MSB aligned (16/24/32bits);
+ * two successive mono samples in one 32bits container;
+ * Two L/R 16bits samples in a 32bits container;
+ * Two channels defined with two MSB aligned samples;
+ * Three channels defined with three MSB aligned samples (MIC);
+ * Four channels defined with four MSB aligned samples (MIC);
+ * . . .
+ * Eight channels defined with eight MSB aligned samples (MIC);
+ */
+#define MONO_MSB 1
+#define MONO_RSHIFTED_16 2
+#define STEREO_RSHIFTED_16 3
+#define STEREO_16_16 4
+#define STEREO_MSB 5
+#define THREE_MSB 6
+#define FOUR_MSB 7
+#define FIVE_MSB 8
+#define SIX_MSB 9
+#define SEVEN_MSB 10
+#define EIGHT_MSB 11
+#define NINE_MSB 12
+#define TEN_MSB 13
+/*
+ * PORT PROTOCOL TYPE - abe_port_protocol_switch_id
+ */
+#define SLIMBUS_PORT_PROT 1
+#define SERIAL_PORT_PROT 2
+#define TDM_SERIAL_PORT_PROT 3
+#define DMIC_PORT_PROT 4
+#define MCPDMDL_PORT_PROT 5
+#define MCPDMUL_PORT_PROT 6
+#define PINGPONG_PORT_PROT 7
+#define DMAREQ_PORT_PROT 8
+/*
+ * PORT IDs, this list is aligned with the FW data mapping
+ */
+#define OMAP_ABE_DMIC_PORT 0
+#define OMAP_ABE_PDM_UL_PORT 1
+#define OMAP_ABE_BT_VX_UL_PORT 2
+#define OMAP_ABE_MM_UL_PORT 3
+#define OMAP_ABE_MM_UL2_PORT 4
+#define OMAP_ABE_VX_UL_PORT 5
+#define OMAP_ABE_MM_DL_PORT 6
+#define OMAP_ABE_VX_DL_PORT 7
+#define OMAP_ABE_TONES_DL_PORT 8
+#define OMAP_ABE_VIB_DL_PORT 9
+#define OMAP_ABE_BT_VX_DL_PORT 10
+#define OMAP_ABE_PDM_DL_PORT 11
+#define OMAP_ABE_MM_EXT_OUT_PORT 12
+#define OMAP_ABE_MM_EXT_IN_PORT 13
+#define TDM_DL_PORT 14
+#define TDM_UL_PORT 15
+#define DEBUG_PORT 16
+#define LAST_PORT_ID 17
+/* definitions for the compatibility with HAL05xx */
+#define PDM_DL1_PORT 18
+#define PDM_DL2_PORT 19
+#define PDM_VIB_PORT 20
+/* There is only one DMIC port, always used with 6 samples
+ per 96kHz periods */
+#define DMIC_PORT1 DMIC_PORT
+#define DMIC_PORT2 DMIC_PORT
+#define DMIC_PORT3 DMIC_PORT
+/*
+ * ABE_DL_SRC_ID source of samples
+ */
+#define SRC_DL1_MIXER_OUTPUT DL1_M_labelID
+#define SRC_SDT_MIXER_OUTPUT SDT_M_labelID
+#define SRC_DL1_GAIN_OUTPUT DL1_GAIN_out_labelID
+#define SRC_DL1_EQ_OUTPUT DL1_EQ_labelID
+#define SRC_DL2_GAIN_OUTPUT DL2_GAIN_out_labelID
+#define SRC_DL2_EQ_OUTPUT DL2_EQ_labelID
+#define SRC_MM_DL MM_DL_labelID
+#define SRC_TONES_DL Tones_labelID
+#define SRC_VX_DL VX_DL_labelID
+#define SRC_VX_UL VX_UL_labelID
+#define SRC_MM_UL2 MM_UL2_labelID
+#define SRC_MM_UL MM_UL_labelID
+/*
+ * abe_patched_pattern_id
+ * selection of the audio engine signal to
+ * replace by a precomputed pattern
+ */
+#define DBG_PATCH_AMIC 1
+#define DBG_PATCH_DMIC1 2
+#define DBG_PATCH_DMIC2 3
+#define DBG_PATCH_DMIC3 4
+#define DBG_PATCH_VX_REC 5
+#define DBG_PATCH_BT_UL 6
+#define DBG_PATCH_MM_DL 7
+#define DBG_PATCH_DL2_EQ 8
+#define DBG_PATCH_VIBRA 9
+#define DBG_PATCH_MM_EXT_IN 10
+#define DBG_PATCH_EANC_FBK_Out 11
+#define DBG_PATCH_MIC4 12
+#define DBG_PATCH_MM_DL_MIXDL1 13
+#define DBG_PATCH_MM_DL_MIXDL2 14
+/*
+ * Signal processing module names - EQ APS MIX ROUT
+ */
+/* equalizer downlink path headset + earphone */
+#define FEAT_EQ1 1
+/* equalizer downlink path integrated handsfree LEFT */
+#define FEAT_EQ2L (FEAT_EQ1+1)
+/* equalizer downlink path integrated handsfree RIGHT */
+#define FEAT_EQ2R (FEAT_EQ2L+1)
+/* equalizer downlink path side-tone */
+#define FEAT_EQSDT (FEAT_EQ2R+1)
+/* equalizer uplink path AMIC */
+#define FEAT_EQAMIC (FEAT_EQSDT+1)
+/* equalizer uplink path DMIC */
+#define FEAT_EQDMIC (FEAT_EQAMIC+1)
+/* Acoustic protection for headset */
+#define FEAT_APS1 (FEAT_EQDMIC+1)
+/* acoustic protection high-pass filter for handsfree "Left" */
+#define FEAT_APS2 (FEAT_APS1+1)
+/* acoustic protection high-pass filter for handsfree "Right" */
+#define FEAT_APS3 (FEAT_APS2+1)
+/* asynchronous sample-rate-converter for the downlink voice path */
+#define FEAT_ASRC1 (FEAT_APS3+1)
+/* asynchronous sample-rate-converter for the uplink voice path */
+#define FEAT_ASRC2 (FEAT_ASRC1+1)
+/* asynchronous sample-rate-converter for the multimedia player */
+#define FEAT_ASRC3 (FEAT_ASRC2+1)
+/* asynchronous sample-rate-converter for the echo reference */
+#define FEAT_ASRC4 (FEAT_ASRC3+1)
+/* mixer of the headset and earphone path */
+#define FEAT_MIXDL1 (FEAT_ASRC4+1)
+/* mixer of the hands-free path */
+#define FEAT_MIXDL2 (FEAT_MIXDL1+1)
+/* mixer for audio being sent on the voice_ul path */
+#define FEAT_MIXAUDUL (FEAT_MIXDL2+1)
+/* mixer for voice communication recording */
+#define FEAT_MIXVXREC (FEAT_MIXAUDUL+1)
+/* mixer for side-tone */
+#define FEAT_MIXSDT (FEAT_MIXVXREC+1)
+/* mixer for echo reference */
+#define FEAT_MIXECHO (FEAT_MIXSDT+1)
+/* router of the uplink path */
+#define FEAT_UPROUTE (FEAT_MIXECHO+1)
+/* all gains */
+#define FEAT_GAINS (FEAT_UPROUTE+1)
+#define FEAT_GAINS_DMIC1 (FEAT_GAINS+1)
+#define FEAT_GAINS_DMIC2 (FEAT_GAINS_DMIC1+1)
+#define FEAT_GAINS_DMIC3 (FEAT_GAINS_DMIC2+1)
+#define FEAT_GAINS_AMIC (FEAT_GAINS_DMIC3+1)
+#define FEAT_GAINS_SPLIT (FEAT_GAINS_AMIC+1)
+#define FEAT_GAINS_DL1 (FEAT_GAINS_SPLIT+1)
+#define FEAT_GAINS_DL2 (FEAT_GAINS_DL1+1)
+#define FEAT_GAIN_BTUL (FEAT_GAINS_DL2+1)
+/* sequencing queue of micro tasks */
+#define FEAT_SEQ (FEAT_GAIN_BTUL+1)
+/* Phoenix control queue through McPDM */
+#define FEAT_CTL (FEAT_SEQ+1)
+/* list of features of the firmware -------------------------------*/
+#define MAXNBFEATURE FEAT_CTL
+/* abe_equ_id */
+/* equalizer downlink path headset + earphone */
+#define EQ1 FEAT_EQ1
+/* equalizer downlink path integrated handsfree LEFT */
+#define EQ2L FEAT_EQ2L
+#define EQ2R FEAT_EQ2R
+/* equalizer downlink path side-tone */
+#define EQSDT FEAT_EQSDT
+#define EQAMIC FEAT_EQAMIC
+#define EQDMIC FEAT_EQDMIC
+/* abe_aps_id */
+/* Acoustic protection for headset */
+#define APS1 FEAT_APS1
+#define APS2L FEAT_APS2
+#define APS2R FEAT_APS3
+/* abe_asrc_id */
+/* asynchronous sample-rate-converter for the downlink voice path */
+#define ASRC1 FEAT_ASRC1
+/* asynchronous sample-rate-converter for the uplink voice path */
+#define ASRC2 FEAT_ASRC2
+/* asynchronous sample-rate-converter for the multimedia player */
+#define ASRC3 FEAT_ASRC3
+/* asynchronous sample-rate-converter for the voice uplink echo_reference */
+#define ASRC4 FEAT_ASRC4
+/* abe_mixer_id */
+#define MIXDL1 FEAT_MIXDL1
+#define MIXDL2 FEAT_MIXDL2
+#define MIXSDT FEAT_MIXSDT
+#define MIXECHO FEAT_MIXECHO
+#define MIXAUDUL FEAT_MIXAUDUL
+#define MIXVXREC FEAT_MIXVXREC
+/* abe_router_id */
+/* there is only one router up to now */
+#define UPROUTE FEAT_UPROUTE
+/*
+ * GAIN IDs
+ */
+#define GAINS_DMIC1 FEAT_GAINS_DMIC1
+#define GAINS_DMIC2 FEAT_GAINS_DMIC2
+#define GAINS_DMIC3 FEAT_GAINS_DMIC3
+#define GAINS_AMIC FEAT_GAINS_AMIC
+#define GAINS_SPLIT FEAT_GAINS_SPLIT
+#define GAINS_DL1 FEAT_GAINS_DL1
+#define GAINS_DL2 FEAT_GAINS_DL2
+#define GAINS_BTUL FEAT_GAIN_BTUL
+/*
+ * EVENT GENERATORS - abe_event_id
+ */
+#define EVENT_TIMER 0
+#define EVENT_44100 1
+/*
+ * SERIAL PORTS IDs - abe_mcbsp_id
+ */
+#define MCBSP1_TX MCBSP1_DMA_TX
+#define MCBSP1_RX MCBSP1_DMA_RX
+#define MCBSP2_TX MCBSP2_DMA_TX
+#define MCBSP2_RX MCBSP2_DMA_RX
+#define MCBSP3_TX MCBSP3_DMA_TX
+#define MCBSP3_RX MCBSP3_DMA_RX
+/*
+ * SERIAL PORTS IDs - abe_slimbus_id;
+ */
+#define SLIMBUS1_TX0 SLIMBUS1_DMA_TX0
+#define SLIMBUS1_TX1 SLIMBUS1_DMA_TX1
+#define SLIMBUS1_TX2 SLIMBUS1_DMA_TX2
+#define SLIMBUS1_TX3 SLIMBUS1_DMA_TX3
+#define SLIMBUS1_TX4 SLIMBUS1_DMA_TX4
+#define SLIMBUS1_TX5 SLIMBUS1_DMA_TX5
+#define SLIMBUS1_TX6 SLIMBUS1_DMA_TX6
+#define SLIMBUS1_TX7 SLIMBUS1_DMA_TX7
+#define SLIMBUS1_RX0 SLIMBUS1_DMA_RX0
+#define SLIMBUS1_RX1 SLIMBUS1_DMA_RX1
+#define SLIMBUS1_RX2 SLIMBUS1_DMA_RX2
+#define SLIMBUS1_RX3 SLIMBUS1_DMA_RX3
+#define SLIMBUS1_RX4 SLIMBUS1_DMA_RX4
+#define SLIMBUS1_RX5 SLIMBUS1_DMA_RX5
+#define SLIMBUS1_RX6 SLIMBUS1_DMA_RX6
+#define SLIMBUS1_RX7 SLIMBUS1_DMA_RX7
+#define SLIMBUS_UNUSED _DUMMY_FIFO_
+/*
+ * ----------------- TYPES USED FOR APIS ---------------
+ */
+
+/*
+ * EQU_T
+ *
+ * coefficients of the equalizer
+ */
+typedef struct {
+ /* type of filter */
+ u32 equ_type;
+ /* filter length */
+ u32 equ_length;
+ union {
+ /* parameters are the direct and recursive coefficients in */
+ /* Q6.26 integer fixed-point format. */
+ s32 type1[NBEQ1];
+ struct {
+ /* center frequency of the band [Hz] */
+ s32 freq[NBEQ2];
+ /* gain of each band. [dB] */
+ s32 gain[NBEQ2];
+ /* Q factor of this band [dB] */
+ s32 q[NBEQ2];
+ } type2;
+ } coef;
+ s32 equ_param3;
+} abe_equ_t;
+
+/*
+ * APS_T
+ *
+ * coefficients of the Acoustics Protection and Safety
+ */
+struct abe_aps_t {
+ s32 coef1[NBAPS1];
+ s32 coef2[NBAPS2];
+};
+
+struct abe_aps_energy_t {
+ /* structure of two energy_t estimation for coil and membrane */
+ u32 e1;
+ u32 e2;
+};
+/*
+ * ROUTER_T
+ *
+ * table of indexes in unsigned bytes
+ */
+typedef u16 abe_router_t;
+/*
+ * DATA_FORMAT_T
+ *
+ * used in port declaration
+ */
+typedef struct {
+ /* Sampling frequency of the stream */
+ u32 f;
+ /* Sample format type */
+ u32 samp_format;
+} abe_data_format_t;
+/*
+ * PORT_PROTOCOL_T
+ *
+ * port declaration
+ */
+typedef struct {
+ /* Direction=0 means input from AESS point of view */
+ u32 direction;
+ /* Protocol type (switch) during the data transfers */
+ u32 protocol_switch;
+ union {
+ /* Slimbus peripheral connected to ATC */
+ struct {
+ /* Address of ATC Slimbus descriptor's index */
+ u32 desc_addr1;
+ /* DMEM address 1 in bytes */
+ u32 buf_addr1;
+ /* DMEM buffer size size in bytes */
+ u32 buf_size;
+ /* ITERation on each DMAreq signals */
+ u32 iter;
+ /* Second ATC index for SlimBus reception (or NULL) */
+ u32 desc_addr2;
+ /* DMEM address 2 in bytes */
+ u32 buf_addr2;
+ } prot_slimbus;
+ /* McBSP/McASP peripheral connected to ATC */
+ struct {
+ u32 desc_addr;
+ /* Address of ATC McBSP/McASP descriptor's in bytes */
+ u32 buf_addr;
+ /* DMEM address in bytes */
+ u32 buf_size;
+ /* ITERation on each DMAreq signals */
+ u32 iter;
+ } prot_serial;
+ /* DMIC peripheral connected to ATC */
+ struct {
+ /* DMEM address in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size in bytes */
+ u32 buf_size;
+ /* Number of activated DMIC */
+ u32 nbchan;
+ } prot_dmic;
+ /* McPDMDL peripheral connected to ATC */
+ struct {
+ /* DMEM address in bytes */
+ u32 buf_addr;
+ /* DMEM size in bytes */
+ u32 buf_size;
+ /* Control allowed on McPDM DL */
+ u32 control;
+ } prot_mcpdmdl;
+ /* McPDMUL peripheral connected to ATC */
+ struct {
+ /* DMEM address size in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size size in bytes */
+ u32 buf_size;
+ } prot_mcpdmul;
+ /* Ping-Pong interface to the Host using cache-flush */
+ struct {
+ /* Address of ATC descriptor's */
+ u32 desc_addr;
+ /* DMEM buffer base address in bytes */
+ u32 buf_addr;
+ /* DMEM size in bytes for each ping and pong buffers */
+ u32 buf_size;
+ /* IRQ address (either DMA (0) MCU (1) or DSP(2)) */
+ u32 irq_addr;
+ /* IRQ data content loaded in the AESS IRQ register */
+ u32 irq_data;
+ /* Call-back function upon IRQ reception */
+ u32 callback;
+ } prot_pingpong;
+ /* DMAreq line to CBPr */
+ struct {
+ /* Address of ATC descriptor's */
+ u32 desc_addr;
+ /* DMEM buffer address in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size size in bytes */
+ u32 buf_size;
+ /* ITERation on each DMAreq signals */
+ u32 iter;
+ /* DMAreq address */
+ u32 dma_addr;
+ /* DMA/AESS = 1 << #DMA */
+ u32 dma_data;
+ } prot_dmareq;
+ /* Circular buffer - direct addressing to DMEM */
+ struct {
+ /* DMEM buffer base address in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size in bytes */
+ u32 buf_size;
+ /* DMAreq address */
+ u32 dma_addr;
+ /* DMA/AESS = 1 << #DMA */
+ u32 dma_data;
+ } prot_circular_buffer;
+ } p;
+} abe_port_protocol_t;
+/*
+ * DMA_T
+ *
+ * dma structure for easing programming
+ */
+typedef struct {
+ /* OCP L3 pointer to the first address of the */
+ void *data;
+ /* destination buffer (either DMA or Ping-Pong read/write pointers). */
+ /* address L3 when addressing the DMEM buffer instead of CBPr */
+ void *l3_dmem;
+ /* address L3 translated to L4 the ARM memory space */
+ void *l4_dmem;
+ /* number of iterations for the DMA data moves. */
+ u32 iter;
+} abe_dma_t;
+
+typedef struct {
+ /* Offset to the first address of the */
+ u32 data;
+ /* number of iterations for the DMA data moves. */
+ u32 iter;
+} abe_dma_t_offset;
+/*
+ * SEQ_T
+ *
+ * struct {
+ * micros_t time; Waiting time before executing next line
+ * seq_code_t code Subroutine index interpreted in the HAL
+ * and translated to FW subroutine codes
+ * in case of ABE tasks
+ * int32 param[2] Two parameters
+ * } seq_t
+ *
+ */
+typedef struct {
+ u32 delta_time;
+ u32 code;
+ u32 param[4];
+ u8 tag;
+} abe_seq_t;
+
+typedef struct {
+ u32 mask;
+ abe_seq_t seq1;
+ abe_seq_t seq2;
+} abe_sequence_t;
+/*
+ * DRIFT_T abe_drift_t = s32
+ *
+ * ASRC drift parameter in [ppm] value
+ */
+/*
+ * -------------------- INTERNAL DATA TYPES ---------------------
+ */
+/*
+ * ABE_IRQ_DATA_T
+ *
+ * IRQ FIFO content declaration
+ * APS interrupts : IRQ_FIFO[31:28] = IRQtag_APS,
+ * IRQ_FIFO[27:16] = APS_IRQs, IRQ_FIFO[15:0] = loopCounter
+ * SEQ interrupts : IRQ_FIFO[31:28] IRQtag_COUNT,
+ * IRQ_FIFO[27:16] = Count_IRQs, IRQ_FIFO[15:0] = loopCounter
+ * Ping-Pong Interrupts : IRQ_FIFO[31:28] = IRQtag_PP,
+ * IRQ_FIFO[27:16] = PP_MCU_IRQ, IRQ_FIFO[15:0] = loopCounter
+ */
+typedef struct {
+ unsigned int counter:16;
+ unsigned int data:12;
+ unsigned int tag:4;
+} abe_irq_data_t;
+/*
+ * ABE_PORT_T status / format / sampling / protocol(call_back) /
+ * features / gain / name ..
+ *
+ */
+typedef struct {
+ /* running / idled */
+ u16 status;
+ /* Sample format type */
+ abe_data_format_t format;
+ /* API : for ASRC */
+ s32 drift;
+ /* optionnal call-back index for errors and ack */
+ u16 callback;
+ /* IO tasks buffers */
+ u16 smem_buffer1;
+ u16 smem_buffer2;
+ abe_port_protocol_t protocol;
+ /* pointer and iteration counter of the xDMA */
+ abe_dma_t_offset dma;
+ /* list of features associated to a port (EQ, APS, ... , ends with 0) */
+ u16 feature_index[MAXFEATUREPORT];
+ char name[NBCHARPORTNAME];
+} abe_port_t;
+/*
+ * ABE_SUBROUTINE_T
+ *
+ */
+typedef struct {
+ u32 sub_id;
+ s32 param[4];
+} abe_subroutine_t;
+
+#endif/* ifndef _ABE_TYP_H_ */
diff --git a/sound/soc/omap/abe/abe_typedef.h b/sound/soc/omap/abe/abe_typedef.h
new file mode 100644
index 0000000..59d7221
--- /dev/null
+++ b/sound/soc/omap/abe/abe_typedef.h
@@ -0,0 +1,232 @@
+/*
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ The full GNU General Public License is included in this distribution
+ in the file called LICENSE.GPL.
+
+ BSD LICENSE
+
+ Copyright(c) 2010-2011 Texas Instruments Incorporated,
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ its contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _ABE_TYPEDEF_H_
+#define _ABE_TYPEDEF_H_
+
+#include "abe_define.h"
+#include "abe_typ.h"
+
+/*
+ * Basic types definition
+ */
+/*
+ * Commonly used structures
+ */
+typedef struct abetaskTag {
+ /* 0 ... Index of called function */
+ u16 iF;
+ /* 2 ... for INITPTR of A0 */
+ u16 A0;
+ /* 4 ... for INITPTR of A1 */
+ u16 A1;
+ /* 6 ... for INITPTR of A2 & A3 */
+ u16 A2_3;
+ /* 8 ... for INITPTR of A4 & A5 */
+ u16 A4_5;
+ /* 10 ... for INITREG of R0, R1, R2, R3 */
+ u16 R;
+ /* 12 */
+ u16 misc0;
+ /* 14 */
+ u16 misc1;
+} ABE_STask;
+typedef ABE_STask *pABE_STask;
+typedef ABE_STask **ppABE_STask;
+
+struct ABE_SIODescriptor {
+ /* 0 */
+ u16 drift_ASRC;
+ /* 2 */
+ u16 drift_io;
+ /* 4 "Function index" of XLS sheet "Functions" */
+ u8 io_type_idx;
+ /* 5 1 = MONO or Stereo1616, 2= STEREO, ... */
+ u8 samp_size;
+ /* 6 drift "issues" for ASRC */
+ s16 flow_counter;
+ /* 8 address for IRQ or DMArequests */
+ u16 hw_ctrl_addr;
+ /* 10 DMA request bit-field or IRQ (DSP/MCU) */
+ u8 atc_irq_data;
+ /* 11 0 = Read, 3 = Write */
+ u8 direction_rw;
+ /* 12 */
+ u8 repeat_last_samp;
+ /* 13 12 at 48kHz, ... */
+ u8 nsamp;
+ /* 14 nsamp x samp_size */
+ u8 x_io;
+ /* 15 ON = 0x80, OFF = 0x00 */
+ u8 on_off;
+ /* 16 For Slimbus and TDM purpose */
+ u16 split_addr1;
+ /* 18 */
+ u16 split_addr2;
+ /* 20 */
+ u16 split_addr3;
+ /* 22 */
+ u8 before_f_index;
+ /* 23 */
+ u8 after_f_index;
+ /* 24 SM/CM INITPTR field */
+ u16 smem_addr1;
+ /* 26 in bytes */
+ u16 atc_address1;
+ /* 28 DMIC_ATC_PTR, MCPDM_UL_ATC_PTR, ... */
+ u16 atc_pointer_saved1;
+ /* 30 samp_size (except in TDM or Slimbus) */
+ u8 data_size1;
+ /* 31 "Function index" of XLS sheet "Functions" */
+ u8 copy_f_index1;
+ /* 32 For Slimbus and TDM purpose */
+ u16 smem_addr2;
+ /* 34 */
+ u16 atc_address2;
+ /* 36 */
+ u16 atc_pointer_saved2;
+ /* 38 */
+ u8 data_size2;
+ /* 39 */
+ u8 copy_f_index2;
+};
+
+/* [w] asrc output used for the next asrc call (+/- 1 / 0) */
+#define drift_asrc_ 0
+/* [w] asrc output used for controlling the number of samples to be
+ exchanged (+/- 1 / 0) */
+#define drift_io_ 2
+/* address of the IO subroutine */
+#define io_type_idx_ 4
+#define samp_size_ 5
+/* flow error counter */
+#define flow_counter_ 6
+/* dmareq address or host irq buffer address (atc address) */
+#define hw_ctrl_addr_ 8
+/* data content to be loaded to "hw_ctrl_addr" */
+#define atc_irq_data_ 10
+/* read dmem =0, write dmem =3 (atc offset of the access pointer) */
+#define direction_rw_ 11
+/* flag set to allow repeating the last sample on downlink paths */
+#define repeat_last_samp_ 12
+/* number of samples (either mono stereo...) */
+#define nsamp_ 13
+/* x number of raw DMEM data moved */
+#define x_io_ 14
+#define on_off_ 15
+/* internal smem buffer initptr pointer index */
+#define split_addr1_ 16
+/* internal smem buffer initptr pointer index */
+#define split_addr2_ 18
+/* internal smem buffer initptr pointer index */
+#define split_addr3_ 20
+/* index of the copy subroutine */
+#define before_f_index_ 22
+/* index of the copy subroutine */
+#define after_f_index_ 23
+#define minidesc1_ 24
+/* internal smem buffer initptr pointer index */
+#define rel_smem_ 0
+/* atc descriptor address (byte address x4) */
+#define rel_atc_ 2
+/* location of the saved ATC pointer (+debug info) */
+#define rel_atc_saved 4
+/* size of each sample (1:mono/1616 2:stereo ... ) */
+#define rel_size_ 6
+/* index of the copy subroutine */
+#define rel_f_ 7
+#define s_mem_mm_ul 24
+#define s_mm_ul_size 30
+#define minidesc2_ 32
+#define Struct_Size 40
+
+struct ABE_SPingPongDescriptor {
+ /* 0: [W] asrc output used for the next ASRC call (+/- 1 / 0) */
+ u16 drift_ASRC;
+ /* 2: [W] asrc output used for controlling the number of
+ samples to be exchanged (+/- 1 / 0) */
+ u16 drift_io;
+ /* 4: DMAReq address or HOST IRQ buffer address (ATC ADDRESS) */
+ u16 hw_ctrl_addr;
+ /* 6: index of the copy subroutine */
+ u8 copy_func_index;
+ /* 7: X number of SMEM samples to move */
+ u8 x_io;
+ /* 8: 0 for mono data, 1 for stereo data */
+ u8 data_size;
+ /* 9: internal SMEM buffer INITPTR pointer index */
+ u8 smem_addr;
+ /* 10: data content to be loaded to "hw_ctrl_addr" */
+ u8 atc_irq_data;
+ /* 11: ping/pong buffer flag */
+ u8 counter;
+ /* 12: current Base address of the working buffer */
+ u16 workbuff_BaseAddr;
+ /* 14: samples left in the working buffer */
+ u16 workbuff_Samples;
+ /* 16: Base address of the ping/pong buffer 0 */
+ u16 nextbuff0_BaseAddr;
+ /* 18: samples available in the ping/pong buffer 0 */
+ u16 nextbuff0_Samples;
+ /* 20: Base address of the ping/pong buffer 1 */
+ u16 nextbuff1_BaseAddr;
+ /* 22: samples available in the ping/pong buffer 1 */
+ u16 nextbuff1_Samples;
+};
+
+#endif/* _ABE_TYPEDEF_H_ */