[MIPS] FPU ownership management & preemption fixes
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 656bde2..28c2e2e 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -49,8 +49,7 @@
#ifndef CONFIG_CPU_HAS_LLSC
sw zero, ll_bit
#endif
- mfc0 t1, CP0_STATUS
- sw t1, THREAD_STATUS(a0)
+ mfc0 t2, CP0_STATUS
cpu_save_nonscratch a0
sw ra, THREAD_REG31(a0)
@@ -60,8 +59,8 @@
lw t3, TASK_THREAD_INFO(a0)
lw t0, TI_FLAGS(t3)
li t1, _TIF_USEDFPU
- and t2, t0, t1
- beqz t2, 1f
+ and t1, t0
+ beqz t1, 1f
nor t1, zero, t1
and t0, t0, t1
@@ -74,10 +73,13 @@
li t1, ~ST0_CU1
and t0, t0, t1
sw t0, ST_OFF(t3)
+ /* clear thread_struct CU1 bit */
+ and t2, t1
fpu_save_single a0, t0 # clobbers t0
1:
+ sw t2, THREAD_STATUS(a0)
/*
* The order of restoring the registers takes care of the race
* updating $28, $29 and kernelsp without disabling ints.