gpio: msm-v3: Fix the INTR_POL_CTL bit configuration
According to the TLMM_v3 hardware spec the INTR_POL_CTL bit
is to be set:
Low for level low interrupts;
High for level high interrupts;
High for all edge interrupts.
Make sure the software configures it as desired.
Change-Id: I3369def7bd00e427c7dfe109bcdd4b6e207ad239
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
diff --git a/drivers/gpio/gpio-msm-v3.c b/drivers/gpio/gpio-msm-v3.c
index e041bfd..26716a0 100644
--- a/drivers/gpio/gpio-msm-v3.c
+++ b/drivers/gpio/gpio-msm-v3.c
@@ -183,10 +183,10 @@
else
cfg |= INTR_DECT_CTL_LEVEL;
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
- cfg |= INTR_POL_CTL_HI;
- else
+ if (type & IRQ_TYPE_LEVEL_LOW)
cfg &= ~INTR_POL_CTL_HI;
+ else
+ cfg |= INTR_POL_CTL_HI;
__raw_writel(cfg, GPIO_INTR_CFG(gpio));
/* Sometimes it might take a little while to update