msm: acpuclock: Add CPU freq. tables 7x25a
MSM7x25a can run at max. freq. of 600Mhz and returns
the same PLL1_Lvalue as of MSM7x27 and due to which
it defaults to the MSM7x27 tables, but the voltage
levels are not 1:1 mapped with 7x27 and actually has one less
voltage level. It is better to have separate tables
in-order to keep MSM7x27 and MSM7x25a changes not impacting
each other.
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock.c b/arch/arm/mach-msm/acpuclock.c
index 796bc64..2147232 100644
--- a/arch/arm/mach-msm/acpuclock.c
+++ b/arch/arm/mach-msm/acpuclock.c
@@ -316,6 +316,20 @@
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
};
+/* 7x25a pll2 at 1200mhz with GSM capable modem */
+static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_1200_pll4_800_25a[] = {
+ { 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 30720 },
+ { 0, 61440, ACPU_PLL_1, 1, 3, 7680, 3, 1, 61440 },
+ { 1, 122880, ACPU_PLL_1, 1, 1, 15360, 3, 2, 61440 },
+ { 1, 245760, ACPU_PLL_1, 1, 0, 30720, 3, 3, 61440 },
+ { 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 4, 150000 },
+ { 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 4, 122880 },
+ { 0, 400000, ACPU_PLL_4, 6, 1, 50000, 3, 4, 122880 },
+ { 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
+ { 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 200000 },
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+};
+
#define PLL_0_MHZ 0
#define PLL_196_MHZ 10
#define PLL_245_MHZ 12
@@ -858,13 +872,21 @@
pll0_needs_fixup = 1;
}
- /* Select the right table to use. */
- for (lst = acpu_freq_tbl_list; lst->tbl != 0; lst++) {
- if (lst->pll0_l == pll0_l && lst->pll1_l == pll1_l
- && lst->pll2_l == pll2_l
- && lst->pll4_l == pll4_l) {
- acpu_freq_tbl = lst->tbl;
- break;
+ /* Fix the tables for 7x25a variant to not conflict with 7x27 ones */
+ if (cpu_is_msm7x25a()) {
+ if (pll1_l == PLL_245_MHZ) {
+ acpu_freq_tbl =
+ pll0_960_pll1_245_pll2_1200_pll4_800_25a;
+ }
+ } else {
+ /* Select the right table to use. */
+ for (lst = acpu_freq_tbl_list; lst->tbl != 0; lst++) {
+ if (lst->pll0_l == pll0_l && lst->pll1_l == pll1_l
+ && lst->pll2_l == pll2_l
+ && lst->pll4_l == pll4_l) {
+ acpu_freq_tbl = lst->tbl;
+ break;
+ }
}
}