msm: acpuclock-7627: Prepare PLLs during init
The new clk_prepare()/clk_unprepare() APIs need to be called from
non-atomic context. Since acpuclock is used in such places as
suspend/resume which is always in atomic context we must prepare
the PLLs during init or risk the chance of enabling a PLL that
isn't prepared.
Change-Id: I3ccf8d9354b302eda52056377c40a63a7fdb382d
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-7627.c b/arch/arm/mach-msm/acpuclock-7627.c
index b6c0b26..99311d4 100644
--- a/arch/arm/mach-msm/acpuclock-7627.c
+++ b/arch/arm/mach-msm/acpuclock-7627.c
@@ -527,7 +527,7 @@
if (reason == SETRATE_CPUFREQ) {
if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) {
- rc = clk_prepare_enable(pll_clk[tgt_s->pll].clk);
+ rc = clk_enable(pll_clk[tgt_s->pll].clk);
if (rc < 0) {
pr_err("PLL%d enable failed (%d)\n",
tgt_s->pll, rc);
@@ -602,7 +602,7 @@
if (cur_s->pll != ACPU_PLL_TCXO
&& !(plls_enabled & (1 << cur_s->pll))) {
- rc = clk_prepare_enable(pll_clk[cur_s->pll].clk);
+ rc = clk_enable(pll_clk[cur_s->pll].clk);
if (rc < 0) {
pr_err("PLL%d enable failed (%d)\n",
cur_s->pll, rc);
@@ -642,7 +642,7 @@
plls_enabled &= ~(1 << tgt_s->pll);
for (pll = ACPU_PLL_0; pll < ACPU_PLL_END; pll++)
if (plls_enabled & (1 << pll))
- clk_disable_unprepare(pll_clk[pll].clk);
+ clk_disable(pll_clk[pll].clk);
/* Nothing else to do for power collapse. */
if (reason == SETRATE_PC)
@@ -669,6 +669,18 @@
int res;
/*
+ * Prepare all the PLLs because we enable/disable them
+ * from atomic context and can't always ensure they're
+ * all prepared in non-atomic context. Same goes for
+ * ebi1_acpu_clk.
+ */
+ BUG_ON(clk_prepare(pll_clk[ACPU_PLL_0].clk));
+ BUG_ON(clk_prepare(pll_clk[ACPU_PLL_1].clk));
+ BUG_ON(clk_prepare(pll_clk[ACPU_PLL_2].clk));
+ BUG_ON(clk_prepare(pll_clk[ACPU_PLL_4].clk));
+ BUG_ON(clk_prepare(drv_state.ebi1_clk));
+
+ /*
* Determine the rate of ACPU clock
*/
@@ -696,7 +708,7 @@
drv_state.current_speed = speed;
if (speed->pll != ACPU_PLL_TCXO) {
- if (clk_prepare_enable(pll_clk[speed->pll].clk))
+ if (clk_enable(pll_clk[speed->pll].clk))
pr_warning("Failed to vote for boot PLL\n");
}
@@ -711,7 +723,7 @@
res = clk_set_rate(drv_state.ebi1_clk, speed->axiclk_khz * 1000);
if (res < 0)
pr_warning("Setting AXI min rate failed (%d)\n", res);
- res = clk_prepare_enable(drv_state.ebi1_clk);
+ res = clk_enable(drv_state.ebi1_clk);
if (res < 0)
pr_warning("Enabling AXI clock failed (%d)\n", res);