msm: clock-8960: Enable PLL8 after set it to fsm mode for 8064
PLL8 might be off when acpuclock running off it during bootup.
Therefore, vote to enable it after setting it to fsm mode to
ensure it is on during clock init. The voting is done on behalf
of RPM since no client from RPM should vote this PLL off so we
have PLL8 always on. These changes will not be needed if boot
chain is in place and configure it correctly in future.
Change-Id: I07fdcabcc8684670f9a9eb54e5851871a516f93e
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 0366c7e..b42db03 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -69,6 +69,7 @@
#define PDM_CLK_NS_REG REG(0x2CC0)
/* 8064 name BB_PLL_ENA_APCS_REG */
#define BB_PLL_ENA_SC0_REG REG(0x34C0)
+#define BB_PLL_ENA_RPM_REG REG(0x34A0)
#define BB_PLL0_STATUS_REG REG(0x30D8)
#define BB_PLL5_STATUS_REG REG(0x30F8)
#define BB_PLL6_STATUS_REG REG(0x3118)
@@ -5556,6 +5557,11 @@
writel_relaxed(regval, BB_PLL8_TEST_CTL_REG);
set_fsm_mode(BB_PLL8_MODE_REG);
+
+ /* Enable PLL8 by voting from RPM */
+ regval = readl_relaxed(BB_PLL_ENA_RPM_REG);
+ regval |= BIT(8);
+ writel_relaxed(regval, BB_PLL_ENA_RPM_REG);
}
/* Check if PLL3 is active */
is_pll_enabled = readl_relaxed(GPLL1_STATUS_REG) & BIT(16);