MIPS: PowerTV: Streamline access to platform device registers
Pre-compute addresses for the basic ASIC registers. This speeds up access
and allows memory for unused configurations to be freed. In addition,
uninitialized register addresses will be returned as NULL to catch bad
usage quickly.
Signed-off-by: David VomLehn <dvomlehn@cisco.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/806/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c
index 03d3884..1ae6623 100644
--- a/arch/mips/powertv/asic/asic-calliope.c
+++ b/arch/mips/powertv/asic/asic-calliope.c
@@ -23,76 +23,79 @@
* Description: Defines the platform resources for the SA settop.
*/
+#include <linux/init.h>
#include <asm/mach-powertv/asic.h>
-const struct register_map calliope_register_map = {
- .eic_slow0_strt_add = 0x800000,
- .eic_cfg_bits = 0x800038,
- .eic_ready_status = 0x80004c,
+#define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x))
- .chipver3 = 0xA00800,
- .chipver2 = 0xA00804,
- .chipver1 = 0xA00808,
- .chipver0 = 0xA0080c,
+const struct register_map calliope_register_map __initdata = {
+ .eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)},
+ .eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)},
+ .eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)},
+
+ .chipver3 = {.phys = CALLIOPE_ADDR(0xA00800)},
+ .chipver2 = {.phys = CALLIOPE_ADDR(0xA00804)},
+ .chipver1 = {.phys = CALLIOPE_ADDR(0xA00808)},
+ .chipver0 = {.phys = CALLIOPE_ADDR(0xA0080c)},
/* The registers of IRBlaster */
- .uart1_intstat = 0xA01800,
- .uart1_inten = 0xA01804,
- .uart1_config1 = 0xA01808,
- .uart1_config2 = 0xA0180C,
- .uart1_divisorhi = 0xA01810,
- .uart1_divisorlo = 0xA01814,
- .uart1_data = 0xA01818,
- .uart1_status = 0xA0181C,
+ .uart1_intstat = {.phys = CALLIOPE_ADDR(0xA01800)},
+ .uart1_inten = {.phys = CALLIOPE_ADDR(0xA01804)},
+ .uart1_config1 = {.phys = CALLIOPE_ADDR(0xA01808)},
+ .uart1_config2 = {.phys = CALLIOPE_ADDR(0xA0180C)},
+ .uart1_divisorhi = {.phys = CALLIOPE_ADDR(0xA01810)},
+ .uart1_divisorlo = {.phys = CALLIOPE_ADDR(0xA01814)},
+ .uart1_data = {.phys = CALLIOPE_ADDR(0xA01818)},
+ .uart1_status = {.phys = CALLIOPE_ADDR(0xA0181C)},
- .int_stat_3 = 0xA02800,
- .int_stat_2 = 0xA02804,
- .int_stat_1 = 0xA02808,
- .int_stat_0 = 0xA0280c,
- .int_config = 0xA02810,
- .int_int_scan = 0xA02818,
- .ien_int_3 = 0xA02830,
- .ien_int_2 = 0xA02834,
- .ien_int_1 = 0xA02838,
- .ien_int_0 = 0xA0283c,
- .int_level_3_3 = 0xA02880,
- .int_level_3_2 = 0xA02884,
- .int_level_3_1 = 0xA02888,
- .int_level_3_0 = 0xA0288c,
- .int_level_2_3 = 0xA02890,
- .int_level_2_2 = 0xA02894,
- .int_level_2_1 = 0xA02898,
- .int_level_2_0 = 0xA0289c,
- .int_level_1_3 = 0xA028a0,
- .int_level_1_2 = 0xA028a4,
- .int_level_1_1 = 0xA028a8,
- .int_level_1_0 = 0xA028ac,
- .int_level_0_3 = 0xA028b0,
- .int_level_0_2 = 0xA028b4,
- .int_level_0_1 = 0xA028b8,
- .int_level_0_0 = 0xA028bc,
- .int_docsis_en = 0xA028F4,
+ .int_stat_3 = {.phys = CALLIOPE_ADDR(0xA02800)},
+ .int_stat_2 = {.phys = CALLIOPE_ADDR(0xA02804)},
+ .int_stat_1 = {.phys = CALLIOPE_ADDR(0xA02808)},
+ .int_stat_0 = {.phys = CALLIOPE_ADDR(0xA0280c)},
+ .int_config = {.phys = CALLIOPE_ADDR(0xA02810)},
+ .int_int_scan = {.phys = CALLIOPE_ADDR(0xA02818)},
+ .ien_int_3 = {.phys = CALLIOPE_ADDR(0xA02830)},
+ .ien_int_2 = {.phys = CALLIOPE_ADDR(0xA02834)},
+ .ien_int_1 = {.phys = CALLIOPE_ADDR(0xA02838)},
+ .ien_int_0 = {.phys = CALLIOPE_ADDR(0xA0283c)},
+ .int_level_3_3 = {.phys = CALLIOPE_ADDR(0xA02880)},
+ .int_level_3_2 = {.phys = CALLIOPE_ADDR(0xA02884)},
+ .int_level_3_1 = {.phys = CALLIOPE_ADDR(0xA02888)},
+ .int_level_3_0 = {.phys = CALLIOPE_ADDR(0xA0288c)},
+ .int_level_2_3 = {.phys = CALLIOPE_ADDR(0xA02890)},
+ .int_level_2_2 = {.phys = CALLIOPE_ADDR(0xA02894)},
+ .int_level_2_1 = {.phys = CALLIOPE_ADDR(0xA02898)},
+ .int_level_2_0 = {.phys = CALLIOPE_ADDR(0xA0289c)},
+ .int_level_1_3 = {.phys = CALLIOPE_ADDR(0xA028a0)},
+ .int_level_1_2 = {.phys = CALLIOPE_ADDR(0xA028a4)},
+ .int_level_1_1 = {.phys = CALLIOPE_ADDR(0xA028a8)},
+ .int_level_1_0 = {.phys = CALLIOPE_ADDR(0xA028ac)},
+ .int_level_0_3 = {.phys = CALLIOPE_ADDR(0xA028b0)},
+ .int_level_0_2 = {.phys = CALLIOPE_ADDR(0xA028b4)},
+ .int_level_0_1 = {.phys = CALLIOPE_ADDR(0xA028b8)},
+ .int_level_0_0 = {.phys = CALLIOPE_ADDR(0xA028bc)},
+ .int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)},
- .mips_pll_setup = 0x980000,
- .usb_fs = 0x980030, /* -default 72800028- */
- .test_bus = 0x9800CC,
- .crt_spare = 0x9800d4,
- .usb2_ohci_int_mask = 0x9A000c,
- .usb2_strap = 0x9A0014,
- .ehci_hcapbase = 0x9BFE00,
- .ohci_hc_revision = 0x9BFC00,
- .bcm1_bs_lmi_steer = 0x9E0004,
- .usb2_control = 0x9E0054,
- .usb2_stbus_obc = 0x9BFF00,
- .usb2_stbus_mess_size = 0x9BFF04,
- .usb2_stbus_chunk_size = 0x9BFF08,
+ .mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)},
+ .usb_fs = {.phys = CALLIOPE_ADDR(0x980030)},
+ .test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)},
+ .crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)},
+ .usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)},
+ .usb2_strap = {.phys = CALLIOPE_ADDR(0x9A0014)},
+ .ehci_hcapbase = {.phys = CALLIOPE_ADDR(0x9BFE00)},
+ .ohci_hc_revision = {.phys = CALLIOPE_ADDR(0x9BFC00)},
+ .bcm1_bs_lmi_steer = {.phys = CALLIOPE_ADDR(0x9E0004)},
+ .usb2_control = {.phys = CALLIOPE_ADDR(0x9E0054)},
+ .usb2_stbus_obc = {.phys = CALLIOPE_ADDR(0x9BFF00)},
+ .usb2_stbus_mess_size = {.phys = CALLIOPE_ADDR(0x9BFF04)},
+ .usb2_stbus_chunk_size = {.phys = CALLIOPE_ADDR(0x9BFF08)},
- .pcie_regs = 0x000000, /* -doesn't exist- */
- .tim_ch = 0xA02C10,
- .tim_cl = 0xA02C14,
- .gpio_dout = 0xA02c20,
- .gpio_din = 0xA02c24,
- .gpio_dir = 0xA02c2C,
- .watchdog = 0xA02c30,
- .front_panel = 0x000000, /* -not used- */
+ .pcie_regs = {.phys = 0x000000}, /* -doesn't exist- */
+ .tim_ch = {.phys = CALLIOPE_ADDR(0xA02C10)},
+ .tim_cl = {.phys = CALLIOPE_ADDR(0xA02C14)},
+ .gpio_dout = {.phys = CALLIOPE_ADDR(0xA02c20)},
+ .gpio_din = {.phys = CALLIOPE_ADDR(0xA02c24)},
+ .gpio_dir = {.phys = CALLIOPE_ADDR(0xA02c2C)},
+ .watchdog = {.phys = CALLIOPE_ADDR(0xA02c30)},
+ .front_panel = {.phys = 0x000000}, /* -not used- */
};
diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c
index 5f4589c..5bb64bf 100644
--- a/arch/mips/powertv/asic/asic-cronus.c
+++ b/arch/mips/powertv/asic/asic-cronus.c
@@ -23,76 +23,79 @@
* Description: Defines the platform resources for the SA settop.
*/
+#include <linux/init.h>
#include <asm/mach-powertv/asic.h>
-const struct register_map cronus_register_map = {
- .eic_slow0_strt_add = 0x000000,
- .eic_cfg_bits = 0x000038,
- .eic_ready_status = 0x00004C,
+#define CRONUS_ADDR(x) (CRONUS_IO_BASE + (x))
- .chipver3 = 0x2A0800,
- .chipver2 = 0x2A0804,
- .chipver1 = 0x2A0808,
- .chipver0 = 0x2A080C,
+const struct register_map cronus_register_map __initdata = {
+ .eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)},
+ .eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)},
+ .eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)},
+
+ .chipver3 = {.phys = CRONUS_ADDR(0x2A0800)},
+ .chipver2 = {.phys = CRONUS_ADDR(0x2A0804)},
+ .chipver1 = {.phys = CRONUS_ADDR(0x2A0808)},
+ .chipver0 = {.phys = CRONUS_ADDR(0x2A080C)},
/* The registers of IRBlaster */
- .uart1_intstat = 0x2A1800,
- .uart1_inten = 0x2A1804,
- .uart1_config1 = 0x2A1808,
- .uart1_config2 = 0x2A180C,
- .uart1_divisorhi = 0x2A1810,
- .uart1_divisorlo = 0x2A1814,
- .uart1_data = 0x2A1818,
- .uart1_status = 0x2A181C,
+ .uart1_intstat = {.phys = CRONUS_ADDR(0x2A1800)},
+ .uart1_inten = {.phys = CRONUS_ADDR(0x2A1804)},
+ .uart1_config1 = {.phys = CRONUS_ADDR(0x2A1808)},
+ .uart1_config2 = {.phys = CRONUS_ADDR(0x2A180C)},
+ .uart1_divisorhi = {.phys = CRONUS_ADDR(0x2A1810)},
+ .uart1_divisorlo = {.phys = CRONUS_ADDR(0x2A1814)},
+ .uart1_data = {.phys = CRONUS_ADDR(0x2A1818)},
+ .uart1_status = {.phys = CRONUS_ADDR(0x2A181C)},
- .int_stat_3 = 0x2A2800,
- .int_stat_2 = 0x2A2804,
- .int_stat_1 = 0x2A2808,
- .int_stat_0 = 0x2A280C,
- .int_config = 0x2A2810,
- .int_int_scan = 0x2A2818,
- .ien_int_3 = 0x2A2830,
- .ien_int_2 = 0x2A2834,
- .ien_int_1 = 0x2A2838,
- .ien_int_0 = 0x2A283C,
- .int_level_3_3 = 0x2A2880,
- .int_level_3_2 = 0x2A2884,
- .int_level_3_1 = 0x2A2888,
- .int_level_3_0 = 0x2A288C,
- .int_level_2_3 = 0x2A2890,
- .int_level_2_2 = 0x2A2894,
- .int_level_2_1 = 0x2A2898,
- .int_level_2_0 = 0x2A289C,
- .int_level_1_3 = 0x2A28A0,
- .int_level_1_2 = 0x2A28A4,
- .int_level_1_1 = 0x2A28A8,
- .int_level_1_0 = 0x2A28AC,
- .int_level_0_3 = 0x2A28B0,
- .int_level_0_2 = 0x2A28B4,
- .int_level_0_1 = 0x2A28B8,
- .int_level_0_0 = 0x2A28BC,
- .int_docsis_en = 0x2A28F4,
+ .int_stat_3 = {.phys = CRONUS_ADDR(0x2A2800)},
+ .int_stat_2 = {.phys = CRONUS_ADDR(0x2A2804)},
+ .int_stat_1 = {.phys = CRONUS_ADDR(0x2A2808)},
+ .int_stat_0 = {.phys = CRONUS_ADDR(0x2A280C)},
+ .int_config = {.phys = CRONUS_ADDR(0x2A2810)},
+ .int_int_scan = {.phys = CRONUS_ADDR(0x2A2818)},
+ .ien_int_3 = {.phys = CRONUS_ADDR(0x2A2830)},
+ .ien_int_2 = {.phys = CRONUS_ADDR(0x2A2834)},
+ .ien_int_1 = {.phys = CRONUS_ADDR(0x2A2838)},
+ .ien_int_0 = {.phys = CRONUS_ADDR(0x2A283C)},
+ .int_level_3_3 = {.phys = CRONUS_ADDR(0x2A2880)},
+ .int_level_3_2 = {.phys = CRONUS_ADDR(0x2A2884)},
+ .int_level_3_1 = {.phys = CRONUS_ADDR(0x2A2888)},
+ .int_level_3_0 = {.phys = CRONUS_ADDR(0x2A288C)},
+ .int_level_2_3 = {.phys = CRONUS_ADDR(0x2A2890)},
+ .int_level_2_2 = {.phys = CRONUS_ADDR(0x2A2894)},
+ .int_level_2_1 = {.phys = CRONUS_ADDR(0x2A2898)},
+ .int_level_2_0 = {.phys = CRONUS_ADDR(0x2A289C)},
+ .int_level_1_3 = {.phys = CRONUS_ADDR(0x2A28A0)},
+ .int_level_1_2 = {.phys = CRONUS_ADDR(0x2A28A4)},
+ .int_level_1_1 = {.phys = CRONUS_ADDR(0x2A28A8)},
+ .int_level_1_0 = {.phys = CRONUS_ADDR(0x2A28AC)},
+ .int_level_0_3 = {.phys = CRONUS_ADDR(0x2A28B0)},
+ .int_level_0_2 = {.phys = CRONUS_ADDR(0x2A28B4)},
+ .int_level_0_1 = {.phys = CRONUS_ADDR(0x2A28B8)},
+ .int_level_0_0 = {.phys = CRONUS_ADDR(0x2A28BC)},
+ .int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)},
- .mips_pll_setup = 0x1C0000,
- .usb_fs = 0x1C0018,
- .test_bus = 0x1C00CC,
- .crt_spare = 0x1c00d4,
- .usb2_ohci_int_mask = 0x20000C,
- .usb2_strap = 0x200014,
- .ehci_hcapbase = 0x21FE00,
- .ohci_hc_revision = 0x1E0000,
- .bcm1_bs_lmi_steer = 0x2E0008,
- .usb2_control = 0x2E004C,
- .usb2_stbus_obc = 0x21FF00,
- .usb2_stbus_mess_size = 0x21FF04,
- .usb2_stbus_chunk_size = 0x21FF08,
+ .mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)},
+ .usb_fs = {.phys = CRONUS_ADDR(0x1C0018)},
+ .test_bus = {.phys = CRONUS_ADDR(0x1C00CC)},
+ .crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)},
+ .usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)},
+ .usb2_strap = {.phys = CRONUS_ADDR(0x200014)},
+ .ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)},
+ .ohci_hc_revision = {.phys = CRONUS_ADDR(0x1E0000)},
+ .bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)},
+ .usb2_control = {.phys = CRONUS_ADDR(0x2E004C)},
+ .usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)},
+ .usb2_stbus_mess_size = {.phys = CRONUS_ADDR(0x21FF04)},
+ .usb2_stbus_chunk_size = {.phys = CRONUS_ADDR(0x21FF08)},
- .pcie_regs = 0x220000,
- .tim_ch = 0x2A2C10,
- .tim_cl = 0x2A2C14,
- .gpio_dout = 0x2A2C20,
- .gpio_din = 0x2A2C24,
- .gpio_dir = 0x2A2C2C,
- .watchdog = 0x2A2C30,
- .front_panel = 0x2A3800,
+ .pcie_regs = {.phys = CRONUS_ADDR(0x220000)},
+ .tim_ch = {.phys = CRONUS_ADDR(0x2A2C10)},
+ .tim_cl = {.phys = CRONUS_ADDR(0x2A2C14)},
+ .gpio_dout = {.phys = CRONUS_ADDR(0x2A2C20)},
+ .gpio_din = {.phys = CRONUS_ADDR(0x2A2C24)},
+ .gpio_dir = {.phys = CRONUS_ADDR(0x2A2C2C)},
+ .watchdog = {.phys = CRONUS_ADDR(0x2A2C30)},
+ .front_panel = {.phys = CRONUS_ADDR(0x2A3800)},
};
diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c
index 1469daa..095cbe10 100644
--- a/arch/mips/powertv/asic/asic-zeus.c
+++ b/arch/mips/powertv/asic/asic-zeus.c
@@ -23,76 +23,79 @@
* Description: Defines the platform resources for the SA settop.
*/
+#include <linux/init.h>
#include <asm/mach-powertv/asic.h>
-const struct register_map zeus_register_map = {
- .eic_slow0_strt_add = 0x000000,
- .eic_cfg_bits = 0x000038,
- .eic_ready_status = 0x00004c,
+#define ZEUS_ADDR(x) (ZEUS_IO_BASE + (x))
- .chipver3 = 0x280800,
- .chipver2 = 0x280804,
- .chipver1 = 0x280808,
- .chipver0 = 0x28080c,
+const struct register_map zeus_register_map __initdata = {
+ .eic_slow0_strt_add = {.phys = ZEUS_ADDR(0x000000)},
+ .eic_cfg_bits = {.phys = ZEUS_ADDR(0x000038)},
+ .eic_ready_status = {.phys = ZEUS_ADDR(0x00004c)},
+
+ .chipver3 = {.phys = ZEUS_ADDR(0x280800)},
+ .chipver2 = {.phys = ZEUS_ADDR(0x280804)},
+ .chipver1 = {.phys = ZEUS_ADDR(0x280808)},
+ .chipver0 = {.phys = ZEUS_ADDR(0x28080c)},
/* The registers of IRBlaster */
- .uart1_intstat = 0x281800,
- .uart1_inten = 0x281804,
- .uart1_config1 = 0x281808,
- .uart1_config2 = 0x28180C,
- .uart1_divisorhi = 0x281810,
- .uart1_divisorlo = 0x281814,
- .uart1_data = 0x281818,
- .uart1_status = 0x28181C,
+ .uart1_intstat = {.phys = ZEUS_ADDR(0x281800)},
+ .uart1_inten = {.phys = ZEUS_ADDR(0x281804)},
+ .uart1_config1 = {.phys = ZEUS_ADDR(0x281808)},
+ .uart1_config2 = {.phys = ZEUS_ADDR(0x28180C)},
+ .uart1_divisorhi = {.phys = ZEUS_ADDR(0x281810)},
+ .uart1_divisorlo = {.phys = ZEUS_ADDR(0x281814)},
+ .uart1_data = {.phys = ZEUS_ADDR(0x281818)},
+ .uart1_status = {.phys = ZEUS_ADDR(0x28181C)},
- .int_stat_3 = 0x282800,
- .int_stat_2 = 0x282804,
- .int_stat_1 = 0x282808,
- .int_stat_0 = 0x28280c,
- .int_config = 0x282810,
- .int_int_scan = 0x282818,
- .ien_int_3 = 0x282830,
- .ien_int_2 = 0x282834,
- .ien_int_1 = 0x282838,
- .ien_int_0 = 0x28283c,
- .int_level_3_3 = 0x282880,
- .int_level_3_2 = 0x282884,
- .int_level_3_1 = 0x282888,
- .int_level_3_0 = 0x28288c,
- .int_level_2_3 = 0x282890,
- .int_level_2_2 = 0x282894,
- .int_level_2_1 = 0x282898,
- .int_level_2_0 = 0x28289c,
- .int_level_1_3 = 0x2828a0,
- .int_level_1_2 = 0x2828a4,
- .int_level_1_1 = 0x2828a8,
- .int_level_1_0 = 0x2828ac,
- .int_level_0_3 = 0x2828b0,
- .int_level_0_2 = 0x2828b4,
- .int_level_0_1 = 0x2828b8,
- .int_level_0_0 = 0x2828bc,
- .int_docsis_en = 0x2828F4,
+ .int_stat_3 = {.phys = ZEUS_ADDR(0x282800)},
+ .int_stat_2 = {.phys = ZEUS_ADDR(0x282804)},
+ .int_stat_1 = {.phys = ZEUS_ADDR(0x282808)},
+ .int_stat_0 = {.phys = ZEUS_ADDR(0x28280c)},
+ .int_config = {.phys = ZEUS_ADDR(0x282810)},
+ .int_int_scan = {.phys = ZEUS_ADDR(0x282818)},
+ .ien_int_3 = {.phys = ZEUS_ADDR(0x282830)},
+ .ien_int_2 = {.phys = ZEUS_ADDR(0x282834)},
+ .ien_int_1 = {.phys = ZEUS_ADDR(0x282838)},
+ .ien_int_0 = {.phys = ZEUS_ADDR(0x28283c)},
+ .int_level_3_3 = {.phys = ZEUS_ADDR(0x282880)},
+ .int_level_3_2 = {.phys = ZEUS_ADDR(0x282884)},
+ .int_level_3_1 = {.phys = ZEUS_ADDR(0x282888)},
+ .int_level_3_0 = {.phys = ZEUS_ADDR(0x28288c)},
+ .int_level_2_3 = {.phys = ZEUS_ADDR(0x282890)},
+ .int_level_2_2 = {.phys = ZEUS_ADDR(0x282894)},
+ .int_level_2_1 = {.phys = ZEUS_ADDR(0x282898)},
+ .int_level_2_0 = {.phys = ZEUS_ADDR(0x28289c)},
+ .int_level_1_3 = {.phys = ZEUS_ADDR(0x2828a0)},
+ .int_level_1_2 = {.phys = ZEUS_ADDR(0x2828a4)},
+ .int_level_1_1 = {.phys = ZEUS_ADDR(0x2828a8)},
+ .int_level_1_0 = {.phys = ZEUS_ADDR(0x2828ac)},
+ .int_level_0_3 = {.phys = ZEUS_ADDR(0x2828b0)},
+ .int_level_0_2 = {.phys = ZEUS_ADDR(0x2828b4)},
+ .int_level_0_1 = {.phys = ZEUS_ADDR(0x2828b8)},
+ .int_level_0_0 = {.phys = ZEUS_ADDR(0x2828bc)},
+ .int_docsis_en = {.phys = ZEUS_ADDR(0x2828F4)},
- .mips_pll_setup = 0x1a0000,
- .usb_fs = 0x1a0018,
- .test_bus = 0x1a0238,
- .crt_spare = 0x1a0090,
- .usb2_ohci_int_mask = 0x1e000c,
- .usb2_strap = 0x1e0014,
- .ehci_hcapbase = 0x1FFE00,
- .ohci_hc_revision = 0x1FFC00,
- .bcm1_bs_lmi_steer = 0x2C0008,
- .usb2_control = 0x2c01a0,
- .usb2_stbus_obc = 0x1FFF00,
- .usb2_stbus_mess_size = 0x1FFF04,
- .usb2_stbus_chunk_size = 0x1FFF08,
+ .mips_pll_setup = {.phys = ZEUS_ADDR(0x1a0000)},
+ .usb_fs = {.phys = ZEUS_ADDR(0x1a0018)},
+ .test_bus = {.phys = ZEUS_ADDR(0x1a0238)},
+ .crt_spare = {.phys = ZEUS_ADDR(0x1a0090)},
+ .usb2_ohci_int_mask = {.phys = ZEUS_ADDR(0x1e000c)},
+ .usb2_strap = {.phys = ZEUS_ADDR(0x1e0014)},
+ .ehci_hcapbase = {.phys = ZEUS_ADDR(0x1FFE00)},
+ .ohci_hc_revision = {.phys = ZEUS_ADDR(0x1FFC00)},
+ .bcm1_bs_lmi_steer = {.phys = ZEUS_ADDR(0x2C0008)},
+ .usb2_control = {.phys = ZEUS_ADDR(0x2c01a0)},
+ .usb2_stbus_obc = {.phys = ZEUS_ADDR(0x1FFF00)},
+ .usb2_stbus_mess_size = {.phys = ZEUS_ADDR(0x1FFF04)},
+ .usb2_stbus_chunk_size = {.phys = ZEUS_ADDR(0x1FFF08)},
- .pcie_regs = 0x200000,
- .tim_ch = 0x282C10,
- .tim_cl = 0x282C14,
- .gpio_dout = 0x282c20,
- .gpio_din = 0x282c24,
- .gpio_dir = 0x282c2C,
- .watchdog = 0x282c30,
- .front_panel = 0x283800,
+ .pcie_regs = {.phys = ZEUS_ADDR(0x200000)},
+ .tim_ch = {.phys = ZEUS_ADDR(0x282C10)},
+ .tim_cl = {.phys = ZEUS_ADDR(0x282C14)},
+ .gpio_dout = {.phys = ZEUS_ADDR(0x282c20)},
+ .gpio_din = {.phys = ZEUS_ADDR(0x282c24)},
+ .gpio_dir = {.phys = ZEUS_ADDR(0x282c2C)},
+ .watchdog = {.phys = ZEUS_ADDR(0x282c30)},
+ .front_panel = {.phys = ZEUS_ADDR(0x283800)},
};
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
index bae8288..6a88219 100644
--- a/arch/mips/powertv/asic/asic_devices.c
+++ b/arch/mips/powertv/asic/asic_devices.c
@@ -67,8 +67,8 @@
unsigned int platform_features;
unsigned int platform_family;
-const struct register_map *register_map;
-EXPORT_SYMBOL(register_map); /* Exported for testing */
+struct register_map _asic_register_map;
+EXPORT_SYMBOL(_asic_register_map); /* Exported for testing */
unsigned long asic_phy_base;
unsigned long asic_base;
EXPORT_SYMBOL(asic_base); /* Exported for testing */
@@ -418,6 +418,15 @@
{
}
+static void __init set_register_map(unsigned long phys_base,
+ const struct register_map *map)
+{
+ asic_phy_base = phys_base;
+ _asic_register_map = *map;
+ register_map_virtualize(&_asic_register_map);
+ asic_base = (unsigned long)ioremap_nocache(phys_base, ASIC_IO_SIZE);
+}
+
/**
* configure_platform - configuration based on platform type.
*/
@@ -431,10 +440,7 @@
case FAMILY_1500VZF:
platform_features = FFS_CAPABLE;
asic = ASIC_CALLIOPE;
- asic_phy_base = CALLIOPE_IO_BASE;
- register_map = &calliope_register_map;
- asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
- ASIC_IO_SIZE);
+ set_register_map(CALLIOPE_IO_BASE, &calliope_register_map);
if (platform_family == FAMILY_1500VZE) {
gp_resources = non_dvr_vze_calliope_resources;
@@ -455,10 +461,7 @@
platform_features = FFS_CAPABLE | PCIE_CAPABLE |
DISPLAY_CAPABLE;
asic = ASIC_ZEUS;
- asic_phy_base = ZEUS_IO_BASE;
- register_map = &zeus_register_map;
- asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
- ASIC_IO_SIZE);
+ set_register_map(ZEUS_IO_BASE, &zeus_register_map);
gp_resources = non_dvr_zeus_resources;
pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n");
@@ -471,11 +474,6 @@
/* The settop has PCIE but it isn't used, so don't advertise
* it*/
platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
- asic_phy_base = CRONUS_IO_BASE; /* same as Cronus */
- register_map = &cronus_register_map; /* same as Cronus */
- asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
- ASIC_IO_SIZE);
- gp_resources = non_dvr_cronuslite_resources;
/* ASIC version will determine if this is a real CronusLite or
* Castrati(Cronus) */
@@ -489,6 +487,9 @@
else
asic = ASIC_CRONUSLITE;
+ /* Cronus and Cronus Lite have the same register map */
+ set_register_map(CRONUS_IO_BASE, &cronus_register_map);
+ gp_resources = non_dvr_cronuslite_resources;
pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, "
"chipversion=0x%08X\n",
(asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE",
@@ -498,10 +499,7 @@
case FAMILY_4600VZA:
platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
asic = ASIC_CRONUS;
- asic_phy_base = CRONUS_IO_BASE;
- register_map = &cronus_register_map;
- asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
- ASIC_IO_SIZE);
+ set_register_map(CRONUS_IO_BASE, &cronus_register_map);
gp_resources = non_dvr_cronus_resources;
pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n");
@@ -512,10 +510,7 @@
platform_features = DVR_CAPABLE | PCIE_CAPABLE |
DISPLAY_CAPABLE;
asic = ASIC_ZEUS;
- asic_phy_base = ZEUS_IO_BASE;
- register_map = &zeus_register_map;
- asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
- ASIC_IO_SIZE);
+ set_register_map(ZEUS_IO_BASE, &zeus_register_map);
gp_resources = dvr_zeus_resources;
pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n");
@@ -526,10 +521,7 @@
platform_features = DVR_CAPABLE | PCIE_CAPABLE |
DISPLAY_CAPABLE;
asic = ASIC_CRONUS;
- asic_phy_base = CRONUS_IO_BASE;
- register_map = &cronus_register_map;
- asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
- ASIC_IO_SIZE);
+ set_register_map(CRONUS_IO_BASE, &cronus_register_map);
gp_resources = dvr_cronus_resources;
pr_info("Platform: 8600/Vz Class B - CRONUS, "