msm: clock-pll: Move 8930, 8064 and 9615 pll config code to clock-pll.
Code to configure PLLs and to switch them to FSM
mode has been duplicated in clock drivers for the
9615 and 8064. Move this out to the common clock-pll
driver so that the code can be re-used for these
and future targets.
Change-Id: Ia77e976d277837f5a2d344f82f05cca4261dcf9d
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 0832a03..29c947a 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -5747,32 +5747,82 @@
writel_relaxed(regval, reg);
}
-static void __init set_fsm_mode(void __iomem *mode_reg)
-{
- u32 regval = readl_relaxed(mode_reg);
+static struct pll_config_regs pll4_regs __initdata = {
+ .l_reg = LCC_PLL0_L_VAL_REG,
+ .m_reg = LCC_PLL0_M_VAL_REG,
+ .n_reg = LCC_PLL0_N_VAL_REG,
+ .config_reg = LCC_PLL0_CONFIG_REG,
+ .mode_reg = LCC_PLL0_MODE_REG,
+};
- /*De-assert reset to FSM */
- regval &= ~BIT(21);
- writel_relaxed(regval, mode_reg);
+static struct pll_config pll4_config __initdata = {
+ .l = 0xE,
+ .m = 0x27A,
+ .n = 0x465,
+ .vco_val = 0x0,
+ .vco_mask = BM(17, 16),
+ .pre_div_val = 0x0,
+ .pre_div_mask = BIT(19),
+ .post_div_val = 0x0,
+ .post_div_mask = BM(21, 20),
+ .mn_ena_val = BIT(22),
+ .mn_ena_mask = BIT(22),
+ .main_output_val = BIT(23),
+ .main_output_mask = BIT(23),
+};
- /* Program bias count */
- regval &= ~BM(19, 14);
- regval |= BVAL(19, 14, 0x1);
- writel_relaxed(regval, mode_reg);
+static struct pll_config_regs pll15_regs __initdata = {
+ .l_reg = MM_PLL3_L_VAL_REG,
+ .m_reg = MM_PLL3_M_VAL_REG,
+ .n_reg = MM_PLL3_N_VAL_REG,
+ .config_reg = MM_PLL3_CONFIG_REG,
+ .mode_reg = MM_PLL3_MODE_REG,
+};
- /* Program lock count */
- regval &= ~BM(13, 8);
- regval |= BVAL(13, 8, 0x8);
- writel_relaxed(regval, mode_reg);
+static struct pll_config pll15_config __initdata = {
+ .l = (0x24 | BVAL(31, 7, 0x620)),
+ .m = 0x1,
+ .n = 0x9,
+ .vco_val = BVAL(17, 16, 0x2),
+ .vco_mask = BM(17, 16),
+ .pre_div_val = 0x0,
+ .pre_div_mask = BIT(19),
+ .post_div_val = 0x0,
+ .post_div_mask = BM(21, 20),
+ .mn_ena_val = BIT(22),
+ .mn_ena_mask = BIT(22),
+ .main_output_val = BIT(23),
+ .main_output_mask = BIT(23),
+};
- /*Enable PLL FSM voting */
- regval |= BIT(20);
- writel_relaxed(regval, mode_reg);
-}
+static struct pll_config_regs pll14_regs __initdata = {
+ .l_reg = BB_PLL14_L_VAL_REG,
+ .m_reg = BB_PLL14_M_VAL_REG,
+ .n_reg = BB_PLL14_N_VAL_REG,
+ .config_reg = BB_PLL14_CONFIG_REG,
+ .mode_reg = BB_PLL14_MODE_REG,
+};
+
+static struct pll_config pll14_config __initdata = {
+ .l = (0x11 | BVAL(31, 7, 0x620)),
+ .m = 0x7,
+ .n = 0x9,
+ .vco_val = 0x0,
+ .vco_mask = BM(17, 16),
+ .pre_div_val = 0x0,
+ .pre_div_mask = BIT(19),
+ .post_div_val = 0x0,
+ .post_div_mask = BM(21, 20),
+ .mn_ena_val = BIT(22),
+ .mn_ena_mask = BIT(22),
+ .main_output_val = BIT(23),
+ .main_output_mask = BIT(23),
+};
static void __init reg_init(void)
{
void __iomem *imem_reg;
+
/* Deassert MM SW_RESET_ALL signal. */
writel_relaxed(0, SW_RESET_ALL_REG);
@@ -5913,40 +5963,18 @@
/* Check if PLL14 is active */
is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
- if (!is_pll_enabled) {
+ if (!is_pll_enabled)
/* Ref clk = 27MHz and program pll14 to 480MHz */
- writel_relaxed(0x00031011, BB_PLL14_L_VAL_REG);
- writel_relaxed(0x7, BB_PLL14_M_VAL_REG);
- writel_relaxed(0x9, BB_PLL14_N_VAL_REG);
-
- /*
- * Enable the main output and the MN accumulator
- * Set pre-divider and post-divider values to 1 and 1
- */
- writel_relaxed(0x00C00000, BB_PLL14_CONFIG_REG);
-
- set_fsm_mode(BB_PLL14_MODE_REG);
- }
+ configure_pll(&pll14_config, &pll14_regs, 1);
/* Program PLL15 to 975MHz with ref clk = 27MHz */
- writel_relaxed(0x31024, MM_PLL3_L_VAL_REG);
- writel_relaxed(0x1, MM_PLL3_M_VAL_REG);
- writel_relaxed(0x9, MM_PLL3_N_VAL_REG);
-
- writel_relaxed(0xC20000, MM_PLL3_CONFIG_REG);
+ configure_pll(&pll15_config, &pll15_regs, 0);
/* Check if PLL4 is active */
is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
- if (!is_pll_enabled) {
+ if (!is_pll_enabled)
/* Ref clk = 27MHz and program pll4 to 393.2160MHz */
- writel_relaxed(0xE, LCC_PLL0_L_VAL_REG);
- writel_relaxed(0x27A, LCC_PLL0_M_VAL_REG);
- writel_relaxed(0x465, LCC_PLL0_N_VAL_REG);
-
- writel_relaxed(0xC00000, LCC_PLL0_CONFIG_REG);
-
- set_fsm_mode(LCC_PLL0_MODE_REG);
- }
+ configure_pll(&pll4_config, &pll4_regs, 1);
/* Enable PLL4 source on the LPASS Primary PLL Mux */
writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG);
@@ -5961,12 +5989,12 @@
* only enable PLL main output.
*/
if (cpu_is_msm8930()) {
- writel_relaxed(0x30021, MM_PLL3_L_VAL_REG);
- writel_relaxed(0x1, MM_PLL3_M_VAL_REG);
- writel_relaxed(0x3, MM_PLL3_N_VAL_REG);
-
- writel_relaxed(0xC20000, MM_PLL3_CONFIG_REG);
- writel_relaxed(0, MM_PLL3_TEST_CTL_REG);
+ pll15_config.l = 0x21 | BVAL(31, 7, 0x600);
+ pll15_config.m = 0x1;
+ pll15_config.n = 0x3;
+ configure_pll(&pll15_config, &pll15_regs, 0);
+ /* Disable AUX and BIST outputs */
+ writel_relaxed(0, MM_PLL3_TEST_CTL_REG);
}
}
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 12d37ae..1fd9b4d 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -1689,28 +1689,51 @@
CLK_LOOKUP("q6_func_clk", q6_func_clk, NULL),
};
-static void set_fsm_mode(void __iomem *mode_reg)
-{
- u32 regval = readl_relaxed(mode_reg);
+static struct pll_config_regs pll0_regs __initdata = {
+ .l_reg = BB_PLL0_L_VAL_REG,
+ .m_reg = BB_PLL0_M_VAL_REG,
+ .n_reg = BB_PLL0_N_VAL_REG,
+ .config_reg = BB_PLL0_CONFIG_REG,
+ .mode_reg = BB_PLL0_MODE_REG,
+};
- /* De-assert reset to FSM */
- regval &= ~BIT(21);
- writel_relaxed(regval, mode_reg);
+static struct pll_config pll0_config __initdata = {
+ .l = 0xE,
+ .m = 0x3,
+ .n = 0x8,
+ .vco_val = 0x0,
+ .vco_mask = BM(17, 16),
+ .pre_div_val = 0x0,
+ .pre_div_mask = BIT(19),
+ .post_div_val = 0x0,
+ .post_div_mask = BM(21, 20),
+ .mn_ena_val = BIT(22),
+ .mn_ena_mask = BIT(22),
+ .main_output_val = BIT(23),
+ .main_output_mask = BIT(23),
+};
- /* Program bias count */
- regval &= ~BM(19, 14);
- regval |= BVAL(19, 14, 0x1);
- writel_relaxed(regval, mode_reg);
+static struct pll_config_regs pll14_regs __initdata = {
+ .l_reg = BB_PLL14_L_VAL_REG,
+ .m_reg = BB_PLL14_M_VAL_REG,
+ .n_reg = BB_PLL14_N_VAL_REG,
+ .config_reg = BB_PLL14_CONFIG_REG,
+ .mode_reg = BB_PLL14_MODE_REG,
+};
- /* Program lock count */
- regval &= ~BM(13, 8);
- regval |= BVAL(13, 8, 0x8);
- writel_relaxed(regval, mode_reg);
-
- /* Enable PLL FSM voting */
- regval |= BIT(20);
- writel_relaxed(regval, mode_reg);
-}
+static struct pll_config pll14_config __initdata = {
+ .l = 0x19,
+ .m = 0x0,
+ .n = 0x1,
+ .vco_val = 0x0,
+ .vco_mask = BM(17, 16),
+ .pre_div_val = 0x0,
+ .pre_div_mask = BIT(19),
+ .post_div_val = 0x0,
+ .post_div_mask = BM(21, 20),
+ .main_output_val = BIT(23),
+ .main_output_mask = BIT(23),
+};
/*
* Miscellaneous clock register initializations
@@ -1731,57 +1754,20 @@
is_pll_enabled = readl_relaxed(BB_PLL0_STATUS_REG) & BIT(16);
if (!is_pll_enabled) {
- writel_relaxed(0xE, BB_PLL0_L_VAL_REG);
- writel_relaxed(0x3, BB_PLL0_M_VAL_REG);
- writel_relaxed(0x8, BB_PLL0_N_VAL_REG);
-
- regval = readl_relaxed(BB_PLL0_CONFIG_REG);
-
- /* Enable the main output and the MN accumulator */
- regval |= BIT(23) | BIT(22);
-
- /* Set pre-divider and post-divider values to 1 and 1 */
- regval &= ~BIT(19);
- regval &= ~BM(21, 20);
-
- /* Set VCO frequency */
- regval &= ~BM(17, 16);
-
- writel_relaxed(regval, BB_PLL0_CONFIG_REG);
-
/* Enable AUX output */
regval = readl_relaxed(BB_PLL0_TEST_CTL_REG);
regval |= BIT(12);
writel_relaxed(regval, BB_PLL0_TEST_CTL_REG);
- set_fsm_mode(BB_PLL0_MODE_REG);
+ configure_pll(&pll0_config, &pll0_regs, 1);
}
/* Check if PLL14 is enabled in FSM mode */
is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
- if (!is_pll_enabled) {
- writel_relaxed(0x19, BB_PLL14_L_VAL_REG);
- writel_relaxed(0x0, BB_PLL14_M_VAL_REG);
- writel_relaxed(0x1, BB_PLL14_N_VAL_REG);
-
- regval = readl_relaxed(BB_PLL14_CONFIG_REG);
-
- /* Enable main output and the MN accumulator */
- regval |= BIT(23) | BIT(22);
-
- /* Set pre-divider and post-divider values to 1 and 1 */
- regval &= ~BIT(19);
- regval &= ~BM(21, 20);
-
- /* Set VCO frequency */
- regval &= ~BM(17, 16);
-
- writel_relaxed(regval, BB_PLL14_CONFIG_REG);
-
- set_fsm_mode(BB_PLL14_MODE_REG);
-
- } else if (!(readl_relaxed(BB_PLL14_MODE_REG) & BIT(20)))
+ if (!is_pll_enabled)
+ configure_pll(&pll14_config, &pll14_regs, 1);
+ else if (!(readl_relaxed(BB_PLL14_MODE_REG) & BIT(20)))
WARN(1, "PLL14 enabled in non-FSM mode!\n");
/* Detect PLL9 rate and fixup structure accordingly */
diff --git a/arch/arm/mach-msm/clock-pll.c b/arch/arm/mach-msm/clock-pll.c
index 5022811..c55fa67 100644
--- a/arch/arm/mach-msm/clock-pll.c
+++ b/arch/arm/mach-msm/clock-pll.c
@@ -42,6 +42,14 @@
((x)->status_reg))
#define PLL_MODE_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->mode_reg)) : \
((x)->mode_reg))
+#define PLL_L_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->l_reg)) : \
+ ((x)->l_reg))
+#define PLL_M_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->m_reg)) : \
+ ((x)->m_reg))
+#define PLL_N_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->n_reg)) : \
+ ((x)->n_reg))
+#define PLL_CONFIG_REG(x) ((x)->base ? (*(x)->base + (u32)((x)->config_reg)) : \
+ ((x)->config_reg))
static DEFINE_SPINLOCK(pll_reg_lock);
@@ -374,3 +382,65 @@
.handoff = pll_clk_handoff,
.is_enabled = pll_clk_is_enabled,
};
+
+static void __init __set_fsm_mode(void __iomem *mode_reg)
+{
+ u32 regval = readl_relaxed(mode_reg);
+
+ /* De-assert reset to FSM */
+ regval &= ~BIT(21);
+ writel_relaxed(regval, mode_reg);
+
+ /* Program bias count */
+ regval &= ~BM(19, 14);
+ regval |= BVAL(19, 14, 0x1);
+ writel_relaxed(regval, mode_reg);
+
+ /* Program lock count */
+ regval &= ~BM(13, 8);
+ regval |= BVAL(13, 8, 0x8);
+ writel_relaxed(regval, mode_reg);
+
+ /* Enable PLL FSM voting */
+ regval |= BIT(20);
+ writel_relaxed(regval, mode_reg);
+}
+
+void __init configure_pll(struct pll_config *config,
+ struct pll_config_regs *regs, u32 ena_fsm_mode)
+{
+ u32 regval;
+
+ writel_relaxed(config->l, PLL_L_REG(regs));
+ writel_relaxed(config->m, PLL_M_REG(regs));
+ writel_relaxed(config->n, PLL_N_REG(regs));
+
+ regval = readl_relaxed(PLL_CONFIG_REG(regs));
+
+ /* Enable the MN accumulator */
+ if (config->mn_ena_mask) {
+ regval &= ~config->mn_ena_mask;
+ regval |= config->mn_ena_val;
+ }
+
+ /* Enable the main output */
+ if (config->main_output_mask) {
+ regval &= ~config->main_output_mask;
+ regval |= config->main_output_val;
+ }
+
+ /* Set pre-divider and post-divider values */
+ regval &= ~config->pre_div_mask;
+ regval |= config->pre_div_val;
+ regval &= ~config->post_div_mask;
+ regval |= config->post_div_val;
+
+ /* Select VCO setting */
+ regval &= ~config->vco_mask;
+ regval |= config->vco_val;
+ writel_relaxed(regval, PLL_CONFIG_REG(regs));
+
+ /* Configure in FSM mode if necessary */
+ if (ena_fsm_mode)
+ __set_fsm_mode(PLL_MODE_REG(regs));
+}
diff --git a/arch/arm/mach-msm/clock-pll.h b/arch/arm/mach-msm/clock-pll.h
index 26bfc68..4ee738a 100644
--- a/arch/arm/mach-msm/clock-pll.h
+++ b/arch/arm/mach-msm/clock-pll.h
@@ -117,4 +117,31 @@
struct clk *pll_vote_clk_get_parent(struct clk *clk);
int pll_vote_clk_is_enabled(struct clk *clk);
+struct pll_config {
+ u32 l;
+ u32 m;
+ u32 n;
+ u32 vco_val;
+ u32 vco_mask;
+ u32 pre_div_val;
+ u32 pre_div_mask;
+ u32 post_div_val;
+ u32 post_div_mask;
+ u32 mn_ena_val;
+ u32 mn_ena_mask;
+ u32 main_output_val;
+ u32 main_output_mask;
+};
+
+struct pll_config_regs {
+ void __iomem *l_reg;
+ void __iomem *m_reg;
+ void __iomem *n_reg;
+ void __iomem *config_reg;
+ void __iomem *mode_reg;
+ void *const __iomem *base;
+};
+
+void __init configure_pll(struct pll_config *, struct pll_config_regs *, u32);
+
#endif