msm: kgsl: add adreno225 support
The adreno220 specific registers and setting are all used
on adreno225. Also there is a a225 specific setting setting
for REG_SQ_FLOW_CONTROl at startup to enable the larger
instruction store found on this gpu.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
diff --git a/drivers/gpu/msm/a200_reg.h b/drivers/gpu/msm/a200_reg.h
index 2bd4902..5f260ec 100644
--- a/drivers/gpu/msm/a200_reg.h
+++ b/drivers/gpu/msm/a200_reg.h
@@ -364,6 +364,7 @@
#define REG_SQ_CF_BOOLEANS 0x4900
#define REG_SQ_CF_LOOP 0x4908
#define REG_SQ_GPR_MANAGEMENT 0x0D00
+#define REG_SQ_FLOW_CONTROL 0x0D01
#define REG_SQ_INST_STORE_MANAGMENT 0x0D02
#define REG_SQ_INT_ACK 0x0D36
#define REG_SQ_INT_CNTL 0x0D34
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index d5d6a1d..43fd5ee 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -137,7 +137,7 @@
rb_edram_info.val = 0;
rb_edram_info.f.edram_size = edram_value;
- if (!adreno_is_a220(adreno_dev))
+ if (!adreno_is_a22x(adreno_dev))
rb_edram_info.f.edram_mapping_mode = 0; /* EDRAM_MAP_UPPER */
/* must be aligned to size */
@@ -283,7 +283,7 @@
}
if (flags & KGSL_MMUFLAGS_PTUPDATE &&
- !adreno_is_a220(adreno_dev)) {
+ adreno_is_a20x(adreno_dev)) {
/* HW workaround: to resolve MMU page fault interrupts
* caused by the VGT.It prevents the CP PFP from filling
* the VGT DMA request fifo too early,thereby ensuring
@@ -507,7 +507,7 @@
/* Only reset CP block if all blocks have previously been reset */
if (!(device->flags & KGSL_FLAGS_SOFT_RESET) ||
- !adreno_is_a220(adreno_dev)) {
+ !adreno_is_a22x(adreno_dev)) {
adreno_regwrite(device, REG_RBBM_SOFT_RESET, 0xFFFFFFFF);
device->flags |= KGSL_FLAGS_SOFT_RESET;
} else
@@ -522,11 +522,16 @@
adreno_regwrite(device, REG_RBBM_CNTL, 0x00004442);
+ if (adreno_is_a225(adreno_dev)) {
+ /* Enable large instruction store for A225 */
+ adreno_regwrite(device, REG_SQ_FLOW_CONTROL, 0x18000000);
+ }
+
adreno_regwrite(device, REG_SQ_VS_PROGRAM, 0x00000000);
adreno_regwrite(device, REG_SQ_PS_PROGRAM, 0x00000000);
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0);
- if (!adreno_is_a220(adreno_dev))
+ if (!adreno_is_a22x(adreno_dev))
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0);
else
adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0x80);
@@ -543,7 +548,7 @@
adreno_regwrite(device, REG_CP_INT_CNTL, 0);
adreno_regwrite(device, REG_SQ_INT_CNTL, 0);
- if (adreno_is_a220(adreno_dev))
+ if (adreno_is_a22x(adreno_dev))
adreno_dev->gmemspace.sizebytes = SZ_512K;
else
adreno_dev->gmemspace.sizebytes = SZ_256K;
diff --git a/drivers/gpu/msm/adreno_a2xx.c b/drivers/gpu/msm/adreno_a2xx.c
index 96b4ae6..f5f6f70 100644
--- a/drivers/gpu/msm/adreno_a2xx.c
+++ b/drivers/gpu/msm/adreno_a2xx.c
@@ -463,7 +463,7 @@
const unsigned int *ptr_register_ranges;
/* Based on chip id choose the register ranges */
- if (adreno_is_a220(adreno_dev)) {
+ if (adreno_is_a22x(adreno_dev)) {
ptr_register_ranges = register_ranges_a22x;
reg_array_size = ARRAY_SIZE(register_ranges_a22x);
} else {
@@ -535,7 +535,7 @@
*cmd++ = REG_TP0_CHICKEN;
*cmd++ = tmp_ctx.reg_values[1];
- if (adreno_is_a220(adreno_dev)) {
+ if (adreno_is_a22x(adreno_dev)) {
unsigned int i;
unsigned int j = 2;
for (i = REG_LEIA_VSC_BIN_SIZE; i <=
@@ -640,7 +640,7 @@
/* SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
*cmds++ = PM4_REG(REG_SQ_PROGRAM_CNTL);
- if (adreno_is_a220(adreno_dev))
+ if (adreno_is_a22x(adreno_dev))
*cmds++ = 0x10018001;
else
*cmds++ = 0x10010001;
@@ -671,7 +671,7 @@
/* disable Z */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
*cmds++ = PM4_REG(REG_RB_DEPTHCONTROL);
- if (adreno_is_a220(adreno_dev))
+ if (adreno_is_a22x(adreno_dev))
*cmds++ = 0x08;
else
*cmds++ = 0;
@@ -745,7 +745,7 @@
*cmds++ = PM4_REG(REG_PA_CL_CLIP_CNTL);
*cmds++ = 0x00010000;
- if (adreno_is_a220(adreno_dev)) {
+ if (adreno_is_a22x(adreno_dev)) {
*cmds++ = pm4_type3_packet(PM4_SET_DRAW_INIT_FLAGS, 1);
*cmds++ = 0;
@@ -845,7 +845,7 @@
*cmds++ = PM4_REG(REG_PA_SC_AA_MASK);
*cmds++ = 0x0000ffff; /* REG_PA_SC_AA_MASK */
- if (!adreno_is_a220(adreno_dev)) {
+ if (!adreno_is_a22x(adreno_dev)) {
/* PA_SC_VIZ_QUERY */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
*cmds++ = PM4_REG(REG_PA_SC_VIZ_QUERY);
@@ -912,7 +912,7 @@
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
*cmds++ = PM4_REG(REG_RB_DEPTHCONTROL);
- if (adreno_is_a220(adreno_dev))
+ if (adreno_is_a22x(adreno_dev))
*cmds++ = 8; /* disable Z */
else
*cmds++ = 0; /* disable Z */
@@ -964,7 +964,7 @@
*cmds++ = PM4_REG(REG_PA_CL_CLIP_CNTL);
*cmds++ = 0x00010000;
- if (adreno_is_a220(adreno_dev)) {
+ if (adreno_is_a22x(adreno_dev)) {
*cmds++ = pm4_type3_packet(PM4_SET_DRAW_INIT_FLAGS, 1);
*cmds++ = 0;
@@ -1024,7 +1024,7 @@
#endif
/* Based on chip id choose the registers ranges*/
- if (adreno_is_a220(adreno_dev)) {
+ if (adreno_is_a22x(adreno_dev)) {
ptr_register_ranges = register_ranges_a22x;
reg_array_size = ARRAY_SIZE(register_ranges_a22x);
} else {
@@ -1061,7 +1061,7 @@
tmp_ctx.reg_values[1] = virt2gpu(cmd, &drawctxt->gpustate);
*cmd++ = 0x00000000;
- if (adreno_is_a220(adreno_dev)) {
+ if (adreno_is_a22x(adreno_dev)) {
unsigned int i;
unsigned int j = 2;
for (i = REG_LEIA_VSC_BIN_SIZE; i <=
@@ -1485,10 +1485,11 @@
context->shader_restore, 3);
}
- cmds[0] = pm4_type3_packet(PM4_SET_BIN_BASE_OFFSET, 1);
- cmds[1] = context->bin_base_offset;
- if (!adreno_is_a220(adreno_dev))
+ if (adreno_is_a20x(adreno_dev)) {
+ cmds[0] = pm4_type3_packet(PM4_SET_BIN_BASE_OFFSET, 1);
+ cmds[1] = context->bin_base_offset;
adreno_ringbuffer_issuecmds(device, 0, cmds, 2);
+ }
}
/*