commit 5bb7ece4d4b02ca96330571837117f5e61e52096
author Jeremy Gebben <jgebben@codeaurora.org> Tue Aug 02 11:04:48 2011 -0600
committer Bryan Huntsman <bryanh@codeaurora.org> Mon Oct 03 10:27:50 2011 -0700
tree 6bf961efb6205d07f1932a6dbfdc82ff4ce9523d
parent 492049ec4f59bf04275878a9d16ae20528159636

msm: kgsl: add adreno225 support

The adreno220 specific registers and setting are all used
on adreno225.  Also there is a a225 specific setting setting
for REG_SQ_FLOW_CONTROl at startup to enable the larger
instruction store found on this gpu.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>

drivers/gpu/msm/adreno.c

diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index d5d6a1d..43fd5ee 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -137,7 +137,7 @@
 	rb_edram_info.val = 0;
 
 	rb_edram_info.f.edram_size = edram_value;
-	if (!adreno_is_a220(adreno_dev))
+	if (!adreno_is_a22x(adreno_dev))
 		rb_edram_info.f.edram_mapping_mode = 0; /* EDRAM_MAP_UPPER */
 
 	/* must be aligned to size */
@@ -283,7 +283,7 @@
 		}
 
 		if (flags & KGSL_MMUFLAGS_PTUPDATE &&
-			!adreno_is_a220(adreno_dev)) {
+			adreno_is_a20x(adreno_dev)) {
 			/* HW workaround: to resolve MMU page fault interrupts
 			* caused by the VGT.It prevents the CP PFP from filling
 			* the VGT DMA request fifo too early,thereby ensuring
@@ -507,7 +507,7 @@
 
 	/* Only reset CP block if all blocks have previously been reset */
 	if (!(device->flags & KGSL_FLAGS_SOFT_RESET) ||
-		!adreno_is_a220(adreno_dev)) {
+		!adreno_is_a22x(adreno_dev)) {
 		adreno_regwrite(device, REG_RBBM_SOFT_RESET, 0xFFFFFFFF);
 		device->flags |= KGSL_FLAGS_SOFT_RESET;
 	} else
@@ -522,11 +522,16 @@
 
 	adreno_regwrite(device, REG_RBBM_CNTL, 0x00004442);
 
+	if (adreno_is_a225(adreno_dev)) {
+		/* Enable large instruction store for A225 */
+		adreno_regwrite(device, REG_SQ_FLOW_CONTROL, 0x18000000);
+	}
+
 	adreno_regwrite(device, REG_SQ_VS_PROGRAM, 0x00000000);
 	adreno_regwrite(device, REG_SQ_PS_PROGRAM, 0x00000000);
 
 	adreno_regwrite(device, REG_RBBM_PM_OVERRIDE1, 0);
-	if (!adreno_is_a220(adreno_dev))
+	if (!adreno_is_a22x(adreno_dev))
 		adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0);
 	else
 		adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0x80);
@@ -543,7 +548,7 @@
 	adreno_regwrite(device, REG_CP_INT_CNTL, 0);
 	adreno_regwrite(device, REG_SQ_INT_CNTL, 0);
 
-	if (adreno_is_a220(adreno_dev))
+	if (adreno_is_a22x(adreno_dev))
 		adreno_dev->gmemspace.sizebytes = SZ_512K;
 	else
 		adreno_dev->gmemspace.sizebytes = SZ_256K;