crypto: Add support for larger ce block size
Adds support for CE block size larger than 16 bytes
by setting appropriate bits in CRYPTO_CONFIG register.
NOTE: This bits are functional in rev 4.2 and higher
of the CE hardware. Setting the bits in 4.0 HW does not
do anything.
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
diff --git a/drivers/crypto/msm/qce40.h b/drivers/crypto/msm/qce40.h
index 4ec6ecc2..c9fbb17 100644
--- a/drivers/crypto/msm/qce40.h
+++ b/drivers/crypto/msm/qce40.h
@@ -34,8 +34,8 @@
SET_LAST_CMD_PTR((GET_PHYS_ADDR((unsigned char *)x)))
-/* Data xfer between DM and CE in blocks of 16 bytes */
-#define ADM_CE_BLOCK_SIZE 16
+/* MAX Data xfer block size between DM and CE */
+#define MAX_ADM_CE_BLOCK_SIZE 64
#define ADM_DESC_LENGTH_MASK 0xffff
#define ADM_DESC_LENGTH(x) (x & ADM_DESC_LENGTH_MASK)
@@ -111,7 +111,7 @@
unsigned char go_proc[CRYPTO_REG_SIZE];
unsigned char status[CRYPTO_REG_SIZE];
- unsigned char pad[2 * ADM_CE_BLOCK_SIZE];
+ unsigned char pad[2 * MAX_ADM_CE_BLOCK_SIZE];
};
/* CE Command lists */
@@ -225,6 +225,8 @@
int ce_in_src_desc_index;
int ce_in_dst_desc_index;
+ int ce_block_size;
+
dma_addr_t phy_ce_out_ignore;
dma_addr_t phy_ce_pad;