[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.
Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 3d033e1..d96f821 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1435,6 +1435,9 @@
flush_icache_range(ebase + offset, ebase + offset + size);
}
+static char panic_null_cerr[] __initdata =
+ "Trying to set NULL cache error exception handler";
+
/* Install uncached CPU exception handler */
void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
{
@@ -1445,6 +1448,9 @@
unsigned long uncached_ebase = TO_UNCAC(ebase);
#endif
+ if (!addr)
+ panic(panic_null_cerr);
+
memcpy((void *)(uncached_ebase + offset), addr, size);
}