msm: cache_erp: Print hardware info on cache errors
Information such as current CPU voltage and frequency, PTE
fuses, MIDR, and PMIC voltage set point may be helpful when
debugging cache errors.
Change-Id: I94b6199eaba22db5e0411ee1d4af9f70024249c3
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
diff --git a/arch/arm/mach-msm/cache_erp.c b/arch/arm/mach-msm/cache_erp.c
index 9a721e4..97225ac 100644
--- a/arch/arm/mach-msm/cache_erp.c
+++ b/arch/arm/mach-msm/cache_erp.c
@@ -17,7 +17,11 @@
#include <linux/errno.h>
#include <linux/proc_fs.h>
#include <linux/cpu.h>
+#include <linux/io.h>
#include <mach/msm-krait-l2-accessors.h>
+#include <mach/msm_iomap.h>
+#include <asm/cputype.h>
+#include "acpuclock.h"
#define CESR_DCTPE BIT(0)
#define CESR_DCDPE BIT(1)
@@ -193,11 +197,25 @@
struct msm_l1_err_stats *l1_stats = dev_id;
unsigned int cesr = read_cesr();
unsigned int i_cesynr, d_cesynr;
+ unsigned int cpu = smp_processor_id();
int print_regs = cesr & CESR_PRINT_MASK;
+ void *const saw_bases[] = {
+ MSM_SAW0_BASE,
+ MSM_SAW1_BASE,
+ MSM_SAW2_BASE,
+ MSM_SAW3_BASE,
+ };
+
if (print_regs) {
- pr_alert("L1 Error detected on CPU %d!\n", smp_processor_id());
- pr_alert("\tCESR = 0x%08x\n", cesr);
+ pr_alert("L1 / TLB Error detected on CPU %d!\n", cpu);
+ pr_alert("\tCESR = 0x%08x\n", cesr);
+ pr_alert("\tCPU speed = %lu\n", acpuclk_get_rate(cpu));
+ pr_alert("\tMIDR = 0x%08x\n", read_cpuid_id());
+ pr_alert("\tPTE fuses = 0x%08x\n",
+ readl_relaxed(MSM_QFPROM_BASE + 0xC0));
+ pr_alert("\tPMIC_VREG = 0x%08x\n",
+ readl_relaxed(saw_bases[cpu] + 0x14));
}
if (cesr & CESR_DCTPE) {