msm: gdsc: Delay 1us after enabling rails while clocks are re-enabled
The GDSC state-machine will temporarily disable clocks to a power
domain while the core reset sequence is performed. After power is
enabled, the clocks will take 4 cycles to re-enable.
This scenario only occurs if gdsc_enable() is called while clocks are
enabled. While this is not the recommended order for device drivers
to perform these steps, the 1us delay is added here just in case
the recommendation is not followed.
Change-Id: Ieff39755561b6f82731747cf0984d8d401001060
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/gdsc.c b/arch/arm/mach-msm/gdsc.c
index df3a92d..f91e3dc 100644
--- a/arch/arm/mach-msm/gdsc.c
+++ b/arch/arm/mach-msm/gdsc.c
@@ -63,10 +63,18 @@
ret = readl_tight_poll_timeout(sc->gdscr, regval, regval & PWR_ON_MASK,
TIMEOUT_US);
- if (ret)
+ if (ret) {
dev_err(&rdev->dev, "%s enable timed out\n", sc->rdesc.name);
+ return ret;
+ }
- return ret;
+ /*
+ * If clocks to this power domain were already on, they will take an
+ * additional 4 clock cycles to re-enable after the rail is enabled.
+ */
+ udelay(1);
+
+ return 0;
}
static int gdsc_disable(struct regulator_dev *rdev)