msm: clock: Move out pll code from clock-local.c to clock-pll.c
The new clock-pll driver is designed to control
PLL clocks including shared, locally controlled
and voteable PLLs. Move PLL code from clock-local.c
into this new driver.
Change-Id: I58fc0c7e4816e52d25dd2521a70baff52d8a74b2
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 89cde6d..ca5a63d 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -33,6 +33,7 @@
#include "clock-voter.h"
#include "clock-dss-8960.h"
#include "devices.h"
+#include "clock-pll.h"
#define REG(off) (MSM_CLK_CTL_BASE + (off))
#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
@@ -478,7 +479,7 @@
.c = {
.dbg_name = "pll2_clk",
.rate = 800000000,
- .ops = &clk_ops_pll,
+ .ops = &clk_ops_local_pll,
CLK_INIT(pll2_clk.c),
.warned = true,
},
@@ -490,7 +491,7 @@
.c = {
.dbg_name = "pll3_clk",
.rate = 1200000000,
- .ops = &clk_ops_pll,
+ .ops = &clk_ops_local_pll,
.vdd_class = &vdd_sr2_pll,
.fmax[VDD_SR2_PLL_ON] = ULONG_MAX,
CLK_INIT(pll3_clk.c),
@@ -502,6 +503,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(4),
.status_reg = LCC_PLL0_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll4_clk",
@@ -516,6 +518,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll8_clk",
@@ -530,6 +533,7 @@
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(14),
.status_reg = BB_PLL14_STATUS_REG,
+ .status_mask = BIT(16),
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll14_clk",
@@ -546,7 +550,7 @@
.c = {
.dbg_name = "pll15_clk",
.rate = 975000000,
- .ops = &clk_ops_pll,
+ .ops = &clk_ops_local_pll,
CLK_INIT(pll15_clk.c),
.warned = true,
},
@@ -6032,7 +6036,7 @@
vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
- clk_ops_pll.enable = sr_pll_clk_enable;
+ clk_ops_local_pll.enable = sr_pll_clk_enable;
/* Initialize clock registers. */
reg_init();