)]}'
{
  "commit": "68477d11769ce8c6830523f08637894c43885c7e",
  "tree": "a2e36829cc638c37e673a749306e31226d0ee2da",
  "parents": [
    "7eb9b2f56c9812d03ac63031869bcc42151067b1"
  ],
  "author": {
    "name": "David Vrabel",
    "email": "dvrabel@arcom.com",
    "time": "Wed Jan 18 22:38:44 2006 +0000"
  },
  "committer": {
    "name": "Russell King",
    "email": "rmk+kernel@arm.linux.org.uk",
    "time": "Wed Jan 18 22:38:44 2006 +0000"
  },
  "message": "[ARM] 3267/1: PXA27x SSP controller register defines\n\nPatch from David Vrabel\n\nPXA27x SSP controller has a few different registers, including SCR (serial clock rate) in SSCR0.\n\nSigned-off-by: David Vrabel \u003cdvrabel@arcom.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "dae138b9cac5033470efe6284a3fa6d51b34db1b",
      "old_mode": 33188,
      "old_path": "include/asm-arm/arch-pxa/pxa-regs.h",
      "new_id": "1409c5bd703f0ae30911bfde802b59255a49739a",
      "new_mode": 33188,
      "new_path": "include/asm-arm/arch-pxa/pxa-regs.h"
    }
  ]
}