| commit | 684f741446f7a3108b4c167faf20214c42b7eeac | [log] [tgz] |
|---|---|---|
| author | Zhiwu Song <zhiwu.song@csr.com> | Tue Aug 30 19:20:34 2011 -0700 |
| committer | Barry Song <21cnbao@gmail.com> | Sun Sep 11 09:17:53 2011 +0800 |
| tree | 7d6b2d4919640170f61aaaf5460e9b2a6dbb24cd | |
| parent | 858ba703e842f4ece6680b45862ee9e6e6297d1e [diff] |
ARM: CSR: add rtc i/o bridge interface for SiRFprimaII The module is a bridge between the RTC clock domain and the CPU interface clock domain. ARM access the register of SYSRTC, GPSRTC and PWRC through this module. Signed-off-by: Zhiwu Song <zhiwu.song@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Acked-by: Arnd Bergmann <arnd@arndb.de>