)]}'
{
  "commit": "6c2b374d74857e892080ee726184ec1d15e7d4e4",
  "tree": "c107532c288bcede80e45ebc3e46292bfaf0cea2",
  "parents": [
    "48408157ebf5b2c6dc1e04ba5d258012f6a7f356"
  ],
  "author": {
    "name": "Zhang, Yanmin",
    "email": "yanmin.zhang@intel.com",
    "time": "Mon Jul 31 15:21:33 2006 +0800"
  },
  "committer": {
    "name": "Greg Kroah-Hartman",
    "email": "gregkh@suse.de",
    "time": "Tue Sep 26 17:43:53 2006 -0700"
  },
  "message": "PCI-Express AER implemetation: AER core and aerdriver\n\nPatch 3 implements the core part of PCI-Express AER and aerdrv\nport service driver.\n\nWhen a root port service device is probed, the aerdrv will call\nrequest_irq to register irq handler for AER error interrupt.\n\nWhen a device sends an PCI-Express error message to the root port,\nthe root port will trigger an interrupt, by either MSI or IO-APIC,\nthen kernel would run the irq handler. The handler collects root\nerror status register and schedules a work. The work will call\nthe core part to process the error based on its type\n(Correctable/non-fatal/fatal).\n\nAs for Correctable errors, the patch chooses to just clear the correctable\nerror status register of the device.\n\nAs for the non-fatal error, the patch follows generic PCI error handler\nrules to call the error callback functions of the endpoint\u0027s driver. If\nthe device is a bridge, the patch chooses to broadcast the error to\ndownstream devices.\n\nAs for the fatal error, the patch resets the pci-express link and\nfollows generic PCI error handler rules to call the error callback\nfunctions of the endpoint\u0027s driver. If the device is a bridge, the patch\nchooses to broadcast the error to downstream devices.\n\nSigned-off-by: Zhang Yanmin \u003cyanmin.zhang@intel.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n",
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