msm: acpuclock: Implement acpuclock APIs through function pointers
Create a generic wrapper acpuclock driver in acpuclock.c to call
SoC-specific function pointer API implementations. With the
exception of iomap conflicts, this should allow multiple acpuclock
driver implementations to be compiled into the same kernel binary.
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Conflicts:
arch/arm/mach-msm/acpuclock-7201.c
arch/arm/mach-msm/board-msm8960.c
diff --git a/arch/arm/mach-msm/acpuclock-8x50.c b/arch/arm/mach-msm/acpuclock-8x50.c
index 1b2416a..be0cf5b 100644
--- a/arch/arm/mach-msm/acpuclock-8x50.c
+++ b/arch/arm/mach-msm/acpuclock-8x50.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -114,11 +114,11 @@
/* Use 128MHz for PC since ACPU will auto-switch to AXI (128MHz) before
* coming back up. This allows detection of return-from-PC, since 128MHz
* is only used for power collapse. */
-#define POWER_COLLAPSE_KHZ (AXI_S->acpuclk_khz)
+#define POWER_COLLAPSE_KHZ 128000
/* Use 245MHz (not 128MHz) for SWFI to avoid unnecessary steps between
* 128MHz<->245MHz. Jumping to high frequencies from 128MHz directly
* is not allowed. */
-#define WAIT_FOR_IRQ_KHZ (PLL0_S->acpuclk_khz)
+#define WAIT_FOR_IRQ_KHZ 245760
#ifdef CONFIG_CPU_FREQ_MSM
static struct cpufreq_frequency_table freq_table[20];
@@ -155,8 +155,6 @@
struct clock_state {
struct clkctl_acpu_speed *current_speed;
struct mutex lock;
- uint32_t acpu_switch_time_us;
- uint32_t max_speed_delta_khz;
uint32_t vdd_switch_time_us;
unsigned int max_vdd;
struct clk *ebi1_clk;
@@ -391,7 +389,8 @@
}
}
-int acpuclk_set_rate(int cpu, unsigned long rate, enum setrate_reason reason)
+static int acpuclk_8x50_set_rate(int cpu, unsigned long rate,
+ enum setrate_reason reason)
{
struct clkctl_acpu_speed *tgt_s, *strt_s;
int res, rc = 0;
@@ -500,7 +499,7 @@
return rc;
}
-static void __init acpuclk_init(void)
+static void __init acpuclk_hw_init(void)
{
struct clkctl_acpu_speed *speed;
uint32_t div, sel, regval;
@@ -567,30 +566,11 @@
pr_info("ACPU running at %d KHz\n", speed->acpuclk_khz);
}
-unsigned long acpuclk_get_rate(int cpu)
+static unsigned long acpuclk_8x50_get_rate(int cpu)
{
return drv_state.current_speed->acpuclk_khz;
}
-uint32_t acpuclk_get_switch_time(void)
-{
- return drv_state.acpu_switch_time_us;
-}
-
-unsigned long acpuclk_power_collapse(void)
-{
- int ret = acpuclk_get_rate(smp_processor_id());
- acpuclk_set_rate(smp_processor_id(), POWER_COLLAPSE_KHZ, SETRATE_PC);
- return ret;
-}
-
-unsigned long acpuclk_wait_for_irq(void)
-{
- int ret = acpuclk_get_rate(smp_processor_id());
- acpuclk_set_rate(smp_processor_id(), WAIT_FOR_IRQ_KHZ, SETRATE_SWFI);
- return ret;
-}
-
/* Spare register populated with efuse data on max ACPU freq. */
#define CT_CSR_PHYS 0xA8700000
#define TCSR_SPARE2_ADDR (ct_csr_base + 0x60)
@@ -689,11 +669,17 @@
}
#endif
-void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
+static struct acpuclk_data acpuclk_8x50_data = {
+ .set_rate = acpuclk_8x50_set_rate,
+ .get_rate = acpuclk_8x50_get_rate,
+ .power_collapse_khz = POWER_COLLAPSE_KHZ,
+ .wait_for_irq_khz = WAIT_FOR_IRQ_KHZ,
+};
+
+int __init acpuclk_8x50_init(struct acpuclk_platform_data *clkdata)
{
mutex_init(&drv_state.lock);
- drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us;
- drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz;
+ acpuclk_8x50_data.switch_time_us = clkdata->acpu_switch_time_us;
drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
drv_state.max_vdd = clkdata->max_vdd;
drv_state.acpu_set_vdd = clkdata->acpu_set_vdd;
@@ -702,13 +688,15 @@
BUG_ON(IS_ERR(drv_state.ebi1_clk));
acpu_freq_tbl_fixup();
- acpuclk_init();
+ acpuclk_hw_init();
lpj_init();
/* Set a lower bound for ACPU rate for boot. This limits the
* maximum frequency hop caused by the first CPUFREQ switch. */
if (drv_state.current_speed->acpuclk_khz < PLL0_S->acpuclk_khz)
acpuclk_set_rate(0, PLL0_S->acpuclk_khz, SETRATE_CPUFREQ);
+ acpuclk_register(&acpuclk_8x50_data);
+
#ifdef CONFIG_CPU_FREQ_MSM
cpufreq_table_init();
cpufreq_frequency_table_get_attr(freq_table, smp_processor_id());
@@ -720,4 +708,5 @@
drv_state.acpu_set_vdd = NULL;
}
#endif
+ return 0;
}