msm: clock-dss-8960: Update HDMI PLL settings
Update the HDMI PLL register settings for all the supported
frequencies to address the issue of HDMI PLL not getting
locked sporadically.
Change-Id: I033f70f11f406a6be0de7e1a2286d9ad17cc0064
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-dss-8960.c b/arch/arm/mach-msm/clock-dss-8960.c
index 49b6cf7..d9ad103 100644
--- a/arch/arm/mach-msm/clock-dss-8960.c
+++ b/arch/arm/mach-msm/clock-dss-8960.c
@@ -236,24 +236,19 @@
switch (rate) {
case 27030000:
/* 480p60/480i60 case */
- writel_relaxed(0x32, HDMI_PHY_PLL_REFCLK_CFG);
+ writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
+ writel_relaxed(0x38, HDMI_PHY_PLL_REFCLK_CFG);
writel_relaxed(0x2, HDMI_PHY_PLL_CHRG_PUMP_CFG);
- writel_relaxed(0x08, HDMI_PHY_PLL_LOOP_FLT_CFG0);
- writel_relaxed(0x77, HDMI_PHY_PLL_LOOP_FLT_CFG1);
- writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
- writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
- writel_relaxed(0x7b, HDMI_PHY_PLL_SDM_CFG0);
- writel_relaxed(0x01, HDMI_PHY_PLL_SDM_CFG1);
- writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG2);
- writel_relaxed(0xC0, HDMI_PHY_PLL_SDM_CFG3);
+ writel_relaxed(0x20, HDMI_PHY_PLL_LOOP_FLT_CFG0);
+ writel_relaxed(0xFF, HDMI_PHY_PLL_LOOP_FLT_CFG1);
+ writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG0);
+ writel_relaxed(0x4E, HDMI_PHY_PLL_SDM_CFG1);
+ writel_relaxed(0xD7, HDMI_PHY_PLL_SDM_CFG2);
+ writel_relaxed(0x03, HDMI_PHY_PLL_SDM_CFG3);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG4);
- writel_relaxed(0x9A, HDMI_PHY_PLL_SSC_CFG0);
- writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
- writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
- writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG3);
writel_relaxed(0x2A, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x03, HDMI_PHY_PLL_VCOCAL_CFG1);
- writel_relaxed(0x2B, HDMI_PHY_PLL_VCOCAL_CFG2);
+ writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
@@ -269,6 +264,7 @@
writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
+ writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x77, HDMI_PHY_PLL_SDM_CFG0);
writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG1);
writel_relaxed(0x00, HDMI_PHY_PLL_SDM_CFG2);
@@ -278,9 +274,12 @@
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
writel_relaxed(0x20, HDMI_PHY_PLL_SSC_CFG3);
+ writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
+ writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
+ writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
writel_relaxed(0xF4, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
- writel_relaxed(0x2B, HDMI_PHY_PLL_VCOCAL_CFG2);
+ writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
@@ -296,6 +295,7 @@
writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
+ writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x7B, HDMI_PHY_PLL_SDM_CFG0);
writel_relaxed(0x01, HDMI_PHY_PLL_SDM_CFG1);
writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG2);
@@ -305,9 +305,12 @@
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG3);
+ writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
+ writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
+ writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
writel_relaxed(0x2a, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x03, HDMI_PHY_PLL_VCOCAL_CFG1);
- writel_relaxed(0x2B, HDMI_PHY_PLL_VCOCAL_CFG2);
+ writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);
@@ -319,12 +322,14 @@
/* 720p60/720p50/1080i60/1080i50
* 1080p24/1080p30/1080p25 case
*/
+ writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x12, HDMI_PHY_PLL_REFCLK_CFG);
writel_relaxed(0x01, HDMI_PHY_PLL_LOOP_FLT_CFG0);
writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel_relaxed(0x76, HDMI_PHY_PLL_SDM_CFG0);
writel_relaxed(0xE6, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
+ writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
break;
case 148500000:
@@ -335,6 +340,7 @@
writel_relaxed(0x33, HDMI_PHY_PLL_LOOP_FLT_CFG1);
writel_relaxed(0x2C, HDMI_PHY_PLL_IDAC_ADJ_CFG);
writel_relaxed(0x6, HDMI_PHY_PLL_I_VI_KVCO_CFG);
+ writel_relaxed(0xA, HDMI_PHY_PLL_PWRDN_B);
writel_relaxed(0x76, HDMI_PHY_PLL_SDM_CFG0);
writel_relaxed(0x01, HDMI_PHY_PLL_SDM_CFG1);
writel_relaxed(0x4C, HDMI_PHY_PLL_SDM_CFG2);
@@ -344,9 +350,12 @@
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG1);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_SSC_CFG3);
+ writel_relaxed(0x10, HDMI_PHY_PLL_LOCKDET_CFG0);
+ writel_relaxed(0x1A, HDMI_PHY_PLL_LOCKDET_CFG1);
+ writel_relaxed(0x0D, HDMI_PHY_PLL_LOCKDET_CFG2);
writel_relaxed(0xe6, HDMI_PHY_PLL_VCOCAL_CFG0);
writel_relaxed(0x02, HDMI_PHY_PLL_VCOCAL_CFG1);
- writel_relaxed(0x2B, HDMI_PHY_PLL_VCOCAL_CFG2);
+ writel_relaxed(0x3B, HDMI_PHY_PLL_VCOCAL_CFG2);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG3);
writel_relaxed(0x86, HDMI_PHY_PLL_VCOCAL_CFG4);
writel_relaxed(0x00, HDMI_PHY_PLL_VCOCAL_CFG5);