ARM: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes
The linker script assumes a cacheline size of 32 bytes when aligning
the .data..cacheline_aligned and .data..percpu sections.
This patch updates the script to use L1_CACHE_BYTES, which should be set
to 64 on platforms that require it.
Change-Id: I6f760c6945138ab8872df2e15c295847077547c8
Signed-off-by: Will Deacon <will.deacon@arm.com>
[stepanm@codeaurora.org: resolved merge conflict]
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 6530fa3..8d71217 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -4,13 +4,14 @@
*/
#include <asm-generic/vmlinux.lds.h>
+#include <asm/cache.h>
#include <asm/thread_info.h>
#include <asm/memory.h>
#include <asm/page.h>
#ifdef CONFIG_STRICT_MEMORY_RWX
#include <asm/pgtable.h>
#endif
-
+
#define PROC_INFO \
VMLINUX_SYMBOL(__proc_info_begin) = .; \
*(.proc.info.init) \
@@ -86,7 +87,7 @@
#endif
}
- PERCPU_SECTION(32)
+ PERCPU_SECTION(L1_CACHE_BYTES)
#ifndef CONFIG_XIP_KERNEL
. = ALIGN(PAGE_SIZE);
@@ -194,7 +195,7 @@
#endif
NOSAVE_DATA
- CACHELINE_ALIGNED_DATA(32)
+ CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
READ_MOSTLY_DATA(32)
/*